CN201725273U - System of multiprocessor architecture on low energy consumption plate - Google Patents
System of multiprocessor architecture on low energy consumption plate Download PDFInfo
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- CN201725273U CN201725273U CN2010202827919U CN201020282791U CN201725273U CN 201725273 U CN201725273 U CN 201725273U CN 2010202827919 U CN2010202827919 U CN 2010202827919U CN 201020282791 U CN201020282791 U CN 201020282791U CN 201725273 U CN201725273 U CN 201725273U
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Abstract
The utility model discloses a system of a multiprocessor architecture on a low energy consumption plate, which comprises a processor part and a memory part. The two parts are integrated on a plate; the processor and the processor, and the processor part and the memory part are communicated through an optical fiber bus. A processor in the system is capable of managing a plurality of external devices synchronously; each processor is connected with one memory or is not connected with the memory; and a processor forms a node independently or forms a node with the memory connected therewith. The node and the external devices show a one-to-many connection relationship. The processor of the utility model is capable of synchronizing a clock of each processor by employing a layout of regular polyhedron. Each processor has clear division of labor and no impact on each other, independently finishes a specific treatment operation, shows a one-to-many connection with the external devices, and is capable of realizing distributed computing. Moreover, the system realizes the reasonable calling and distribution of the processor to the maximum extent and reduces the energy consumption. The system has the advantages of good communication quality, low energy consumption, light weight and strong anti-jamming capability.
Description
Technical field
The present invention relates to the architecture system in computer architecture field, more particularly, relate to the system of multiple processor structure on a kind of plate of low energy consumption of integrated distributed computing technology, network technology and optical communication technique.
Background technology
The multithread row is polycaryon processor on present PC (Personal Computer) market, and single core processor has been the product that is in the stage of eliminating.Can cause integrated difficulty owing on monokaryon, improve to handle frequency, and power consumption uprises, the heat radiation difficulty, the multinuclear treatment technology has become present main flow.No matter being supercomputer or common PC now, all is the processor architecture that belongs to multinuclear.Common PC adopts SMP (Symmetrical Multi-Processing) framework, i.e. Dui Cheng the multicore architecture that has shared drive subsystem and bus more.The appearance of multinuclear also make parallel computation on a computing machine being embodied as for may.
In existing Computer System Design, two kinds of architectures are arranged: von Neumann system, Harvard's system.But because at that time state-of-art is limit, these two kinds of architectures all fail to consider the application of polycaryon processor, multiprocessor etc., make the polycaryon processor under the prior art and the fusion of multiprocessor and this class architecture encounter difficulties.And single core processor, polycaryon processor exist following weak point separately: single core processor is followed Moore's Law, and along with the propelling of time, speed has produced bottleneck; Polycaryon processor than single core processor precision, because the manufacturing cost of chip improves along with the raising of manufacturing process, makes the development experience bottleneck of polycaryon processor on manufacturing process.When manufacturing process precision during to 18 nanometers, just reached the technology operating limit, manufacturing cost also improves thereupon.
Computing machine under the above prior art is difficult to realize simultaneously efficiently and the purpose of low energy, and complex process, is subjected to the influence of technology bottleneck easily.
Summary of the invention
The object of the present invention is to provide and a kind ofly can realize the high and system of the employing multiple processor structure of low energy simultaneously of processing speed, system of the present invention can realize Distributed Calculation on a main frame, and low, the transmission signals quality height of consuming energy, the traffic are big.
In order to address the above problem, the system of multiple processor structure on a kind of low energy consumption plate of the present invention, described system comprise processor part, memory portion.Wherein, processor part and memory portion are integrated on the plate; Communicate by fiber buss between processor and processor, processor part and the memory portion.
Described processor partly comprises a primary processor and a plurality of divisional processing device; Described each processor distributes according to the topological structure of the regular polygon of Euclidean space principle onboard; There is optical router R at described polyhedron center; Described each divisional processing device clock synchronization; Described processor carries out two-way communication with storer and external unit respectively by fiber buss; The mutually different specific single operation of the separate execution of described each divisional processing device; Described all divisional processing devices are unified the Control Allocation task by primary processor.
A divisional processing device in the system of the present invention can be managed one or more external units of a class simultaneously, each processor links to each other with one or zero storer, and a processor and the storer that is attached thereto are formed a node, are the annexation of one-to-many between node and the external unit.
The invention has the advantages that, adopt the system of a plurality of processor architectures, processor adopting regular polygon layout can realize that each processor clock is synchronous.Each processor clarification in certain roles is independent of each other, and independently finishes specific single processing operation separately, carries out being connected of one-to-many with external unit, can realize Distributed Calculation, and realizes rationally calling and distributing of processor to the full extent, cuts down the consumption of energy.Adopt fiber buss to communicate in the system of the present invention, make the total system good communication quality, energy consumption is low, and weight is little, and antijamming capability is strong.
Description of drawings
Fig. 1 is each part block architecture diagram synoptic diagram of the present invention;
Fig. 2 is processor and an external unit annexation synoptic diagram in the system of the present invention;
Fig. 3 is a processor topology synoptic diagram of the present invention.
Embodiment
As shown in Figure 1, the system of multiple processor structure on the low energy consumption plate of the present invention comprises processor part, memory portion.The processor part represents that with P memory portion shows that with ram table external unit is represented with D.Wherein, processor part and memory portion are integrated on the plate; Communicate by fiber buss between processor and processor, processor part and the memory portion.
Described processor partly comprises a primary processor and a plurality of divisional processing device, as shown in Figure 1, each processor P (i) i=1,2 ... N} is in internal system of the present invention, and each processor distributes according to the topological structure of the regular polygon of Euclidean space principle onboard; As shown in Figure 3, the polyhedron center of processor distribution is equipped with optical router R, each divisional processing device clock synchronization.Described processor carries out two-way communication with storer and external unit respectively by fiber buss; The mutually different specific single operation of the separate execution of described each divisional processing device; Described all divisional processing devices are unified the Control Allocation task by primary processor.
As shown in Figure 2, a divisional processing device in the system of the present invention can be managed a plurality of external units simultaneously, each processor links to each other with one or zero storer, and processor and the storer that is attached thereto form a node, is the annexation of one-to-many between node and the external unit.
The distribution of the multiprocessor among the present invention can realize Distributed Calculation with setting on a computing machine.Generally speaking, Distributed Calculation be based on many computer implemented, by task division being become a plurality of modules, and allow many computer realization corresponding calculated and gathering, this is a kind of based on the constructed system of existing network technology.Yet after multiprocessor application class of the present invention, can on the processor that on the computing machine task is assigned to special use according to treatment characteristic, handle, and then concentrate, make special-purpose processor just move when needed, and distribute and gather task and control all the other processors by primary processor, so just on a main frame, realize Distributed Calculation.
Multiprocessor characteristic of the present invention can provide the sensor management of effective low energy consumption for wireless sensor network.At present, sensor network is among the rapid growth momentum, especially is " Internet of Things " development of extending with the wireless sensor network.Wireless sensor network can obtain objective physical message, has very wide application prospect, can be applied to fields such as military and national defense, industrial or agricultural control, city management, biologic medical, environment measuring, rescue and relief work, hazardous location Long-distance Control, cause the great attention of many national academias and industry member, be considered to one of technology of power that 21 century had an immense impact on.Multiprocessor of the present invention has the function of polycaryon processor, and does not have the development bottleneck of polycaryon processor, more can satisfy the demands.
The present invention adopts the fiber arrangement bus structure, can make that system of the present invention is faster than the system speed of other frameworks, transmission quantity is bigger.Optical fiber communication has brought a revolution for the whole communications field since coming out, and it makes two-forty, jumbo communication become possibility.Loss is low owing to having in optical fiber communication, transmission frequency bandwidth, capacity is big, volume is little, electromagnetic interference (EMI) in light weight, anti-, be difficult for the favor that advantages such as cross-talk enjoy the insider, develops very fast.For now, enterprise such as Intel, Hewlett-Packard is is researching and developing and is making the mutual product that changes of photoelectricity cheaply.The technology that this series products relied on is that realization of the present utility model is laid a good foundation.
The present invention adopts the system of multiple processor structure on the plate, in conjunction with distributed computing technology, optical communication technique and network technology function in one, realize the clock synchronization of multiprocessor based on the Euclidean space principle design, by the functionalization of processor divide and mode of operation the purpose that reaches efficient processing and low energy is set.
Traditional polycaryon processor (CMP) is chip multi-core processor, promptly at integrated two even a more a plurality of processor cores above the single-chip, not with they concrete classification application, cause the usefulness of processor not to be not fully exerted, no matter use the sort processor framework on PC or embedded device, energy consumption all is the problem that can not be ignored.If by application class, then do not have the task handling device can be in the lowest power consumption or the state of zero-power processor, so just can fundamentally solve the power consumption problems of too of processor.
Simultaneously, as material, thermal value height, transmitted error rate height all are unavoidable problem to its bus of traditional computer system with copper; Yet, adopt optical fiber as transmission medium, because the good characteristic that Optical Fiber Transmission itself is had makes the high problem of thermal value and transmitted error rate be readily solved.
And native system is provided with special CPU network interface is managed, for " Internet of Things " and the many interface networks of next generation computer provide technical guarantee.
With Fig. 1-3 is that embodiment illustrates system architecture of the present invention.
One, architecture
The framework of native system comprises a plurality of processors and a plurality of storer, and uses optical fiber as the bus material.
(1) a plurality of processors distribute according to the topological structure of regular polygon onboard.
(2) primary processors are responsible for the mode of operation of all processors is controlled.
(3) each processor has zero or a storer to connect.
(4) optical fiber makes and can carry out communicating by letter of control information and data between a plurality of processors as transmission medium.
(5) input-output apparatus are connected with one or more processor, and an input-output apparatus is controlled by one or more processors.
Two, the relation of each node
Framework of the present invention is described with S set.S={N, R, D}, wherein N is used for representing processor, and R is used for representing RAM (Radom Acce s s Memory), and D is used for describing external device.External device not only is meant in esse physical equipment, wherein also comprises the notional virtual equipment of software.
As shown in Figure 1, in order to describe accurately, we are numbered 1 with N processor, 2,3...N, the RAM that each processor connected are numbered R (i), { i=1,2...n}, the device numbering of being responsible for is D (j), and { j=1,2...} are referred to as 1 node together with 1 processor and connected RAM.
Synchronous for guaranteeing processor clock, the Synchronization Design mode based on Euclidean space is adopted in the distribution of all processors.Under Euclidean space, only there are 5 kinds of regular polygons, are respectively positive tetrahedron, regular hexahedron, regular octahedron, regular dodecahedron and regular dodecahedron.For making that the clock of each processor can be synchronous, adopt the topological structure of regular polygon.Wherein, each summit all is a node.
In this kind design, wherein regular dodecahedron has 20 summits, under the optimal way, selects the regular dodecahedron structure for use, and this kind structure is enough to satisfy the connection requirement of required external device.
Three, the relation of each node and external device
In the framework of the present invention, the pass of each node and external device be 1 couple of n (n=1,2,3 ...) relation.Use the reason of such scheme be to allow the management independent of external device as far as possible, make 1 or limited equipment of 1 processor management, and 1 the non-traditional equipment that processor management is all.
As shown in Figure 2, node 1 be responsible for D (1) equipment unlatching, move, close and other work of relevant this equipment, and node 2 be responsible for equipment D (2), D (3) unlatching, move, close and other work of relevant this equipment, the rest may be inferred for other nodes.For example, the all-network interface of 1 pair of system of node manages and operates, and 2 pairs of various input-output device of node manage and operate or the like.Wherein, the responsible equipment of each node should quantitatively should lack as far as possible.
Four, optical fiber connects
The present invention makes the carrier of using up as its signal transmission, and many advantages are arranged.
(1) optical signal transmission speed is fast.Light transmission speed in optical fiber approaches light velocity of propagation in a vacuum substantially, and light signal can not cause the generation of heating phenomenon.
(2) transmittability is strong.Use light can increase transmission bandwidth, make that more multidata can the while parallel transmission.
(3) signal attenuation is little.Use the Optical Fiber Transmission data little more a lot of than signal attenuation in traditional electric wire transmission.
Therefore, using optical fiber is a kind of more satisfactory selection as transmission medium.
Optical fiber layout onboard adopts the optical substrate technology.
The optical substrate technology is exactly to add an optical communication layer in traditional printed circuit board (PCB), with the copper cash among the traditional PCB (Printed circuit board) of optical waveguide replacement.
Because free space optical interconnection does not rely on transmission medium, therefore can directly utilize free space and lens/catoptron that two chips are coupled together with light beam.Wherein, the band micro-ring resonator that adopts time delay to try one's best low is realized the steering operation of data.
The realization of low energy consumption of the present invention depends on the sleeping/waking control of multiprocessor.There is not the processor of use will be in dormant state in the task executions.In case when needing to use certain processor, wake this processor up to carry out some specific operation.Wherein, primary processor of needs distributes and manages, and makes a series of processor rational allocation to use.
The utility model also depends on the realization that photoelectricity changes technology and light interconnection technique mutually.For the communication between multiprocessor on the plate, if adopt the conventional bus mode to face huge challenge at aspects such as performance, power consumption, time-delay and reliabilities: communication bandwidth is limited, the global synchronization difficulty, and reusability is poor, the structural extended difficulty.Optical fiber means before data in the bus enter processor and must make multiprocessor to communicate by optical fiber through the conversion of light signal and electric signal as bus.Therefore, the mutual technology of changeing of photoelectricity is used herein.
Native system is used for reference computer network adopting on the basis of light as carrier, proposes new internuclear communication construction---plate glazing network interconnection technology (Photonic Network-on-Board).The copper cash that the optical-fiber network interconnection technique is different from traditional approach connects, and it provides good parallel communications ability, thereby makes communication bandwidth increase several magnitude, and its network topology structure makes extendability stronger.In addition, the optical-fiber network interconnection technique has advantages such as height is handled up, low energy consumption.
The present invention is connected on the same plate by the processor of a plurality of difference in functionalitys, uses the processor processes data of specific function as required.Based on distributed computing technology, on individual plates, realize the Distributed Calculation of a plurality of processors.This is the characteristics that are different from the traditional distributed computing system.
The above; only be the preferable embodiment of the present invention; but protection scope of the present invention is not limited thereto; anyly be familiar with those skilled in the art in the technical scope that the present invention discloses; be equal to replacement or change according to technical scheme of the present invention and inventive concept thereof, all should be encompassed within protection scope of the present invention.
Claims (2)
1. the system of multiple processor structure on the plate of a low energy consumption is characterized in that, described system comprises processor part, memory portion, and described processor part and memory portion are integrated on the plate; Communicate by fiber buss between described processor part and the memory portion;
Described processor partly comprises a primary processor and a plurality of divisional processing device; Described each processor distributes according to the topological structure of the regular polygon of Euclidean space principle onboard; There is optical router R at described polyhedron center; Described each divisional processing device clock synchronization; Described each processor carries out two-way communication with storer and external unit respectively by fiber buss; The mutually different specific single operation of the separate execution of described each divisional processing device; Described all divisional processing devices are unified the Control Allocation task by primary processor.
2. the system of multiple processor structure on the plate of low energy consumption according to claim 1 is characterized in that, a described divisional processing device can be managed one or more external units of a class simultaneously; Described processor links to each other with one or zero storer; A described processor and the storer that is attached thereto are formed a node; It between described node and the external unit annexation of one-to-many.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2023000220A1 (en) * | 2021-07-21 | 2023-01-26 | 深圳市大疆创新科技有限公司 | Distributed architecture of movable platform and movable platform |
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| WO2023000220A1 (en) * | 2021-07-21 | 2023-01-26 | 深圳市大疆创新科技有限公司 | Distributed architecture of movable platform and movable platform |
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Granted publication date: 20110126 Termination date: 20130805 |