CN201708784U - Electric level transfer circuit with function of anti-jamming protection - Google Patents
Electric level transfer circuit with function of anti-jamming protection Download PDFInfo
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- CN201708784U CN201708784U CN201020247538XU CN201020247538U CN201708784U CN 201708784 U CN201708784 U CN 201708784U CN 201020247538X U CN201020247538X U CN 201020247538XU CN 201020247538 U CN201020247538 U CN 201020247538U CN 201708784 U CN201708784 U CN 201708784U
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Abstract
The utility model discloses an electric level transfer circuit with the function of anti-jamming protection, which is formed by a pulse generating circuit, a first MOS (Metal Oxide Semiconductor) tube, a second MOS tube, a first comparator, a second comparator, a logic circuit and an RS (remote sensing) trigger. The first reference voltage switched in the first comparator is lower than the second reference voltage switched in the second comparator, so that by adjusting the width to length ratio of the first MOS tube and the second MOS tube, the voltage at the communal connecting end of drain electrodes of the first and the second MOS tubes is larger than the value of the first reference voltage and is less than the value of the second reference voltage when the first MOS tube is connected, and the voltage at the communal connecting end is lower than the first reference voltage when the second MOS tube is connected. Therefore, when the electric level transfer circuit is in normal work, an electric level signal consistent with an input signal is outputted, and when interfering signals cause the electric level transfer circuit to work, a fixed electric level is outputted to cut off the follow-up circuits driven by the electric level transfer circuit, so as to achieve the function of protecting the follow-up circuits.
Description
Technical field
The utility model relates to a kind of level transfer techniques, especially relates to a kind of level shifter with anti-interference protection function.
Background technology
In many integrated circuits, for satisfying the requirement of withstand voltage of different semiconductor device in the integrated circuit, need to convert lower level signal to higher level signal, perhaps convert higher level signal to lower level signal, level shifts (Level shift) technology and promptly is used to realize this function.
Traditional level shifter normally directly converts input signal to an output signal consistent with the input signal phase place.If the input signal that integrated circuit needs is when being sent to the input of level shifter, integrated circuit keeps normal operating conditions.But if produce an interference signal at the input of level shifter, then the output signal of the output of level shifter output then has uncertainty, may export a high level, also may export a low level.The uncertainty of this traditional level shifter output signal might cause expendable damage to the semiconductor device in the integrated circuit, typical example is as driving half-bridge drive circuit with level shifter, if the output signal of the output of level shifter output is used for driving on high-tension side N type MOSFEF pipe, so in the time of the conducting of the N type MOSFET of low-pressure side pipe, input at level shifter can produce an interference signal, this interference signal triggering level carry circuit work, then level shifter may be exported a high level and allow the conducting of on high-tension side N type MOSFET pipe, at this moment the situation of the N type MOSFET pipe conducting simultaneously of on high-tension side N type MOSFET pipe and low-pressure side will occur, the N type MOSFET pipe of on high-tension side N type MOSFET pipe and low-pressure side will be damaged simultaneously.
Summary of the invention
Technical problem to be solved in the utility model provides a kind of level shifter with stronger anti-interference protection function; this level shifter can keep output output fixed level to protect with the subsequent conditioning circuit work of closing driving when interference signal occurring.
The utility model solves the problems of the technologies described above the technical scheme that is adopted: a kind of level shifter with anti-interference protection function; comprise pulse-generating circuit; first metal-oxide-semiconductor; second metal-oxide-semiconductor; pull-up resistor; first comparator; second comparator; logical circuit and rest-set flip-flop; the input of described pulse-generating circuit inserts input signal; the pulse signal that first output output of described pulse-generating circuit produces when the rising edge of input signal; the pulse signal that second output output of described pulse-generating circuit produces when the trailing edge of input signal; first output of described pulse-generating circuit is connected with the grid of described first metal-oxide-semiconductor; second output of described pulse-generating circuit is connected with the grid of described second metal-oxide-semiconductor; the equal ground connection of the source electrode of the source electrode of described first metal-oxide-semiconductor and substrate and described second metal-oxide-semiconductor and substrate; the drain electrode of described first metal-oxide-semiconductor is connected with the drain electrode of described second metal-oxide-semiconductor; its public connecting end respectively with first end of described pull-up resistor; the first input end of described first comparator is connected with the first input end of described second comparator; the second termination high voltage source of described pull-up resistor; second input of described first comparator inserts first reference voltage; second input of described second comparator inserts second reference voltage; described first reference voltage is less than described second reference voltage; the voltage at the public connecting end place of the drain electrode of the drain electrode of described first metal-oxide-semiconductor and described second metal-oxide-semiconductor is greater than described first reference voltage and less than described second reference voltage during described first metal-oxide-semiconductor conducting; the voltage at the public connecting end place of the drain electrode of the drain electrode of described first metal-oxide-semiconductor and described second metal-oxide-semiconductor is less than described first reference voltage during described second metal-oxide-semiconductor conducting; described logical circuit has first input end; second input; first output and second output; the first input end of described logical circuit is connected with the output of described first comparator; second input of described logical circuit is connected with the output of described second comparator; the voltage at the public connecting end place of the drain electrode of the drain electrode of described first metal-oxide-semiconductor and described second metal-oxide-semiconductor is during greater than described first reference voltage and less than described second reference voltage; the output signal of described second comparator is overturn; second output of described logical circuit is connected with the set input of described rest-set flip-flop; the signal of second output output of described logical circuit is input to the set input of described rest-set flip-flop as the asserts signal of described rest-set flip-flop; the output output high level of described rest-set flip-flop; the voltage at the public connecting end place of the drain electrode of the drain electrode of described first metal-oxide-semiconductor and described second metal-oxide-semiconductor is during less than described first reference voltage; the output signal of the output signal of described second comparator and described first comparator is successively overturn; described logical circuit shields the output signal of described second comparator; first output of described logical circuit is connected with the RESET input of described rest-set flip-flop; the signal of first output of described logical circuit output is input to the RESET input of described rest-set flip-flop, the output output low level of described rest-set flip-flop as the reset signal of described rest-set flip-flop.
Described first metal-oxide-semiconductor and described second metal-oxide-semiconductor are the N-channel MOS pipe, and the breadth length ratio of the breadth length ratio of described first metal-oxide-semiconductor and described second metal-oxide-semiconductor is unequal.
Described first metal-oxide-semiconductor and described second metal-oxide-semiconductor are N-channel MOS FET pipe, and the breadth length ratio of the breadth length ratio of described first metal-oxide-semiconductor and described second metal-oxide-semiconductor is unequal.
Described input signal is a square-wave signal.
Described logical circuit is mainly by first inverter, second inverter, the 3rd inverter, the 4th inverter, the 5th inverter, hex inverter, the 7th inverter, first with the door, second with door and electric capacity composition, the input of described first inverter is as the first input end of described logical circuit, it is connected by the output of first binding post with described first comparator, the output of described first inverter is connected with the first input end of door with described first with described the 4th inverter 34 inputs respectively, the output of described the 4th inverter is as first output of described logical circuit, it is connected with the RESET input of described rest-set flip-flop by the 3rd binding post, the input of described second inverter is as second input of described logical circuit, it is connected by the output of second binding post with described second comparator, the output of described second inverter is connected with second input of door with described first, described first with the door output be connected with the input of described the 3rd inverter, the output of described the 3rd inverter is connected with the first input end of door and the input of described the 5th inverter with described second respectively, the output of described the 5th inverter is connected with the input of described the 7th inverter and first end of described electric capacity respectively, the second end ground connection of described electric capacity, the output of described the 7th inverter is connected with second input of door with described second, described second with the door output be connected with the input of described hex inverter, the output of described hex inverter is as second output of described logical circuit, and it is connected with the set input of described rest-set flip-flop by the 4th binding post.
Compared with prior art; advantage of the present utility model is by pulse-generating circuit; first metal-oxide-semiconductor; second metal-oxide-semiconductor; first comparator; second comparator; logical circuit and rest-set flip-flop constitute level shifter; because first reference voltage of second input of access first comparator is less than second reference voltage of second input that inserts second comparator; the breadth length ratio by regulating first metal-oxide-semiconductor and the breadth length ratio of second metal-oxide-semiconductor; the voltage at the public connecting end place of the drain electrode of the drain electrode of first metal-oxide-semiconductor and second metal-oxide-semiconductor is greater than the value of first reference voltage and less than the value of second reference voltage when making the first metal-oxide-semiconductor conducting; the voltage at the public connecting end place of the drain electrode of the drain electrode of first metal-oxide-semiconductor and second metal-oxide-semiconductor is less than the value of first reference voltage when making the second metal-oxide-semiconductor conducting; like this when this level shifter operate as normal; it exports a level signal consistent with input signal; and when causing this level shifter work because of interference signal; fixed level of this level shifter output; this fixed level will turn-off the subsequent conditioning circuit that this level shifter drives, thereby reach the function of protection subsequent conditioning circuit.
Description of drawings
Fig. 1 is the circuit theory diagrams of level shifter of the present utility model;
Fig. 2 a is the waveform schematic diagram of the input signal that inserts of the input of pulse-generating circuit;
Fig. 2 b is first output of pulse-generating circuit is exported the pulse signal that produces when the rising edge of input signal a waveform schematic diagram;
Fig. 2 c is second output of pulse-generating circuit is exported the pulse signal that produces when the trailing edge of input signal a waveform schematic diagram;
Fig. 2 d is the waveform schematic diagram of asserts signal of second output output of logical circuit;
Fig. 2 e is the waveform schematic diagram of reset signal of first output output of logical circuit;
Fig. 2 f is the waveform schematic diagram of output signal of the output output of rest-set flip-flop;
Fig. 3 is a logical circuitry.
Embodiment
Embodiment describes in further detail the utility model below in conjunction with accompanying drawing.
A kind of level shifter that the utility model proposes with anti-interference protection function; as shown in Figure 1; it comprises pulse-generating circuit 19; first metal-oxide-semiconductor 20; second metal-oxide-semiconductor 21; pull-up resistor 22; first comparator 23; second comparator 24; logical circuit 25 and rest-set flip-flop 26; the power end of the power end of logical circuit 25 and rest-set flip-flop 26 all meets high voltage source HV; the input of pulse-generating circuit 19 inserts input signal IN; input signal IN is the lower square-wave signal of high level current potential shown in Fig. 2 a; pulse-generating circuit 19 becomes the rising edge of input signal IN into a pulse signal; the pulse signal SET shown in Fig. 2 b that its first output output produces when the rising edge of input signal IN; pulse-generating circuit 19 becomes the trailing edge of input signal IN into a pulse signal; the pulse signal RESET shown in Fig. 2 c that its second output output produces when the trailing edge of input signal; first output of pulse-generating circuit 19 is connected with the grid of first metal-oxide-semiconductor 20; second output of pulse-generating circuit 19 is connected with the grid of second metal-oxide-semiconductor 21; the equal ground connection of the source electrode of the source electrode of first metal-oxide-semiconductor 20 and substrate and second metal-oxide-semiconductor 21 and substrate; the drain electrode of first metal-oxide-semiconductor 20 is connected with the drain electrode of second metal-oxide-semiconductor 21; its public connecting end respectively with first end of pull-up resistor 22; the first input end of first comparator 23 is connected with the first input end of second comparator 24; the second termination high voltage source HV of pull-up resistor 22; second input of first comparator 23 inserts the first reference voltage V ref1; second input of second comparator 24 inserts the second reference voltage V ref2; logical circuit 25 has first input end; second input; first output and second output; the first input end of logical circuit 25 is connected with the output of first comparator 23; second input of logical circuit 25 is connected with the output of second comparator 24; the signal of first output output of logical circuit 25 is shown in Fig. 2 e; this signal is input to the RESET input R of rest-set flip-flop 26 as the reset signal of rest-set flip-flop 26; the signal of second output output of logical circuit 25 is shown in Fig. 2 d; this signal is input to the set input S of rest-set flip-flop 26 as the asserts signal of rest-set flip-flop 26; when coming interim rest-set flip-flop 26, the pulse signal SET shown in Fig. 2 b is set; the output output high level of rest-set flip-flop 26; when coming interim rest-set flip-flop 26, the pulse signal RESET shown in Fig. 2 c is reset; the output output low level of rest-set flip-flop 26; the duty ratio of the output signal Vout of the output output of rest-set flip-flop 26 and duty ratio and the cycle of cycle and input signal Vin are consistent; this output signal Vout is shown in Fig. 2 f; it is a square-wave signal that the high level current potential is higher; realized the basic function of level shifter, be about to lower level signal and converted a higher level signal to.
In this specific embodiment, first metal-oxide-semiconductor 20 and second metal-oxide-semiconductor 21 can all adopt the N-channel MOS pipe, also can all adopt N-channel MOS FET pipe; The breadth length ratio of the breadth length ratio of first metal-oxide-semiconductor 20 and second metal-oxide-semiconductor 21 is unequal.
At this, the value of the first reference voltage V ref1 is less than the value of the second reference voltage V ref2, regulate the breadth length ratio of first metal-oxide-semiconductor 20 and the resistance value of pull-up resistor 22, the pulse signal SET that exports when first output of pulse-generating circuit 19 is a high level, and when the pulse signal RESET of second output of pulse-generating circuit 19 output was low level, the voltage VDS at the public connecting end place of the drain electrode of the drain electrode of first metal-oxide-semiconductor 20 and second metal-oxide-semiconductor 21 was greater than the value of the first reference voltage V ref1 and less than the value of the second reference voltage V ref2 when making 20 conductings of first metal-oxide-semiconductor; Regulate the breadth length ratio of second metal-oxide-semiconductor 21 again, the pulse signal SET that exports when first output of pulse-generating circuit 19 is a low level, and when the pulse signal RESET of second output of pulse-generating circuit 19 output was high level, the voltage VDS at the public connecting end place of the drain electrode of the drain electrode of first metal-oxide-semiconductor 20 and second metal-oxide-semiconductor 21 was less than the first reference voltage V ref1 when making 21 conductings of second metal-oxide-semiconductor.Like this, the pulse signal SET that exports when first output of pulse-generating circuit 19 comes interim, because the voltage VDS at the public connecting end place of the drain electrode of first metal-oxide-semiconductor 20 and the drain electrode of second metal-oxide-semiconductor 21 is greater than the value of the first reference voltage V ref1 and less than the second reference voltage V ref2, therefore have only second comparator 24 to overturn, after the output signal of second comparator 24 is handled by logical circuit 25, signal of second output output of logical circuit 25 is input to the set input S of rest-set flip-flop 26 as the asserts signal of rest-set flip-flop 26, rest-set flip-flop is set, its output output high level.The pulse signal RESET that exports when second output of pulse-generating circuit 19 comes interim, because the voltage VDS at the public connecting end place of the drain electrode of first metal-oxide-semiconductor 20 and the drain electrode of second metal-oxide-semiconductor 21 is less than the first reference voltage V ref1, therefore first comparator 23 and second comparator 24 all will overturn, but logical circuit 25 will mask the output signal of second comparator 24 this moment, and be input to the RESET input R of rest-set flip-flop 26 as the reset signal of rest-set flip-flop 26 at signal of first output of logical circuit 25 output, rest-set flip-flop is reset, its output output low level.Because the rising edge of the output signal Vout of rest-set flip-flop is obtained by the pulse signal SET of the rising edge generation of input signal IN, the trailing edge of output signal Vout is obtained by the pulse signal RESET of the trailing edge generation of input signal IN, duty ratio and the cycle of the duty ratio of output signal Vout and cycle and input signal IN are consistent, thereby have realized the basic function of level shifter.
When interference signal occurring; because interference signal is generally a very narrow pulse signal; to produce a pulse interference signal simultaneously on the pulse signal RESET of the pulse signal SET of first output output of pulse-generating circuit 19 and second output output of pulse-generating circuit 19; the voltage VDS at the public connecting end place of the drain electrode of the drain electrode of first metal-oxide-semiconductor 20 and second metal-oxide-semiconductor 21 will drop to less than the first reference voltage V ref1; as mentioned above; as the voltage VDS at the public connecting end place of the drain electrode of the drain electrode of first metal-oxide-semiconductor 20 and second metal-oxide-semiconductor 21 during less than the first reference voltage V ref1; second comparator 24 and first comparator 23 successively overturn; the signal of the output output of second comparator 24 will be masked by logical circuit 25; after having only the signal of the output output of first comparator 23 to handle by logical circuit 25; the signal of first output output of logical circuit 25 is sent to the RESET input R of rest-set flip-flop 26 as the reset signal of rest-set flip-flop 26; rest-set flip-flop 26 is reset or hold reset; rest-set flip-flop 26 output signal Vout will become low level or keep low level; the subsequent conditioning circuit that this moment, this level shifter drove is turned off, thereby has realized anti-interference protection function.
When driving half-bridge drive circuit with level shifter of the present utility model; when interference signal occurring; level shifter of the present utility model is output low level always; turn-off on high-tension side N type MOSFET pipe; avoid the N type MOSFET pipe conducting simultaneously of on high-tension side N type MOSFET pipe and low-pressure side like this, effectively protected the N type MOSFET pipe of on high-tension side N type MOSFET pipe and low-pressure side not to be damaged.
In this specific embodiment, pulse-generating circuit 19 adopts prior art, and first comparator 23 and second comparator 24 all adopt common voltage amplitude comparator, and rest-set flip-flop 26 adopts existing basic rest-set flip-flop.
In this specific embodiment, logical circuit 25 can adopt circuit structure as shown in Figure 3, it comprises first inverter 30, second inverter 31, the 3rd inverter 33, the 4th inverter 34, the 5th inverter 37, hex inverter 36, the 7th inverter 38, first with the door 32, second with door 35 and electric capacity 39, the input of first inverter 30 is as the first input end of logical circuit 25, it is connected with the output of first comparator 23 by the first binding post IN1, the output of first inverter 30 is connected with the first input end of door 32 with first with the input of the 4th inverter 34 respectively, the output of the 4th inverter 34 is as first output of logical circuit 25, it is connected with the RESET input R of rest-set flip-flop 26 by the 3rd binding post R1, the input of second inverter 31 is as second input of logical circuit 25, it is connected with the output of second comparator 24 by the second binding post IN2, the output of second inverter 31 is connected with second input of door 32 with first, first is connected with the input of the 3rd inverter 33 with door 32 output, the output of the 3rd inverter 33 is connected with the first input end of door 35 and the input of the 5th inverter 37 with second respectively, the output of the 5th inverter 37 is connected with the input of the 7th inverter 38 and first end of electric capacity 39 respectively, the output of the 7th inverter 38 is connected with second input of door 35 with second, second is connected with the input of hex inverter 36 with door 35 output, the output of hex inverter 36 is as second output of logical circuit 25, it is connected with the set input S of rest-set flip-flop 26 by the 4th binding post S1, the second end ground connection of electric capacity 39.When the pulse signal SET shown in Fig. 2 b comes interim, have only second comparator 24 to overturn, this moment, 23 outputs of first comparator kept low level, then first inverter 30 is exported high level, first is effective with door 32, the signal of the output of second comparator 24 output can by first with door 32, again through the 3rd inverter 33 of back, hex inverter 36, the 5th inverter 37, the 7th inverter 38 and second and door 35 and electric capacity 39 handle pulse signal of back output, this pulse signal is input to the set input S of rest-set flip-flop 26 as the asserts signal of rest-set flip-flop 26, and rest-set flip-flop is set.When the pulse signal RESET shown in Fig. 2 c comes interim, first comparator 23 and second comparator 24 all will overturn, and the signal of the output output of first comparator 23 can directly be input to the RESET input R of rest-set flip-flop 26 by first inverter 30 and the 4th inverter 34.The signal of the output of first comparator 23 output through first inverter 30 be input to first with the first input end of door 32, the signal of the output of second comparator 24 output through second inverter 31 be input to first with second input of door 32, but because the value of the first reference voltage V ref1 is less than the value of the second reference voltage V ref2, the time that upset takes place first comparator 23 slightly lags behind the time that upset takes place second comparator, therefore, first with door 32 first input end signal time difference of existence with second input, be specifically first with door 32 first input end signal rising edge slightly lag behind first with the rising edge of second input end signal of door 32, first with door 32 first input end signal trailing edge slightly be ahead of first with the trailing edge of second input end signal of door 32, such first will export two undersuings that pulse duration is extremely narrow with door 32 output, these two extremely narrow undersuings are promptly through becoming two positive pulse signals that pulse duration is extremely narrow behind the 3rd inverter 33, the extremely narrow positive pulse signal of these two pulse durations will be by the 5th inverter 37, the 7th inverter 38, electric capacity 39 and second and the screened circuits formed of door 35 masked, export a high level second with the output of door 35 at last, low level of output output of hex inverter 36, this low level is input to the set input S of rest-set flip-flop 26, and rest-set flip-flop 26 can not be set.Therefore 26 of rest-set flip-flops are reset output low level when first comparator 23 and second comparator 24 all take place to overturn.
In this embodiment, it is effective that the set of rest-set flip-flop 26 and reset signal are considered to low level, if rest-set flip-flop 26 is that high level is effective, then only needs to be connected a circuit structure respectively and get final product with inverter functionality in the 4th inverter 34 and hex inverter 36 back.
Claims (5)
1. level shifter with anti-interference protection function; it is characterized in that comprising pulse-generating circuit; first metal-oxide-semiconductor; second metal-oxide-semiconductor; pull-up resistor; first comparator; second comparator; logical circuit and rest-set flip-flop; the input of described pulse-generating circuit inserts input signal; the pulse signal that first output output of described pulse-generating circuit produces when the rising edge of input signal; the pulse signal that second output output of described pulse-generating circuit produces when the trailing edge of input signal; first output of described pulse-generating circuit is connected with the grid of described first metal-oxide-semiconductor; second output of described pulse-generating circuit is connected with the grid of described second metal-oxide-semiconductor; the equal ground connection of the source electrode of the source electrode of described first metal-oxide-semiconductor and substrate and described second metal-oxide-semiconductor and substrate; the drain electrode of described first metal-oxide-semiconductor is connected with the drain electrode of described second metal-oxide-semiconductor; its public connecting end respectively with first end of described pull-up resistor; the first input end of described first comparator is connected with the first input end of described second comparator; the second termination high voltage source of described pull-up resistor; second input of described first comparator inserts first reference voltage; second input of described second comparator inserts second reference voltage; described first reference voltage is less than described second reference voltage; the voltage at the public connecting end place of the drain electrode of the drain electrode of described first metal-oxide-semiconductor and described second metal-oxide-semiconductor is greater than described first reference voltage and less than described second reference voltage during described first metal-oxide-semiconductor conducting; the voltage at the public connecting end place of the drain electrode of the drain electrode of described first metal-oxide-semiconductor and described second metal-oxide-semiconductor is less than described first reference voltage during described second metal-oxide-semiconductor conducting; described logical circuit has first input end; second input; first output and second output; the first input end of described logical circuit is connected with the output of described first comparator; second input of described logical circuit is connected with the output of described second comparator; the voltage at the public connecting end place of the drain electrode of the drain electrode of described first metal-oxide-semiconductor and described second metal-oxide-semiconductor is during greater than described first reference voltage and less than described second reference voltage; the output signal of described second comparator is overturn; second output of described logical circuit is connected with the set input of described rest-set flip-flop; the signal of second output output of described logical circuit is input to the set input of described rest-set flip-flop as the asserts signal of described rest-set flip-flop; the output output high level of described rest-set flip-flop; the voltage at the public connecting end place of the drain electrode of the drain electrode of described first metal-oxide-semiconductor and described second metal-oxide-semiconductor is during less than described first reference voltage; the output signal of the output signal of described second comparator and described first comparator is successively overturn; described logical circuit shields the output signal of described second comparator; first output of described logical circuit is connected with the RESET input of described rest-set flip-flop; the signal of first output of described logical circuit output is input to the RESET input of described rest-set flip-flop, the output output low level of described rest-set flip-flop as the reset signal of described rest-set flip-flop.
2. a kind of level shifter according to claim 1 with anti-interference protection function; it is characterized in that described first metal-oxide-semiconductor and described second metal-oxide-semiconductor are the N-channel MOS pipe, the breadth length ratio of the breadth length ratio of described first metal-oxide-semiconductor and described second metal-oxide-semiconductor is unequal.
3. a kind of level shifter according to claim 1 with anti-interference protection function; it is characterized in that described first metal-oxide-semiconductor and described second metal-oxide-semiconductor are N-channel MOS FET pipe, the breadth length ratio of the breadth length ratio of described first metal-oxide-semiconductor and described second metal-oxide-semiconductor is unequal.
4. according to each described a kind of level shifter in the claim 1 to 3, it is characterized in that described input signal is a square-wave signal with anti-interference protection function.
5. a kind of level shifter according to claim 4 with anti-interference protection function; it is characterized in that described logical circuit is mainly by first inverter; second inverter; the 3rd inverter; the 4th inverter; the 5th inverter; hex inverter; the 7th inverter; first with the door; second with door and electric capacity composition; the input of described first inverter is as the first input end of described logical circuit; it is connected by the output of first binding post with described first comparator; the output of described first inverter is connected with the first input end of door with described first with described the 4th inverter 34 inputs respectively; the output of described the 4th inverter is as first output of described logical circuit; it is connected with the RESET input of described rest-set flip-flop by the 3rd binding post; the input of described second inverter is as second input of described logical circuit; it is connected by the output of second binding post with described second comparator; the output of described second inverter is connected with second input of door with described first; described first with the door output be connected with the input of described the 3rd inverter; the output of described the 3rd inverter is connected with the first input end of door and the input of described the 5th inverter with described second respectively; the output of described the 5th inverter is connected with the input of described the 7th inverter and first end of described electric capacity respectively; the second end ground connection of described electric capacity; the output of described the 7th inverter is connected with second input of door with described second; described second with the door output be connected with the input of described hex inverter; the output of described hex inverter is as second output of described logical circuit, and it is connected with the set input of described rest-set flip-flop by the 4th binding post.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201020247538XU CN201708784U (en) | 2010-06-29 | 2010-06-29 | Electric level transfer circuit with function of anti-jamming protection |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201020247538XU CN201708784U (en) | 2010-06-29 | 2010-06-29 | Electric level transfer circuit with function of anti-jamming protection |
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| CN201708784U true CN201708784U (en) | 2011-01-12 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103108427A (en) * | 2011-11-14 | 2013-05-15 | 深圳市长运通光电技术有限公司 | Light emitting diode (LED) lamp and high voltage monitoring protection circuit |
-
2010
- 2010-06-29 CN CN201020247538XU patent/CN201708784U/en not_active Expired - Lifetime
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103108427A (en) * | 2011-11-14 | 2013-05-15 | 深圳市长运通光电技术有限公司 | Light emitting diode (LED) lamp and high voltage monitoring protection circuit |
| CN103108427B (en) * | 2011-11-14 | 2015-05-13 | 深圳市长运通光电技术有限公司 | Light emitting diode (LED) drive chip, LED lamp and high voltage monitoring protection circuit |
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Effective date of registration: 20161206 Address after: 315809 Beilun City, Ningbo Province, Wan Chai street, Wan Jing Road, No. G, block, floor three, 12-3, 213 Patentee after: Core integrated circuit (Ningbo) Co., Ltd. Address before: Ningbo city science and Technology Park in Zhejiang province 315040 lease Poplar Road No. 7 Lane 578 Patentee before: Daily Silver IMP Microelectronics Co., Ltd. |
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Granted publication date: 20110112 |