CN201681895U - Lead frame structure without base island - Google Patents
Lead frame structure without base island Download PDFInfo
- Publication number
- CN201681895U CN201681895U CN2010201826228U CN201020182622U CN201681895U CN 201681895 U CN201681895 U CN 201681895U CN 2010201826228 U CN2010201826228 U CN 2010201826228U CN 201020182622 U CN201020182622 U CN 201020182622U CN 201681895 U CN201681895 U CN 201681895U
- Authority
- CN
- China
- Prior art keywords
- pin
- pins
- lead frame
- plastic packaging
- frame structure
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
Abstract
The utility model relates to a lead frame structure without a base island, which comprises pins (2). A first metal layer (4) is arranged on the front face of each pin (2), a second metal layer (5) is arranged on the back face of each pin (2), the front faces of the pins (2) extend to the side of a follow-up area needing to be provided with a chip as much as possible, the area on the peripheries of the pins (2) and the area among the pins (2) are provided with plastic packaging materials (3) without fillers in an embedded manner, the plastic packaging materials (3) without fillers connect the lower portions of the pins together, and the back faces of the pins (2) are smaller than the front faces of the pins (2) in size to form a pin structure with a large upper portion and a smaller lower portion. The lead frame structure without a base island has the advantages of large bound capacity of a plastic packaging body and the pins, cost reduction, energy saving, carbon decrease and waste reduction.
Description
(1) technical field
The utility model relates to a kind of lead frame structure.Belong to the semiconductor packaging field.
(2) background technology
Traditional lead frame structure mainly contains two kinds:
First kind:
After chemical etching and surface electrical coating are carried out in the front of employing metal substrate, stick the resistant to elevated temperatures glued membrane of one deck at the back side of metal substrate and form the leadframe carrier (as shown in Figure 2) that to carry out encapsulation process.
Second kind:
After chemical etching and surface electrical coating are carried out in the front of employing metal substrate, promptly finish the making (as shown in Figure 3) of lead frame.Back etched is then carried out at the back side of lead frame again in encapsulation process.
And the not enough point of two kinds of above-mentioned lead frames below in encapsulation process, having existed:
First kind:
1) but this kind lead frame must stick the glued membrane of one deck costliness high temperature resistance because of the back side.So directly increased high cost.
2) but also because the glued membrane of one deck high temperature resistance must be sticked in the back side of this kind lead frame, so the load technology in encapsulation process can only be used conduction or nonconducting resin technology, and the technology that can not adopt eutectic technology and slicken solder is fully carried out load, so selectable product category just has bigger limitation.
3) but again because the glued membrane of one deck high temperature resistance must be sticked in the back side of this kind lead frame, and in the ball bonding bonding technology in encapsulation process, because but the glued membrane of this high temperature resistance is a soft materials, so caused the instability of ball bonding bonding parameter, seriously influenced the quality of ball bonding and the stability of production reliability.
4) but again because the glued membrane of one deck high temperature resistance must be sticked in the back side of this kind lead frame, and the plastic package process process in encapsulation process, because the high pressure of plastic packaging relation is easy to cause between lead frame and the glued membrane and infiltrates plastic packaging material, be that the kenel of conduction has become insulation pin (as shown in Figure 4) on the contrary because of having infiltrated plastic packaging material and will formerly should belong to metal leg.
Second kind:
This kind lead frame structure has carried out etching partially technology in the metal substrate front, though can solve the problem of first kind of lead frame, but because only carried out the work that etches partially in the metal substrate front, and plastic packaging material only envelopes the height of half pin in the plastic packaging process, so the constraint ability of plastic-sealed body and metal leg has just diminished, when if the plastic-sealed body paster is not fine to pcb board, does over again again and heavily paste, with regard to the problem (as shown in Figure 5) that is easy to generate pin.
Especially the kind of plastic packaging material is to adopt when filler is arranged, because material is at the environment and the follow-up surface-pasted stress changing relation of production process, can cause metal and plastic packaging material to produce the crack of vertical-type, its characteristic is the high more then hard more crisp more crack that is easy to generate more of proportion of filler.
In addition, because the distance between chip and the metal leg is far away, the length of metal wire is longer, shown in Fig. 6～7, and metal wire cost higher (the especially metal wire of Ang Gui proof gold matter); Same because the length of metal wire is longer, make that the signal output speed of chip is slow (being the product of storage class and the calculating that needs mass data by it, more outstanding); Too because the length of metal wire is longer, so existing dead resistance/parasitic capacitance of metal wire and parasitic electric pole are also higher to the interference of signal; Because the distance between chip and the metal leg is far away, make that the volume and the area of encapsulation are bigger again, material cost is higher, and discarded object is more.
(3) summary of the invention
The purpose of this utility model is to overcome above-mentioned deficiency, provides a kind of and reduces that packaging cost, selectable product category are wide, the big no-pad lead frame structure of constraint ability of good stability, plastic-sealed body and the metal leg of the quality of ball bonding and production reliability.
The purpose of this utility model is achieved in that a kind of no-pad lead frame structure, comprise pin, front at described pin is provided with the first metal layer, be provided with second metal level at the back side of described pin, described pin front extends to the follow-up next door, zone that needs cartridge chip as much as possible, be equipped with packless plastic packaging material in the zone of described pin periphery and the zone between pin and the pin, described packless plastic packaging material links into an integrated entity the pin bottom, and make described pin back side size less than the positive size of pin, form up big and down small pin configuration.
The beneficial effects of the utility model are:
1) but the glued membrane of one deck costliness high temperature resistance need not sticked in the back side of this kind lead frame.So directly reduced high cost.
2) but because the glued membrane of one deck high temperature resistance need not sticked in the back side of this kind lead frame yet, so the load technology in encapsulation process is except using conduction or nonconducting resin technology, can also adopt the technology of eutectic technology and slicken solder to carry out load, so selectable product category is just wide.
3) but again because the glued membrane of one deck high temperature resistance need not sticked in the back side of this kind lead frame, guaranteed the stability of ball bonding bonding parameter, guaranteed the quality of ball bonding and the stability of production reliability.
4) but again because this kind lead frame need not stick the glued membrane of one deck high temperature resistance, and the plastic package process process in encapsulation process can not cause between lead frame and the glued membrane fully and infiltrate plastic packaging material.
5) because the zone between described pin and pin is equipped with packless soft gap filler, this packless soft gap filler has the filler plastic packaging material to envelope the height of whole pin with the routine in the plastic packaging process, so the constraint ability of plastic-sealed body and pin just becomes big, do not have the problem that produces pin again.
6) owing to adopted positive method of separating the etching operation with the back side, so in the etching operation, can form slightly little and the structure that positive pin size is big slightly of the size of back side pin, and slided by the tighter more difficult generation that packless plastic packaging material coated and falling pin with the size that varies in size up and down of a pin.
7) separate etched technology owing to used the back side with the front, so the pin in lead frame front can be extended to as much as possible the follow-up next door, zone that needs cartridge chip, impel chip and pin distance significantly to shorten, shown in Fig. 8～9, so the cost of metal wire also can significantly reduce (the especially metal wire of Ang Gui proof gold matter).
8) also because the shortening of metal wire makes also significantly speedup (the especially product of storage class and the calculating that needs mass data of signal output speed of chip, more outstanding), because the length of metal wire has shortened, so existing dead resistance/parasitic capacitance of metal wire and parasitic electric pole are to the also significantly reduction of interference of signal.
9) because of having used the elongation technology of pin,, make the volume and the area of encapsulation significantly to dwindle so can be easy to produce the distance between high pin number and highdensity pin and the pin.
10) because volume after being encapsulated is significantly dwindled, more direct embody material cost significantly descend with because the minimizing of material usage also significantly reduces the puzzlement of discarded object environmental protection.
(4) description of drawings
Fig. 1 is the utility model no-pad lead frame structure schematic diagram.
Fig. 2 was for sticked the resistant to elevated temperatures glued membrane figure of one deck operation in the past at the back side of metal substrate.
Fig. 3 was for to adopt the front of metal substrate to carry out chemical etching and surface electrical coating flow diagram in the past.
Fig. 4 was for formed insulation pin schematic diagram in the past.
Fig. 5 pin figure for what formed in the past.
Fig. 6 is an encapsulating structure schematic diagram in the past.
Fig. 7 is 6 vertical view.
Fig. 8 is for adopting the encapsulating structure schematic diagram of the utility model lead frame.
Fig. 9 is 8 vertical view.
Reference numeral among the figure:
(5) embodiment
Referring to Fig. 1, Fig. 1 is the utility model no-pad lead frame structure schematic diagram.As seen from Figure 1, the utility model no-pad lead frame structure, comprise pin 2, described pin 2 fronts extend to the follow-up next door, zone that needs cartridge chip as much as possible, be provided with the first metal layer 4 in the front of described pin 2, be provided with second metal level 5 at the back side of described pin 2, be equipped with packless plastic packaging material 3 in the zone of described pin 2 peripheries and the zone between pin 2 and the pin 2, described packless plastic packaging material 3 links into an integrated entity the pin bottom, and make described pin back side size less than the positive size of pin, form up big and down small pin configuration.
The utility model can be electroplated the making that the first metal layer 4 or regional area are electroplated the first metal layer 4 because of the Zone Full that need carry out in the front of above-mentioned pin 2 of chip functions.
Claims (1)
1. no-pad lead frame structure, comprise pin (2), be provided with the first metal layer (4) in the front of described pin (2), be provided with second metal level (5) at the back side of described pin (2), it is characterized in that: described pin (2) front extends to the follow-up next door, zone that needs cartridge chip, be equipped with packless plastic packaging material (3) in the zone of described pin (2) periphery and the zone between pin (2) and the pin (2), described packless plastic packaging material (3) links into an integrated entity the pin bottom, and make described pin (2) back side size less than the positive size of pin (1), form up big and down small pin configuration.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010201826228U CN201681895U (en) | 2010-04-30 | 2010-04-30 | Lead frame structure without base island |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010201826228U CN201681895U (en) | 2010-04-30 | 2010-04-30 | Lead frame structure without base island |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN201681895U true CN201681895U (en) | 2010-12-22 |
Family
ID=43346931
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2010201826228U Expired - Lifetime CN201681895U (en) | 2010-04-30 | 2010-04-30 | Lead frame structure without base island |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN201681895U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101814481A (en) * | 2010-04-30 | 2010-08-25 | 江苏长电科技股份有限公司 | No-pad lead frame structure and production method thereof |
| CN103130173A (en) * | 2011-11-24 | 2013-06-05 | 无锡华润安盛科技有限公司 | Leadframe array, packaging structure and island-free leadframe for micro-electromechanical system (MEMS) chip packaging, |
-
2010
- 2010-04-30 CN CN2010201826228U patent/CN201681895U/en not_active Expired - Lifetime
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101814481A (en) * | 2010-04-30 | 2010-08-25 | 江苏长电科技股份有限公司 | No-pad lead frame structure and production method thereof |
| CN103130173A (en) * | 2011-11-24 | 2013-06-05 | 无锡华润安盛科技有限公司 | Leadframe array, packaging structure and island-free leadframe for micro-electromechanical system (MEMS) chip packaging, |
| CN103130173B (en) * | 2011-11-24 | 2015-11-25 | 无锡华润安盛科技有限公司 | For MEMS chip encapsulation without little island lead frame, array of leadframes and encapsulating structure |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101814482B (en) | Base island lead frame structure and production method thereof | |
| CN201752013U (en) | Packaging structure capable of directly placing multi-ring pin by chip and passive device | |
| CN201681936U (en) | Passive component packaging structure without substrate | |
| CN201681895U (en) | Lead frame structure without base island | |
| CN201752004U (en) | Packaging structure for arranging chip directly | |
| CN201681893U (en) | Lead frame structure with base islands | |
| CN201752008U (en) | Paddle-free lead frame structure with static discharge ring | |
| CN201752006U (en) | Encapsulation structure with base island and multiple circles of pins | |
| CN201681896U (en) | No-paddle dap packaging structure | |
| CN201752011U (en) | Foundation island-free and multi-ring pin packaging structure | |
| CN201681897U (en) | Non-base island multi-pin static releasing coil packing structure | |
| CN201681890U (en) | Lead frame structure for direct placement by chip | |
| CN201681935U (en) | Non-paddle multiturn pin static release ring passive device packaging structure | |
| CN201681873U (en) | Multiple base island exposing type single-ring pin packaging structure | |
| CN201681933U (en) | Pin-type packaging structure with direct placement of chip and reactive device | |
| CN201752007U (en) | Lead frame structure with base island and multiple circles of pins | |
| CN201681894U (en) | Substrate-free lead frame structure with multiple circles of pins | |
| CN201681892U (en) | Basic island packaging structure | |
| CN201766077U (en) | Packaging structure with paddle for passive device | |
| CN201752009U (en) | Lead frame structure of static discharge coil with multiple circles of pins but without base island | |
| CN201752010U (en) | Base-island-free electrostatic discharge ring packaging structure | |
| CN201681938U (en) | Non-paddle multiturn pin passive device packaging structure | |
| CN201681934U (en) | Encapsulating structure for passive device with base island and multi-ring pins | |
| CN201681891U (en) | Direct-chip-placing multi-turn pin type encapsulation structure | |
| CN201752005U (en) | Direct chip arrangement multi-ring pin mode lead frame structure |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CX01 | Expiry of patent term | ||
| CX01 | Expiry of patent term |
Granted publication date: 20101222 |