CN201655114U - Hardware structure of DSP experimental platform - Google Patents
Hardware structure of DSP experimental platform Download PDFInfo
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- CN201655114U CN201655114U CN2010201719160U CN201020171916U CN201655114U CN 201655114 U CN201655114 U CN 201655114U CN 2010201719160 U CN2010201719160 U CN 2010201719160U CN 201020171916 U CN201020171916 U CN 201020171916U CN 201655114 U CN201655114 U CN 201655114U
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Abstract
The utility model discloses a hardware structure of a DSP experimental platform, comprising a DSP, a CPLD, and a power supply circuit, to the data interface of DSP are connected a EEPROM memory chip and a RAM memory chip, to the communication interface are respectively connected an I2C bus chip, a RS232 serial chip, a CAN bus chip, a PS/2 interface, an SPI bus interface and an 8-bit parallel data bus interface; CPLD is in communicating connection with the SPI interface, JTAG debugging interfaces of CPLD and DSP are hung in the air, to the data interface of CPLD are connected a temperature sensor and a buzzer, to the SPI interface is connected an SD stand, and an LED and an audio frequency decoding board; the power supply circuit module generates 12V, 5V, and 3.3 V power, which are connected to the power supply interface of each chip.
Description
Technical field
The utility model relates to electronic experiment platform field, is specially a kind of hardware configuration of DSP experiment porch.
Background technology
The DSP experiment porch plays very big help as the experiment apparatus that arrives commonly used in the logical circuit study to teaching.DSP experiment porch of the prior art, because insufficient memory is big, so its algorithm is also comparatively simple; Simultaneously the most function of DSP experiment porch of the prior art is fairly simple, but opposite be that price is very expensive.
The utility model content
The purpose of this utility model provides a kind of hardware configuration of DSP experiment porch, by DSP experiment porch and CPLD are combined, to solve traditional DSP experiment porch function singleness, algorithm simple question.
In order to achieve the above object, the technical scheme that the utility model adopted is:
A kind of hardware configuration of DSP experiment porch, it is characterized in that: the power circuit that includes DSP, CPLD, constitutes by regulator, be connected to eeprom memory chip, RAM and ROM storage chip on the data-interface of described DSP, be connected to I on the communication interface of described DSP respectively
2C bus chip, RS232 serial port chip, CAN bus chip, PS/2 interface, spi bus interface, 8 bit parallel bus interface, also be connected one by one with liquid crystal interface chip, Ethernet chip respectively on the data-interface of described DSP by two level transferring chip, described Ethernet chip is connected with a RJ45 seat by signal wire, and described DSP is reserved with the motor-driven plate interface; Described CPLD is connected with described spi bus, the JTAG debugging interface of CPLD and DSP is vacant, be connected to temperature sensor, hummer on the data-interface of CPLD, be connected to eight toggle switch on the digital-quantity input interface of CPLD, be connected to eight light emitting diodes on the corresponding digital-quantity output interface, also be connected to the charactron and the button of quaternity on the data-interface of described CPLD; Be connected to the SD deck on the described spi bus, be connected to led board and audio decoder plate on the spi bus interface; Described power circuit module generates 12V, 5V, and the 3.3V power supply is connected with the power interface of each chip.
In the utility model, CPLD and DSP are realized mutual communication by the SPI interface, increased the function of whole DSP experiment porch greatly, not only can carry out the study of DPS in use, yet can carry out the study of CPLD simultaneously.DSP is connected to the RAM chip, with data storage and the program's memory space of expansion DSP, the complicated algorithm that can realize of DSP is calculated, and had copying.DSP is connected to the various communication interfaces chip, can realize that by a plurality of communication interface chips DSP and outside other chip portfolios of experiment porch use, and have increased the usable range of DSP experiment porch greatly.Be circumscribed with led board and audio decoder plate on the SPI interface, increased the anecdote of DSP experiment greatly, experimental result can be displayed more intuitively, while SPI interface chip is reserved with a plurality of interfaces can carry out the circuit expansion.
The utility model major advantage is:
1, each functions of modules is clear, connects simple and convenient.
2, DSP is connected to multiple storage chip, make platform both can in-circuit emulation operation, again can the programming offline operation, enough external memory spaces make loaded down with trivial details complicated algorithm also can move.
3, realized most function expansions and bus experiment, and more senior experiment is provided, development platform is upward-compatible, and postgraduate's study is suitable for exploitation is same.
4, residence religion amusement has strengthened the recreational of experiment, no longer is confined to simple uninteresting meaningless study such as digital operation, and the experiment of having dosed more visual pattern, vivid and interesting.
5, the software implementation of hardware such as logical circuit has become the basic concept of numerous designs, the study of complex logic array able to programme (CPLD) is also quite important, and the JTAG debug port of CPLD is reserved, and the user also can do the CPLD related experiment, study CPLD relevant knowledge has been accomplished " a tractor serves several purposes ".
Description of drawings
Fig. 1 is the utility model hardware configuration synoptic diagram.
Embodiment
As shown in Figure 1.A kind of hardware configuration of DSP experiment porch, the power circuit that includes DSP that model is TMS320LF2407A, CPLD that model is EMP240T100C5N, constitutes by regulator, regulator has three, wherein two models are LM2596, export 12V and 5V voltage respectively, also having a model is LM1117T, output 3.3V voltage.The eeprom memory chip, the model that are connected to model on the data-interface of DSP and are AT24C16 are 6416 RAM storage chip, are connected to the I that model is AT24C16 on the communication interface of DSP respectively
2C bus chip, model are the RS232 serial port chip of MAX232, CAN bus chip, PS/2 interface, SPI interface, the 8 bit parallel bus interface that model is 82C250; The level transferring chip that also is LVC16245A by two models on the data-interface of DSP is that the Ethernet chip of RLT8019AS is connected one by one with liquid crystal interface chip, model respectively, Ethernet chip is connected with a RJ45 seat by signal wire, and DSP is reserved with the motor-driven plate interface; CPLD is connected with the SPI interface, the JTAG debugging interface of CPLD and DSP is vacant, be connected to temperature sensor, hummer that model is 18B20 on the data-interface of CPLD, be connected to eight toggle switch on the digital-quantity input interface of CPLD, be connected to eight light emitting diodes on the corresponding digital-quantity output interface, also be connected to the charactron and the button of quaternity on the data-interface of CPLD; Be connected to the SD deck on the spi bus interface, be connected to led board and audio decoder plate; The power circuit module generates 12V, 5V, and the 3.3V power supply is connected with the power interface of each chip.
Claims (1)
1. the hardware configuration of a DSP experiment porch, it is characterized in that: the power circuit that includes DSP, CPLD, constitutes by regulator, be connected to eeprom memory chip, RAM and ROM storage chip on the data-interface of described DSP, be connected to I on the communication interface of described DSP respectively
2C bus chip, RS232 serial port chip, CAN bus chip, PS/2 interface, spi bus interface, 8 bit parallel bus interface, also be connected one by one with liquid crystal interface chip, Ethernet chip respectively on the data-interface of described DSP by two level transferring chip, described Ethernet chip is connected with a RJ45 seat by signal wire, and described DSP is reserved with the motor-driven plate interface; Described CPLD is connected with described spi bus, the JTAG debugging interface of CPLD and DSP is vacant, be connected to temperature sensor, hummer on the data-interface of CPLD, be connected to eight toggle switch on the digital-quantity input interface of CPLD, be connected to eight light emitting diodes on the corresponding digital-quantity output interface, also be connected to the charactron and the button of quaternity on the data-interface of described CPLD; Be connected to the SD deck on the described spi bus, be connected to led board and audio decoder plate on the spi bus interface; Described power circuit module generates 12V, 5V, and the 3.3V power supply is connected with the power interface of each chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010201719160U CN201655114U (en) | 2010-04-26 | 2010-04-26 | Hardware structure of DSP experimental platform |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010201719160U CN201655114U (en) | 2010-04-26 | 2010-04-26 | Hardware structure of DSP experimental platform |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN201655114U true CN201655114U (en) | 2010-11-24 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN2010201719160U Expired - Fee Related CN201655114U (en) | 2010-04-26 | 2010-04-26 | Hardware structure of DSP experimental platform |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102760367A (en) * | 2011-04-29 | 2012-10-31 | 中国矿业大学 | PSOC-CPLD (Programmable System On Chip-Complex Programmable Logic Device) electronic comprehensive experiment device |
| CN104699548A (en) * | 2013-12-04 | 2015-06-10 | 中国直升机设计研究所 | Method for solving SPI communication error between DSP and EEPROM at high temperature |
| CN105047051A (en) * | 2015-04-28 | 2015-11-11 | 北京百科融创教学仪器设备有限公司 | Digital signal processing (DSP) experimental box for teaching purpose |
| CN108447363A (en) * | 2018-05-11 | 2018-08-24 | 西安电子科技大学 | Common bus protocol experiment porch based on STM32 |
| CN115080473A (en) * | 2022-06-29 | 2022-09-20 | 海光信息技术股份有限公司 | Multi-chip interconnection system and safe starting method based on same |
-
2010
- 2010-04-26 CN CN2010201719160U patent/CN201655114U/en not_active Expired - Fee Related
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102760367A (en) * | 2011-04-29 | 2012-10-31 | 中国矿业大学 | PSOC-CPLD (Programmable System On Chip-Complex Programmable Logic Device) electronic comprehensive experiment device |
| CN104699548A (en) * | 2013-12-04 | 2015-06-10 | 中国直升机设计研究所 | Method for solving SPI communication error between DSP and EEPROM at high temperature |
| CN105047051A (en) * | 2015-04-28 | 2015-11-11 | 北京百科融创教学仪器设备有限公司 | Digital signal processing (DSP) experimental box for teaching purpose |
| CN108447363A (en) * | 2018-05-11 | 2018-08-24 | 西安电子科技大学 | Common bus protocol experiment porch based on STM32 |
| CN115080473A (en) * | 2022-06-29 | 2022-09-20 | 海光信息技术股份有限公司 | Multi-chip interconnection system and safe starting method based on same |
| CN115080473B (en) * | 2022-06-29 | 2023-11-21 | 海光信息技术股份有限公司 | Multi-chip interconnection system and safe starting method based on same |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20101124 Termination date: 20110426 |