CN115080473A - A multi-chip interconnection system and a secure boot method based thereon - Google Patents

Abstract

The invention provides a multi-chip interconnection system and a secure boot method based thereon. The multi-chip interconnection system includes a circuit board, and a firmware storage device and at least two chips are arranged on the circuit board. At least two chips are interconnected by a chip interconnect bus. The master chip is directly connected to the firmware storage device, and each slave chip is directly connected to the master chip or indirectly connected to the master chip through other slave chips. It also includes a high-speed storage device connected to the chip interconnect bus, and all chips share the high-speed storage device. The firmware storage device stores the same firmware used by all chips, the master chip loads the same firmware from the firmware storage device to the high-speed storage device, so that the master chip and each slave chip obtain the same firmware from the high-speed storage device. data. In a multi-chip scenario where the same firmware is used for multiple chips, the legality verification time is shortened, the legality verification efficiency is improved, and the secure boot time of the entire system can be effectively shortened.

Description

A multi-chip interconnection system and a secure boot method based thereon

technical field

The present invention relates to the field of chip technology, in particular to a multi-chip interconnection system and a secure boot method based thereon.

Background technique

Multi-chip means that multiple chips work together through bus interconnection, and externally appear as a complete system. The interconnection method of the multi-chip structure in the processor field can be expressed as the interconnection of multiple single-chip modules (Single-Chip Module, SCM for short), or it can be expressed as one or more homogeneous multi-chip packages (Multi -Chip Module, MCM for short) interconnection, and can also be expressed as one or more heterogeneous multi-chip package (System In Package, SIP for short) interconnection. The type of multi-chip interconnection can be line, ring, star, and the like. Secure boot is a process of verifying the off-chip trusted firmware in turn through the built-in trusted root of the chip, so as to realize the trusted boot of the system. Through secure boot, the tampered firmware can be effectively prevented from being executed on the chip, thereby ensuring the reliability and security of the entire system. The corresponding multi-chip secure boot is to realize the secure boot process under the multi-chip structure.

In the secure boot process, one of the steps is the process of loading the basic firmware. This process is critical in the multi-chip secure boot process. For scenarios with a large number of chips, the loading method of the basic firmware directly affects the boot time and security of the system. That is, how to quickly and securely load firmware for multiple chips is a key issue for multi-chip secure boot. In the existing design methods for motherboards and multi-chip structures, for consideration of cost and simplicity of motherboard design, the common sense in the industry is to design only one firmware storage device (usually Flash, flash memory) on the motherboard. The connection method of the multi-chip structure and the firmware storage device can be summarized into two categories. One type (referred to as scheme a) is: only one chip is connected to the Flash, and this chip acts as the master chip, responsible for receiving read and write requests from the slave chip, and acting as an agent for data access of its firmware storage device. The other type (referred to as scheme b) is: each chip is connected to the Flash, and each chip can individually access the firmware storage device in turn to obtain data. Since the firmware storage device usually uses a low-speed serial SPI (Serial Peripheral Interface, serial peripheral interface) interface (the rate is in the order of 100Mbps), and the inter-chip Link (interconnection) usually uses a high-speed interface (the rate is 10Gbps). level above), so the firmware loading efficiency of scheme a and scheme b are equivalent, and both are approximately equal to the total time to read all firmware data from the firmware storage device. For a scenario where multiple chips in a multi-chip structure use different firmware, limited by the fact that all firmware data must be read from the firmware storage device, the above solutions a and b are both reasonable. For the scenario where multiple chips in a multi-chip structure use the same firmware, solutions a and b need to repeatedly read the same firmware from the firmware storage device, which will seriously affect the system startup time when the number of chips is large.

SUMMARY OF THE INVENTION

The present invention provides a multi-chip interconnection system and a secure boot method based thereon, which can shorten the loading time of the same firmware, shorten the validity verification time, and improve the validity under the multi-chip scenario where the same firmware is used for multiple chips. Verify efficiency and effectively shorten the safe startup time of the entire system.

In a first aspect, the present invention provides a multi-chip interconnection system, the multi-chip interconnection system includes a circuit board on which a firmware storage device and at least two chips are arranged. At least two chips are interconnected through a chip interconnect bus, and the at least two chips include a master chip and other slave chips. The master chip is directly connected to the firmware storage device, and each slave chip is directly connected to the master chip or indirectly connected to the master chip through other slave chips. The multi-chip interconnection system further includes a high-speed storage device connected to the chip interconnection bus, and all chips share the high-speed storage device. The same firmware used by all chips is stored in the firmware storage device, the master chip is used to load the same firmware from the firmware storage device to the high-speed storage device, so that the master chip and each slave chip obtain the same firmware from the high-speed storage device firmware execution data. A legality verification module is also arranged in the main chip, and the legality verification module is used to verify the legality of the same firmware loaded into the high-speed storage device.

In the above solution, by setting a high-speed storage device connected to the chip interconnection bus, in the scenario where the same firmware used by all chips is stored in the firmware storage device, the main chip only needs to access the low-speed firmware storage device once. The same firmware is loaded from the firmware storage device to the high-speed storage device, so that the master chip and other slave chips use the chip interconnect bus to obtain the same firmware from the high-speed storage device during the process of security verification or execution of the same firmware. Firmware execution data for firmware. And the main chip will only verify the validity of the same firmware after loading the same firmware into the high-speed storage device, so that the interactive process of legality verification also runs between the high-speed transmission chip interconnection bus and the high-speed storage device, shortening the time. Legality verification time, improve legality verification efficiency. Compared with multiple chips in the prior art that repeatedly read the firmware execution data of the same firmware from the firmware storage device through the chip interconnect bus, the solution of the present application is optimized to use the chip interconnect bus from the high-speed storage device. The firmware execution data of the same firmware is read in the firmware, and the read rate of the data read from the firmware storage device is increased from the order of 100Mbps to the order of 10Gbps, and the transmission rate between the chip and the shared high-speed storage device is low. The advantage of more than 100 times the access rate of the firmware storage device greatly shortens the time for each chip to read the firmware execution data. That is, in a multi-chip scenario where the same firmware is used for multiple chips, the solution of the present application can effectively shorten the safe startup time of the entire system. Due to the multi-chip structure in the processor field, whether it is a homogeneous structure or a heterogeneous structure, there are a large number of identical chips in the entire system, and the same chips usually use the same firmware due to the similar initialization process. When the solution is applied to the multi-chip structure in the processor field, the loading time of the same firmware can be shortened, the validity verification time can be shortened, the validity verification efficiency can be improved, and the safe startup time of the entire system can be greatly shortened.

In a specific embodiment, at least two chips are provided with status registers for synchronous use. After the master chip completes verifying the legitimacy of the same firmware loaded into the high-speed storage device, the master chip also changes the status register from the first state to the second state to broadcast notification to all slave chips. After the master chip completes the legality verification, it broadcasts the information to all other slave chips in time. Since the initialization process of the same firmware is similar for multiple chips, other slave chips do not need to repeat the legality verification for the same firmware. Further reduction of safe boot time.

In a specific implementation manner, the status register is a register integrated in the main chip, so that the main chip can quickly change the state of the status register.

In a specific embodiment, the high-speed storage device supports concurrent access of at least two chips, so that multiple chips can concurrently acquire the firmware code of the same firmware from the high-speed storage device. Therefore, as the number of slave chips increases, this technical solution The overall system startup time does not increase accordingly.

In a specific embodiment, the firmware execution data includes firmware code and independent variable data for each chip. The high-speed storage device is divided into a first storage space and at least two second storage spaces. The first storage space is used to store firmware codes; at least two second storage spaces are in one-to-one correspondence with at least two chips, and each second storage space is used to store independent variable data of the corresponding chip. And each chip internally maps the first storage space address and the second storage space address corresponding to the chip to the same virtual address. It is convenient for the same firmware code to be executed concurrently in multiple chips.

In a specific implementation manner, each chip is provided with a cryptographic module, and key agreement is supported between the cryptographic modules in at least two chips. Each chip encrypts the plaintext to be written in the high-speed storage device into ciphertext through its internal cryptographic module and writes it into the high-speed storage device; each chip also reads and decrypts the stored data in the high-speed storage device through its internal cryptographic module. ciphertext. By adding a cipher module in each chip, and the cipher modules of multiple chips support key negotiation, the negotiated key is correspondingly configured in the cipher module, so that all cipher texts are stored in the high-speed storage device. . It not only makes it impossible for attackers to deduce the key to decrypt the ciphertext in the high-speed storage device, but also prevents the attacker from tampering and then encrypting it and putting it back into the high-speed storage device. Moreover, if the attacker directly tampers with the ciphertext, the decrypted content is usually not the correct instruction, which will directly cause the system to crash and prevent the attacker from attacking.

In a specific embodiment, the cryptographic modules in at least two chips generate a shared key through key negotiation; the shared key is used for each cryptographic module to encrypt plaintext into ciphertext, or decrypt ciphertext into plaintext .

In a specific embodiment, the cryptographic module further encrypts the address information to be stored in the high-speed storage device into the address ciphertext by encrypting the ciphertext. Make the address where the data will be saved also participate in the encryption calculation, so the attacker cannot attack by repeatedly placing the firmware ciphertext data.

In a specific embodiment, the high-speed storage device is arranged outside the chip of at least two chips, so that the slave chip can choose whether to access the high-speed storage device through the master chip, so that each slave chip can access the high-speed storage device with an optimal access path. device. Or the high-speed storage device is arranged in the main chip, so that the main chip can load the same firmware from the firmware storage device into the high-speed storage device.

In a second aspect, the present invention also provides a secure boot method based on any of the above-mentioned multi-chip interconnection systems. The secure boot method includes: the main chip loads the same firmware stored in the firmware storage device into the high-speed storage device; The chip verifies the legitimacy of the same firmware loaded into the high-speed storage device; the master chip and each slave chip obtain the firmware execution data of the same firmware from the high-speed storage device.

In the above solution, by setting a high-speed storage device connected to the chip interconnection bus, in the scenario where the same firmware used by all chips is stored in the firmware storage device, the main chip only needs to access the low-speed firmware storage device once. The same firmware is loaded from the firmware storage device to the high-speed storage device, so that the master chip and other slave chips use the chip interconnect bus to obtain the same firmware from the high-speed storage device during the process of security verification or execution of the same firmware. Firmware execution data for firmware. After the main chip loads the same firmware into the high-speed storage device, the legality verification of the same firmware is carried out, so that the interactive process of legality verification also runs between the high-speed transmission chip interconnection bus and the high-speed storage device, shortening the legal It reduces the time for legality verification and improves the efficiency of legality verification. Compared with multiple chips in the prior art that repeatedly read the firmware execution data of the same firmware from the firmware storage device through the chip interconnect bus, the solution of the present application is optimized to use the chip interconnect bus from the high-speed storage device. The firmware execution data of the same firmware is read in the firmware, and the read rate of the data read from the firmware storage device is increased from the order of 100Mbps to the order of 10Gbps, and the transmission rate between the chip and the shared high-speed storage device is low. The advantage of more than 100 times the access rate of the firmware storage device greatly shortens the time for each chip to read the firmware execution data. That is, in a multi-chip scenario where the same firmware is used for multiple chips, the solution of the present application can effectively shorten the safe startup time of the entire system. Due to the multi-chip structure in the processor field, whether it is a homogeneous structure or a heterogeneous structure, there are a large number of identical chips in the entire system, and the same chips usually use the same firmware due to the similar initialization process. When the solution is applied to the multi-chip structure in the processor field, the loading time of the same firmware can be shortened, the validity verification time can be shortened, the validity verification efficiency can be improved, and the safe startup time of the entire system can be greatly shortened.

In a specific embodiment, at least two chips are provided with status registers for synchronous use. After the master chip completes verifying the validity of the same firmware loaded into the high-speed storage device, the secure boot method further includes: the master chip changes the state register from the first state to the second state to broadcast notification to all slave chips. After the master chip completes the legality verification, it broadcasts the information to all other slave chips in time. Since the initialization process of the same firmware is similar for multiple chips, other slave chips do not need to repeat the legality verification for the same firmware. Further reduction of safe boot time.

In a specific embodiment, the fact that the master chip and each slave chip obtain the firmware execution data of the same firmware from the high-speed storage device includes: the master chip and each slave chip concurrently access the high-speed storage device to obtain the firmware execution data of the same firmware data, so that multiple chips can concurrently acquire the firmware code of the same firmware from the high-speed storage device, so with the increase of the number of slave chips, the overall system startup time of the technical solution will not increase accordingly.

In a specific embodiment, the firmware execution data includes firmware code and independent variable data for each chip. The concurrent access of the master chip and each slave chip to the high-speed storage device includes: all chips are divided into the same first storage space in the high-speed storage device, and the first storage space is used to store firmware codes; each chip is also in the high-speed storage device. There is a second storage space corresponding to the chip, and the second storage space is used to store the independent variable data of the corresponding chip; the first storage space address and the second storage space address corresponding to the chip are mapped to the same inside each chip. virtual address. It is convenient for the same firmware code to be executed concurrently in multiple chips.

In a specific implementation manner, each chip is provided with a cryptographic module, and key agreement is supported between the cryptographic modules in at least two chips. The secure boot method also includes: performing key negotiation between cryptographic modules in at least two chips; each chip encrypts the plaintext to be written in the high-speed storage device into ciphertext through the cryptographic module in the chip and writes it into the high-speed storage device ; Each chip also reads and decrypts the ciphertext stored in the high-speed storage device through its cryptographic module. By adding a cipher module in each chip, and the cipher modules of multiple chips support key negotiation, the negotiated key is correspondingly configured in the cipher module, so that all cipher texts are stored in the high-speed storage device. . It not only makes it impossible for attackers to deduce the key to decrypt the ciphertext in the high-speed storage device, but also prevents the attacker from tampering and then encrypting it and putting it back into the high-speed storage device. Moreover, if the attacker directly tampers with the ciphertext, the decrypted content is usually not the correct instruction, which will directly cause the system to crash and prevent the attacker from attacking.

In a specific embodiment, performing key negotiation between the cryptographic modules in the at least two chips includes: performing key negotiation between the cryptographic modules in the at least two chips to generate a shared key. Encrypting the plaintext to be written in the high-speed storage device into ciphertext and then writing to the high-speed storage device includes: encrypting the plaintext to be written in the high-speed storage device into ciphertext using a shared key and writing to the high-speed storage device. Reading and decrypting the ciphertext stored in the high-speed storage device includes: reading and decrypting the ciphertext stored in the high-speed storage device using the shared key.

In a specific embodiment, encrypting the plaintext to be written in the high-speed storage device into ciphertext and then writing to the high-speed storage device further includes: further encrypting the address information to be stored in the high-speed storage device into the address ciphertext by encrypting the ciphertext. Make the address where the data will be saved also participate in the encryption calculation, so the attacker cannot attack by repeatedly placing the firmware ciphertext data.

Description of drawings

1 is a schematic block diagram of a multi-chip interconnection system provided by an embodiment of the present invention;

2 is a schematic block diagram of another multi-chip interconnection system provided by an embodiment of the present invention;

3 is a schematic block diagram of the workflow of the multi-chip interconnection system shown in FIG. 2;

Fig. 4 is the working flow chart of the multi-chip interconnection system shown in Fig. 2;

FIG. 5 is a schematic block diagram of a workflow of another multi-chip interconnection system provided by an embodiment of the present invention.

Reference number:

10-Firmware storage device 20-Master chip 21-Slave chip

201-Cryptographic Module 202-Control Module 30-High Speed Storage Device

Detailed ways

In order to make the purposes, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments It is only a part of the embodiments of the present invention, but not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

In order to facilitate understanding of the multi-chip interconnection system provided by the embodiment of the present invention, the following first describes the application scenario of the multi-chip interconnection system provided by the embodiment of the present invention. The multi-chip interconnection system is applied to a multi-chip interconnection system composed of multiple chips. in the system. The multi-chip interconnection system will be described in detail below with reference to the accompanying drawings.

Referring to FIG. 1 , a multi-chip interconnection system provided by an embodiment of the present invention includes a circuit board (not shown in the figure), and a firmware storage device 10 and at least two chips are arranged on the circuit board. At least two chips are interconnected through a chip interconnection bus (the thicker lines in FIG. 1 to FIG. 3 and FIG. 5 represent the chip interconnection bus), and the at least two chips include a master chip 20 and other slave chips twenty one. The master chip 20 is directly connected to the firmware storage device 10 , and each slave chip 21 is directly connected to the master chip 20 or indirectly connected to the master chip 20 through other slave chips 21 . The multi-chip interconnection system further includes a high-speed storage device 30 connected to the chip interconnection bus, and all chips share the high-speed storage device 30 . The same firmware used by all the chips is stored in the firmware storage device 10, and the master chip 20 is used to load the same firmware from the firmware storage device 10 to the high-speed storage device 30, so that the master chip 20 and each slave chip 21 are loaded from the high-speed storage device 30. The firmware execution data of the same firmware is acquired in the storage device 30 . A legality verification module is set in the main chip 20 , and the legality verification module is used to verify the legality of the same firmware loaded into the high-speed storage device 30 .

In the above solution, by setting the high-speed storage device 30 connected to the chip interconnection bus, in the scenario where the firmware storage device 10 stores the same firmware used by all chips, the main chip 20 only needs to access the low-speed firmware storage device. 10 times, the same firmware is loaded from the firmware storage device 10 to the high-speed storage device 30, so that the master chip 20 and other slave chips 21 use the chip interconnection bus during the security verification or execution of the same firmware. The firmware execution data of the same firmware is acquired from the high-speed storage device 30 . And the main chip 20 only performs legality verification on the same firmware after loading the same firmware into the high-speed storage device 30, so that the interactive process of legality verification also runs between the high-speed transmission chip interconnect bus and the high-speed storage device 30. time, shorten the legality verification time and improve the legality verification efficiency. Compared with the prior art, multiple chips repeatedly read the firmware execution data of the same firmware from the firmware storage device 10 through the chip interconnect bus. The firmware execution data of the same firmware is read in the device 30, and the read rate of the data read from the firmware storage device 10 is increased from the order of 100 Mbps to the order of 10 Gbps, using the transmission between the chip and the shared high-speed storage device 30. The rate is more than 100 times the access rate of the low-speed firmware storage device 10, which greatly shortens the time for each chip to read the firmware execution data. That is, in a multi-chip scenario where the same firmware is used for multiple chips, the solution of the present application can effectively shorten the safe startup time of the entire system. Due to the multi-chip structure in the processor field, whether it is a homogeneous structure or a heterogeneous structure, there are a large number of identical chips in the entire system, and the same chips usually use the same firmware due to the similar initialization process. When the solution is applied to the multi-chip structure in the processor field, the loading time of the same firmware can be shortened, the validity verification time can be shortened, the validity verification efficiency can be improved, and the safe startup time of the entire system can be greatly shortened. The above structures will be described in detail below with reference to the accompanying drawings.

When setting the circuit board, the circuit board may specifically be a mainboard in a server, or may be a circuit board composed of traces and vias in other scenarios. The circuit board is a carrying and interconnecting structure for setting the firmware storage device 10 and the chip, and can be realized by using a printed circuit board.

Referring to FIG. 1 , a firmware storage device 10 is provided on the circuit board, and the firmware storage device 10 is used as a storage medium to store the off-chip firmware of each chip, so that when the chip is started, each chip is loaded from the firmware storage device 10 corresponding to firmware to implement the corresponding functions. In specific settings, the firmware storage device 10 may use a memory such as but not limited to a flash memory (Flash). The firmware storage device 10 usually adopts an SPI interface, and its transfer rate is on the order of 100 Mbps. In this application, the firmware storage device 10 stores the same firmware used by all the above chips, that is, each of the at least two chips needs to load the same firmware during the startup process to implement corresponding functions.

Referring to FIG. 1 , at least two chips are further arranged on the circuit board, and the at least two chips are interconnected through a chip interconnection bus. Wherein, each chip in this may be a single chip package (SCM), a homogeneous multi-chip package (MCM), or a chip in an homogeneous multi-chip package. Even, each chip can be a heterogeneous multi-chip package (SIP) or a chip in a heterogeneous multi-chip package. That is, each chip in the present application may specifically be a package formed by packaging a single or multiple homogeneous or heterogeneous chips, and may also be a chip in a package formed by packaging multiple homogeneous or heterogeneous chips. The present application does not limit whether the chip is a package or a bare chip in the package, but defines a manner in which a plurality of chips are connected through a chip interconnection bus. The chip interconnection bus may specifically be a chip interconnection bus formed in a package to interconnect different dies in the same package; it may also be a package substrate or a circuit board formed outside the package to connect A chip interconnect bus for different packages or chips within different packages. The data transmission rate of the chip interconnection bus is far greater than the data transmission rate between the chip and other devices other than the at least two chip systems. Specifically, the data transmission rate of the chip interconnection bus may be set to be above the order of 10 Gbps, that is, the chip interconnection bus interface used between chips is a high-speed interface.

Continuing to refer to FIG. 1 , the at least two chips include a main chip 20 , and the main chip 20 is directly connected to the firmware storage device 10 , specifically, directly connected to the firmware storage device 10 through an SPI bus. The data transmission rate of the bus directly connected between the firmware storage device 10 and the main chip 20 is lower than the data transmission rate of the chip interconnection bus. As shown in FIG. 1 , other chips except the master chip 20 in the at least two chips are used as slave chips 21 and are directly connected to the master chip 20 through a chip interconnection bus, or through the chip interconnection bus and other slave chips. 21 is indirectly connected to the main chip 20 . It should be noted that even if the slave chip 21 is indirectly connected to the master chip 20 through the chip interconnection bus and other slave chips 21, the data transmission rate between the slave chip 21 and the master chip 20 is much higher than that between the master chip 20 and the master chip 20. Data transfer rate between firmware storage devices 10 . When implementing the interconnection between the slave chip 21 and the master chip 20 , at least two chips may be interconnected in an interconnection manner such as, but not limited to, a line type, a ring type, a star type, and the like. As shown in FIG. 1 , at least two chips are interconnected by a chip interconnection bus line, that is, at least two chips are connected in a line topology structure through a chip interconnection bus. It should be noted that the manner of interconnecting the at least two chips is not limited to the linear interconnection manner shown in FIG. 1 , and other interconnection manners may also be used.

Referring to FIG. 1 , the multi-chip interconnection system further includes a high-speed storage device 30 , which is connected to the chip interconnection bus, so that the high-speed storage device 30 has a globally independent address. And all chips in at least two chips share the high-speed storage device 30 , so that each chip can access the high-speed storage device 30 . The high-speed storage device 30 has high-speed data access capability, so that each chip can access the high-speed storage device 30 at a higher data transfer rate when connected to the chip interconnection bus. In the specific setting, a random access memory (Random Access Memory, RAM) such as but not limited to a cache memory (Cache) can be used as the high-speed storage device 30, so that each chip can transmit at a high-speed data rate through the chip interconnection bus. Access to high-speed storage device 30 .

Referring to FIG. 1 , the high-speed storage device 30 can be arranged outside the chips of at least two chips, that is, not located in each chip, so that the slave chip 21 can choose whether to access the high-speed storage device 30 through the master chip 20, which is convenient for each chip. Each slave chip 21 accesses the high-speed storage device 30 with an optimal access path. Of course, referring to FIG. 5 , the high-speed storage device 30 can also be provided in the main chip 20 , so that the main chip 20 can load the same firmware from the firmware storage device 10 into the high-speed storage device 30 . It should be understood that this application does not limit the location of the high-speed storage device 30, but mainly restricts the high-speed storage device 30 to access the chip interconnection bus, so that multiple chips can share the high-speed storage device 30, and can transmit in high-speed quantities. speed to access the high-speed storage device 30.

During the secure boot process, referring to FIG. 1 and FIG. 4 , the main chip 20 can load the same firmware from the firmware storage device 10 to the high-speed storage device 30 . Specifically, the main chip 20 loads the same firmware stored in the firmware storage device 10 . firmware, and write the same firmware into the high-speed storage device 30, so that the master chip 20 and each slave chip 21 obtain the firmware execution data of the same firmware from the high-speed storage device 30 to perform verification, loading and other execution operations . By setting the high-speed storage device 30 connected to the chip interconnection bus, in the scenario where the firmware storage device 10 stores the same firmware used by all chips, the main chip 20 only needs to access the low-speed firmware storage device 10 once, and the same firmware is stored in the firmware storage device 10. The firmware is loaded from the firmware storage device 10 to the high-speed storage device 30, so that the master chip 20 and other slave chips 21 all use the chip interconnect bus from the high-speed storage device 30 in the process of security verification or execution of the same firmware. Get firmware execution data for that same firmware. Compared with the prior art, multiple chips repeatedly read the firmware execution data of the same firmware from the firmware storage device 10 through the chip interconnect bus. The firmware execution data of the same firmware is read in the device 30, and the read rate of the data read from the firmware storage device 10 is increased from the order of 100 Mbps to the order of 10 Gbps, using the transmission between the chip and the shared high-speed storage device 30. The rate is more than 100 times the access rate of the low-speed firmware storage device 10, which greatly shortens the time for each chip to read the firmware execution data. That is, in a multi-chip scenario where the same firmware is used for multiple chips, the solution of the present application can effectively shorten the safe startup time of the entire system. Due to the multi-chip structure in the processor field, whether it is a homogeneous structure or a heterogeneous structure, there are a large number of identical chips in the entire system, and the same chips usually use the same firmware due to the similar initialization process. When the solution is applied to the multi-chip structure in the processor field, the secure boot time of the entire system can be greatly shortened.

In addition, after loading the same firmware from the firmware storage device 10 into the high-speed storage device 30, the main chip 20 can also interact with the same firmware in the high-speed storage device 30 to verify the validity of the same firmware. Specifically, a legality verification module may be set in the main chip 20, and when the same firmware is loaded into the high-speed storage device 30, the legality verification module is used to verify the legality of the same firmware loaded into the high-speed storage device 30 . Only after the main chip 20 loads the same firmware into the high-speed storage device 30, does the same firmware verify the legality, so that the interactive process of legality verification also runs between the high-speed transmission chip interconnect bus and the high-speed storage device 30. , shorten the legality verification time and improve the legality verification efficiency. It should be understood that the main chip 20 is not limited to an implementation manner of performing legality verification by interacting with the same firmware loaded into the high-speed storage device 30, and other manners may also be used. For example, the main chip 20 may first interact with the same firmware in the firmware storage device 10 to verify its legitimacy, that is, before loading the same firmware in the firmware storage device 10, the main chip 20 verifies the legitimacy of the same firmware, The same firmware is loaded into the high-speed storage device 30 only after the validity verification is passed.

Further, a status register for synchronous use can also be set in at least two chips, and the status change of the status register is used to identify whether the master chip 20 completes the legality verification of the same firmware, so as to notify other slave chips 21 according to Its needs decide whether to verify the validity of the same firmware again. Specifically, after the main chip 20 completes the verification of the validity of the same firmware loaded into the high-speed storage device 30, the main chip 20 also needs to change the state register from the first state to the second state, where the first state may be binary The second state can be binary “1”. Of course, the opposite definition method can be adopted to notify all slave chips 21 by broadcast that the master chip 20 has completed the validity verification of the same firmware. After the master chip 20 completes the legality verification, it broadcasts the information to all other slave chips 21 in time. Since the initialization process of the same firmware by multiple chips is similar, other slave chips 21 do not need to repeat the legalization process for the same firmware. security verification, further shortening the secure boot time. When specifically selecting the status register, the master chip 20 can negotiate with each other slave chip 21 to use a register in the master chip 20 as the status register, so that the master chip 20 can quickly change the state of the status register. Of course, the status register may also be located in a register of any slave chip 21 .

When the master chip 20 and the slave chip 21 share access to the high-speed storage device 30, the software and hardware can be adjusted so that the high-speed storage device 30 supports concurrent access by at least two chips, so that multiple chips can concurrently access the high-speed storage device. The firmware code of the same firmware is obtained in 30, so with the increase of the number of slave chips 21, the overall system startup time of the technical solution will not increase accordingly. Taking FIG. 3 and FIG. 4 as an example, for the main chip 20, the time of the entire firmware loading process of the same firmware is: the main chip 20 loads the same firmware from the firmware storage device 10 to the shared firmware through the path 1→2→3. time of the high-speed storage device 30 . For the subsequent other master chips 20 and each slave chip 21, the subsequent master chip 20 passes the path 2→3, the slave chip 1 (the slave chips 1, 2, 3..., n in FIG. 3 and FIG. 4) Chip 1) goes through path 4→5, slave chip 2 (slave chip 2 in slave chips 1, 2, 3..., n in FIG. 3 and FIG. 4) passes through path 6→7, concurrently from the shared high-speed storage device 30 , to obtain the corresponding firmware execution data. When the master chip 20 and the slave chip 21 access the firmware execution data of the same firmware in the high-speed storage device 30, the firmware execution data may include firmware codes and independent variable data for each chip. Therefore, when implementing concurrent access, it is necessary to support multiple chips to concurrently access the same firmware code of the same firmware. When implementing the concurrent shared access of the master chip 20 and the slave chip 21 to the high-speed storage device 30, various implementation manners may be adopted. An implementation is exemplarily shown as follows.

The high-speed storage device 30 may be divided into a first storage space and at least two second storage spaces. Wherein, the first storage space is used to store a firmware code of the same firmware. The at least two second storage spaces are in one-to-one correspondence with the at least two chips, and each second storage space is used to store independent variable data of the corresponding chip. At this time, it is necessary to adjust the software inside each chip including the master chip 20 and the slave chip 21, so that the first storage space address and the second storage space address corresponding to the chip are mapped to the same virtual address inside each chip, which is convenient for the same A copy of the firmware code can be executed normally in multiple chips concurrently. It should be understood that the above only illustrates an implementation manner for supporting multiple chips to access the high-speed storage device 30 concurrently, and other implementation manners may also be adopted.

Furthermore, functional modules for ensuring security can be added, and when the firmware execution data is transmitted between the high-speed storage device 30 and the chip, the security of transmission is guaranteed by these functional modules. Specifically, referring to FIG. 2 , FIG. 3 and FIG. 5 , a cryptographic module 201 may be provided in each chip, and the cryptographic modules 201 in at least two chips support key negotiation, so that all the chips can communicate with each other. Ability to share symmetric keys. Afterwards, each chip encrypts the plaintext to be written in the high-speed storage device 30 into ciphertext through the cryptographic module 201 in the chip, and writes it into the high-speed storage device 30 . Each chip also reads and decrypts the ciphertext stored in the high-speed storage device 30 through the cryptographic module 201 therein. That is, when each chip writes, but not limited to, the same firmware into the high-speed storage device 30 , it first needs to encrypt the plaintext into ciphertext, and then write it into the high-speed storage device 30 . Specifically, referring to FIG. 2 , FIG. 3 and FIG. 5 , each chip is further provided with a control module 202 , which is connected to the cryptographic module 201 to control corresponding operations. As shown in FIG. 2 , after the control module 202 of the main chip 20 loads the same firmware from the firmware storage device 10, it is first handed over to the cryptographic module 201 in the main chip 20 for encryption into ciphertext, and then written to the high-speed storage device 30 . After the master chip 20 or each slave chip 21 loads firmware codes such as but not limited to the same firmware or independent variable data for each chip from the high-speed storage device 30, it needs to be decrypted by the cryptographic module 201 first, and then handed over to the The control module 202 in each chip performs corresponding operations. By adding a cryptographic module 201 to each chip, and the cryptographic modules 201 of multiple chips support key negotiation, the negotiated key is correspondingly configured in the cryptographic module 201, so that the stored data in the high-speed storage device 30 is enabled. All are ciphertext. It not only prevents the attacker from inferring the key to decrypt the ciphertext in the high-speed storage device 30 , but also prevents the attacker from tampering with it and then encrypting it and putting it back into the high-speed storage device 30 . Moreover, if the attacker directly tampers with the ciphertext, the decrypted content is usually not the correct instruction, which will directly cause the system to crash and prevent the attacker from attacking. In a more preferred embodiment, the cryptographic module 201 can also make the ciphertext encrypt the address information to be stored in the high-speed storage device 30 into an address ciphertext, that is, the address information of the data to be stored in the high-speed storage device 30 is also encrypted. , so that the address that will save the data also participates in the encryption calculation, so the attacker cannot attack by repeatedly placing the firmware ciphertext data.

Wherein, when the cryptographic modules 201 in the above at least two chips perform key negotiation, the cryptographic modules 201 in the at least two chips can generate a shared key through key negotiation, and the shared key is used for each cryptographic module 201 Encrypt plaintext to ciphertext, or decrypt ciphertext to plaintext.

In the solution described above, by setting the high-speed storage device 30 connected to the chip interconnection bus, in the scenario where the firmware storage device 10 stores the same firmware used by all chips, the main chip 20 only needs to access the low-speed firmware storage device 10. Once, the same firmware is loaded from the firmware storage device 10 to the high-speed storage device 30, so that the master chip 20 and other slave chips 21 all use the chip interconnect bus in the process of security verification or execution of the same firmware. The firmware execution data of the same firmware is acquired in the high-speed storage device 30 . And the main chip 20 only performs legality verification on the same firmware after loading the same firmware into the high-speed storage device 30, so that the interactive process of legality verification also runs between the high-speed transmission chip interconnect bus and the high-speed storage device 30. time, shorten the legality verification time and improve the legality verification efficiency. Compared with the prior art, multiple chips repeatedly read the firmware execution data of the same firmware from the firmware storage device 10 through the chip interconnect bus. The firmware execution data of the same firmware is read in the device 30, and the read rate of the data read from the firmware storage device 10 is increased from the order of 100 Mbps to the order of 10 Gbps, using the transmission between the chip and the shared high-speed storage device 30. The rate is more than 100 times the access rate of the low-speed firmware storage device 10, which greatly shortens the time for each chip to read the firmware execution data. That is, in a multi-chip scenario where the same firmware is used for multiple chips, the solution of the present application can effectively shorten the safe startup time of the entire system. Due to the multi-chip structure in the processor field, whether it is a homogeneous structure or a heterogeneous structure, there are a large number of identical chips in the entire system, and the same chips usually use the same firmware due to the similar initialization process. When the solution is applied to the multi-chip structure in the processor field, the loading time of the same firmware can be shortened, the validity verification time can be shortened, the validity verification efficiency can be improved, and the safe startup time of the entire system can be greatly shortened.

In addition, an embodiment of the present invention also provides a secure boot method based on any of the above-mentioned multi-chip interconnection systems. Referring to FIG. 1 , the secure boot method includes: the main chip 20 loads the same firmware stored in the firmware storage device 10 to the high-speed storage device 30 ; the master chip 20 verifies the validity of the same firmware loaded into the high-speed storage device 30 ; the master chip 20 and each slave chip 21 obtain the firmware execution data of the same firmware from the high-speed storage device 30 .

In the above solution, by setting the high-speed storage device 30 connected to the chip interconnection bus, in the scenario where the firmware storage device 10 stores the same firmware used by all chips, the main chip 20 only needs to access the low-speed firmware storage device. 10 times, the same firmware is loaded from the firmware storage device 10 to the high-speed storage device 30, so that the master chip 20 and other slave chips 21 use the chip interconnection bus during the security verification or execution of the same firmware. The firmware execution data of the same firmware is acquired from the high-speed storage device 30 . And the main chip 20 only performs legality verification on the same firmware after loading the same firmware into the high-speed storage device 30, so that the interactive process of legality verification also runs between the high-speed transmission chip interconnect bus and the high-speed storage device 30. time, shorten the legality verification time and improve the legality verification efficiency. Compared with the prior art, multiple chips repeatedly read the firmware execution data of the same firmware from the firmware storage device 10 through the chip interconnect bus. The firmware execution data of the same firmware is read in the device 30, and the read rate of the data read from the firmware storage device 10 is increased from the order of 100 Mbps to the order of 10 Gbps, using the transmission between the chip and the shared high-speed storage device 30. The rate is more than 100 times the access rate of the low-speed firmware storage device 10, which greatly shortens the time for each chip to read the firmware execution data. That is, in a multi-chip scenario where the same firmware is used for multiple chips, the solution of the present application can effectively shorten the safe startup time of the entire system. Due to the multi-chip structure in the processor field, whether it is a homogeneous structure or a heterogeneous structure, there are a large number of identical chips in the entire system, and the same chips usually use the same firmware due to the similar initialization process. When the solution is applied to the multi-chip structure in the processor field, the loading time of the same firmware can be shortened, the validity verification time can be shortened, the validity verification efficiency can be improved, and the safe startup time of the entire system can be greatly shortened. The above steps are described in detail below with reference to the accompanying drawings.

First, the main chip 20 loads the same firmware stored in the firmware storage device 10 into the high-speed storage device 30 . For a specific implementation manner, reference is made to the foregoing description of the multi-chip interconnection system, which will not be repeated here.

Also, referring to FIG. 4 , after the host chip 20 loads the same firmware stored in the firmware storage device 10 into the high-speed storage device 30 , the host chip 20 verifies the validity of the same firmware loaded into the high-speed storage device 30 . For a specific implementation manner, reference is made to the foregoing description of the multi-chip interconnection system, which will not be repeated here.

Status registers for synchronous use may also be provided in at least two chips, as described above in relation to the multi-chip interconnect system. The specific way of using the status register may be as follows: after the main chip 20 completes the verification of the validity of the same firmware loaded into the high-speed storage device 30, the main chip 20 also changes the status register from the first state to the second state to broadcast All slave chips 21 are notified. After the master chip 20 completes the legality verification, it broadcasts the information to all other slave chips 21 in time. Since the initialization process of the same firmware by multiple chips is similar, other slave chips 21 do not need to repeat the legalization process for the same firmware. security verification, further shortening the secure boot time.

Next, referring to FIG. 3 and FIG. 4 , the master chip 20 and each slave chip 21 acquire firmware execution data of the same firmware from the high-speed storage device 30 .

As described above in relation to the multi-chip interconnection system, when the master chip 20 and each slave chip 21 acquire the firmware execution data of the same firmware from the high-speed storage device 30, the master chip 20 and each slave chip 21 can be made concurrently Access the high-speed storage device 30 to obtain the firmware execution data of the same firmware, so that multiple chips can concurrently obtain the firmware code of the same firmware from the high-speed storage device 30. Therefore, as the number of slave chips 21 increases, the overall The system startup time does not increase accordingly. When the master chip 20 and the slave chip 21 access the firmware execution data of the same firmware in the high-speed storage device 30, the firmware execution data may include firmware codes and independent variable data for each chip. Therefore, when implementing concurrent access, it is necessary to support multiple chips to concurrently access the same firmware code of the same firmware. When implementing the concurrent shared access of the master chip 20 and the slave chip 21 to the high-speed storage device 30, various implementation manners may be adopted. An implementation is exemplarily shown as follows.

When the main chip 20 and each slave chip 21 concurrently access the high-speed storage device 30, all chips are divided into the same first storage space in the high-speed storage device 30, and the first storage space is used to store firmware codes; Each chip is further divided into a second storage space corresponding to the chip in the high-speed storage device 30, and the second storage space is used to store the independent variable data of the corresponding chip; the first storage space address and the first storage space address corresponding to the chip are stored inside each chip. Two memory space addresses are mapped to the same virtual address. It is convenient for the same firmware code to be executed concurrently in multiple chips. For a specific implementation manner, reference is made to the foregoing description of the multi-chip interconnection system, which will not be repeated here.

In addition, referring to FIG. 2 , FIG. 3 and FIG. 5 , each chip may also be provided with a cryptographic module 201 , and the cryptographic modules 201 in at least two chips support key negotiation. At this time, the secure boot method may further include: performing key negotiation between the cryptographic modules 201 in at least two chips; each chip encrypts the plaintext to be written into the high-speed storage device 30 through the cryptographic module 201 in the chip as The ciphertext is then written into the high-speed storage device 30 ; each chip also reads and decrypts the ciphertext stored in the high-speed storage device 30 through the cryptographic module 201 therein. By adding a cryptographic module 201 to each chip, and the cryptographic modules 201 of multiple chips support key negotiation, the negotiated key is correspondingly configured in the cryptographic module 201, so that the stored data in the high-speed storage device 30 is enabled. All are ciphertext. It not only prevents the attacker from inferring the key to decrypt the ciphertext in the high-speed storage device 30 , but also prevents the attacker from tampering with it and then encrypting it and putting it back into the high-speed storage device 30 . Moreover, if the attacker directly tampers with the ciphertext, the decrypted content is usually not the correct instruction, which will directly cause the system to crash and prevent the attacker from attacking. For a specific implementation manner, reference is made to the foregoing description of the multi-chip interconnection system, which will not be repeated here.

Wherein, when key negotiation is performed between the cryptographic modules 201 in the at least two chips, the cryptographic modules 201 in the at least two chips may perform key negotiation to generate a shared key. At this time, encrypting the plaintext to be written in the high-speed storage device 30 into ciphertext and then writing to the high-speed storage device 30 includes: encrypting the plaintext to be written in the high-speed storage device 30 into ciphertext using a shared key and then writing it into the high-speed storage device 30. At this time, reading and decrypting the ciphertext stored in the high-speed storage device 30 includes: reading and decrypting the ciphertext stored in the high-speed storage device 30 using the shared key.

Further, when the plaintext to be written in the high-speed storage device 30 is encrypted into ciphertext and then written into the high-speed storage device 30, the address information to be stored in the high-speed storage device 30 can also be encrypted into the address ciphertext by the ciphertext, so that the ciphertext is encrypted. The address where the data will be saved is also involved in the encryption calculation, so an attacker cannot attack by repeatedly placing the firmware ciphertext data.

The above are only specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art who is familiar with the technical scope disclosed by the present invention can easily think of changes or substitutions. All should be included within the protection scope of the present invention. Therefore, the protection scope of the present invention should be subject to the protection scope of the claims.

Claims (16)

1. A multichip interconnect system, comprising:

a circuit board;

a firmware storage device disposed on the circuit board;

at least two chips arranged on the circuit board and interconnected through a chip interconnection bus, wherein the at least two chips comprise a master chip and other slave chips; the main chip is directly connected with the firmware storage device, and each slave chip is directly connected with the main chip or indirectly connected with the main chip through other slave chips;

a high speed storage device accessing the chip interconnect bus and shared by all of the chips;

the firmware storage device stores the same firmware used by all the chips;

the main chip is used for loading the same firmware from the firmware storage device to the high-speed storage device so that the main chip and each slave chip can acquire firmware execution data of the same firmware from the high-speed storage device;

and a validity verification module is also arranged in the main chip and used for verifying the validity of the same firmware loaded in the high-speed storage device.

2. The multichip interconnect system according to claim 1, wherein status registers for synchronous use are provided in said at least two chips;

after the master chip finishes verifying the validity of the same firmware loaded into the high-speed storage device, the master chip also changes the status register from the first state to the second state to broadcast a notification to all slave chips.

3. The multichip interconnect system of claim 2, wherein the status register is a register integrated within the master chip.

4. The multichip interconnect system of claim 1, wherein the high speed memory device supports concurrent access by the at least two chips.

5. The multichip interconnect system according to claim 4, wherein the firmware execution data includes firmware code and independent variable data for each chip;

the high-speed storage device is divided into a first storage space and at least two second storage spaces; wherein the first storage space is used for storing the firmware codes; the at least two second storage spaces correspond to the at least two chips one by one, and each second storage space is used for storing the independent variable data of the corresponding chip;

and mapping the first storage space address and a second storage space address corresponding to the chip into the same virtual address in each chip.

6. The multichip interconnect system according to claim 1, wherein a cryptographic module is disposed in each chip, and key agreement is supported between cryptographic modules in said at least two chips;

each chip encrypts a plaintext to be written into the high-speed storage device into a ciphertext through the cryptographic module in the chip and writes the ciphertext into the high-speed storage device; each chip also reads and decrypts the ciphertext stored in the high-speed storage device through the cryptographic module in the chip.

7. The multichip interconnect system according to claim 6, wherein a shared key is generated between the cryptographic modules in the at least two chips through key agreement;

the shared secret key is used for each cryptographic module to encrypt the plaintext into the ciphertext or decrypt the ciphertext into the plaintext.

8. The multichip interconnect system of claim 6, wherein the cryptographic module further encrypts the address information that the ciphertext is to be stored in the high-speed storage device as an address ciphertext.

9. The multichip interconnect system according to claim 1, wherein said high speed storage device is disposed off-chip of said at least two chips; or the like, or, alternatively,

the high-speed storage device is disposed within the main chip.

10. A secure boot method of the multichip interconnect system according to claim 1, comprising:

the main chip loads the same firmware stored in the firmware storage device to the high-speed storage device;

the main chip verifies the validity of the same firmware loaded into the high-speed storage device;

the master chip and each slave chip acquire firmware execution data of the same firmware from the high-speed storage device.

11. The secure boot method according to claim 10, wherein a status register for synchronous use is provided in the at least two chips;

after the master chip finishes verifying the validity of the same firmware loaded into the high-speed storage device, the secure boot method further comprises: the master chip changes the status register from a first state to a second state to broadcast a notification to all slave chips.

12. The secure boot method of claim 10, wherein the master chip and each slave chip obtaining firmware execution data of the same firmware from the high-speed storage device comprises:

the master chip and each slave chip concurrently access the high-speed storage device to obtain firmware execution data of the same firmware.

13. The secure boot method of claim 12, wherein the firmware execution data includes firmware code and independent variable data for each chip;

the master chip and each slave chip concurrently accessing the high-speed storage device includes:

all the chips divide the same first storage space in the high-speed storage device, wherein the first storage space is used for storing the firmware codes;

each chip is also divided into a second storage space corresponding to the chip in the high-speed storage device, and the second storage space is used for storing the independent variable data of the corresponding chip;

and mapping the first storage space address and a second storage space address corresponding to the chip into the same virtual address in each chip.

14. The secure boot method according to claim 10, wherein a cryptographic module is disposed in each chip, and key agreement is supported between the cryptographic modules in the at least two chips;

the secure boot method further comprises:

carrying out key agreement between the cryptographic modules in the at least two chips;

each chip encrypts a plaintext to be written into the high-speed storage device into a ciphertext through the cryptographic module in the chip and writes the ciphertext into the high-speed storage device;

each chip also reads and decrypts the ciphertext stored in the high-speed storage device through the cryptographic module in the chip.

15. The secure boot method of claim 14, wherein performing key agreement between the cryptographic modules in the at least two chips comprises: carrying out key agreement between the cryptographic modules in the at least two chips to generate a shared key;

the encrypting the plaintext to be written into the high-speed storage device into the ciphertext and then writing into the high-speed storage device comprises the following steps: encrypting the plaintext to be written into the high-speed storage device into ciphertext by using the shared secret key and writing the ciphertext into the high-speed storage device;

the reading and decrypting the ciphertext stored in the high-speed storage comprises: reading and decrypting the ciphertext stored in the high-speed storage using the shared key.

16. The secure boot method of claim 14, wherein said writing the plaintext to be written to the high-speed storage device after encrypting the plaintext to ciphertext further comprises:

the address information to be stored in the high-speed storage device is also encrypted as an address ciphertext.

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