CN115080473A - Multi-chip interconnection system and safe starting method based on same - Google Patents
Multi-chip interconnection system and safe starting method based on same Download PDFInfo
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Abstract
The invention provides a multi-chip interconnection system and a safe starting method based on the same. At least two chips are interconnected by a chip interconnect bus. The master chip is directly connected with the firmware storage device, and each slave chip is directly connected with the master chip or indirectly connected with the master chip through other slave chips. Also included is a high speed memory device accessed to the chip interconnect bus, with all chips sharing the high speed memory device. The firmware storage device stores the same firmware used by all chips, and the master chip loads the same firmware from the firmware storage device to the high-speed storage device, so that the master chip and each slave chip acquire the firmware execution data of the same firmware from the high-speed storage device. Under the multi-chip scene that the same firmware is used for a plurality of chips, the validity verification time is shortened, the validity verification efficiency is improved, and the safe starting time of the whole system can be effectively shortened.
Description
Technical Field
The invention relates to the technical field of chips, in particular to a multi-chip interconnection system and a safe starting method based on the same.
Background
The multi-chip is that a plurality of chips are interconnected and work cooperatively through a bus, and the external appearance is a complete system. As for the interconnection mode of the Multi-Chip structure In the processor field, it may be represented as a plurality of Single-Chip modules (SCM) interconnection, or may be represented as 1 or more homogeneous Multi-Chip modules (MCM) interconnection, or may be represented as 1 or more heterogeneous Multi-Chip packages (System In Package, SIP) interconnection. The multi-chip interconnect type may be in the form of a wire, a ring, a star, etc. The safe starting is a process for sequentially verifying the trusted firmware outside the chip through the trusted root built in the chip so as to realize the trusted starting of the system. Through safe starting, the tampered firmware can be effectively prevented from being executed on the chip, and therefore the credibility and the safety of the whole system are guaranteed. And the corresponding multi-chip safe starting realizes the safe starting process under the multi-chip structure.
In the safe starting process, one step is a process of loading basic firmware, the process is more critical in the safe starting process of multiple chips, and for scenes with more chips, the loading method of the basic firmware directly influences the starting time and the safety of the system. How to load the firmware for a plurality of chips quickly is a key problem of multi-chip safe starting. In the design of a motherboard and a multi-chip structure, it is common knowledge in the art to design a firmware storage device (usually Flash, Flash memory) on the motherboard only, in consideration of the cost and simplicity of the motherboard design. The connection between the multi-chip architecture and the firmware storage device can be summarized into two categories. One of the groups (abbreviated as scheme a) is: only one chip is connected with Flash, and the chip is used as a main chip and is responsible for receiving read-write requests of the slave chip and acting on data access of a firmware storage device of the slave chip. Another class (abbreviated as scheme b) is: each chip is connected with Flash, and each chip can access the firmware storage device to acquire data sequentially and independently. Since the firmware storage device usually uses a low-speed Serial Peripheral Interface (SPI) Interface (with a rate of 100 Mbps), and the inter-chip Link usually uses a high-speed Interface (with a rate of 10 Gbps), the firmware loading efficiency of the scheme a and the scheme b is equivalent to about the total time for reading all firmware data from the firmware storage device. For the scenario where multiple chips in a multi-chip structure use different firmware, the above schemes a and b are reasonable, as it is limited by the necessity to read all firmware data from the firmware storage device. For the scenario that multiple chips in the multi-chip structure use the same firmware, the scenario a and the scenario b may seriously affect the system startup time when the number of chips is large because the same firmware needs to be repeatedly read from the firmware storage device.
Disclosure of Invention
The invention provides a multi-chip interconnection system and a safe starting method based on the same, which can shorten the loading time of the same firmware, shorten the validity verification time, improve the validity verification efficiency and effectively shorten the safe starting time of the whole system under the multi-chip scene that a plurality of chips use the same firmware.
In a first aspect, the present invention provides a multichip interconnect system that includes a circuit board on which a firmware storage device and at least two chips are disposed. At least two chips are interconnected by a chip interconnection bus, and the at least two chips comprise a master chip and other slave chips. The main chip is directly connected with the firmware storage device, and each slave chip is directly connected with the main chip or indirectly connected with the main chip through other slave chips. The multichip interconnect system also includes a high speed memory device that is accessed to the chip interconnect bus, all chips sharing the high speed memory device. The same firmware used by all chips is stored in the firmware storage device, and the master chip is used for loading the same firmware from the firmware storage device to the high-speed storage device, so that the master chip and each slave chip can obtain the firmware execution data of the same firmware from the high-speed storage device. The main chip is also internally provided with a legality verifying module which is used for verifying the legality of the same firmware loaded in the high-speed storage device.
In the above solution, by providing a high-speed storage device accessing a chip interconnection bus, in a scenario where the same firmware used by all chips is stored in the firmware storage device, a master chip only needs to access the low-speed firmware storage device once to load the same firmware from the firmware storage device to the high-speed storage device, so that the master chip and other slave chips all use the chip interconnection bus to obtain firmware execution data of the same firmware from the high-speed storage device in a process of performing security verification or execution on the same firmware. And the main chip carries out validity verification on the same firmware after loading the same firmware to the high-speed storage device, so that an interaction process of validity verification also runs between the chip interconnection bus and the high-speed storage device in high-speed transmission, the validity verification time is shortened, and the validity verification efficiency is improved. Compared with the prior art that a plurality of chips repeatedly read the firmware executing data of the same firmware from the firmware storage device through the chip interconnection bus, the scheme of the application is optimized to read the firmware executing data of the same firmware from the high-speed storage device by using the chip interconnection bus, the reading speed of the data read from the firmware storage device is increased from 100Mbps magnitude to 10Gbps magnitude, and the time for reading the firmware executing data by each chip is greatly shortened by utilizing the advantage that the transmission speed between the chip and the shared high-speed storage device is more than 100 times of the access speed of the low-speed firmware storage device. Namely, under the multi-chip scene that the same firmware is used for a plurality of chips, the scheme of the application can effectively shorten the safe starting time of the whole system. Because a multi-chip structure in the field of processors, whether the structure is a homogeneous structure or a heterogeneous structure, a large number of identical chips exist in the whole system, and the identical chips are similar in initialization flow and generally use the same firmware. When the scheme is applied to the multi-chip structure in the field of processors, the loading time of the same firmware can be shortened, the validity verification time is shortened, the validity verification efficiency is improved, and the safe starting time of the whole system is greatly shortened.
In a specific embodiment, status registers for synchronous use are provided in at least two chips. After the master chip finishes verifying the validity of the same firmware loaded into the high-speed storage device, the master chip also changes the status register from the first state to the second state to broadcast a notification to all slave chips. After the master chip completes the validity verification, the information is broadcasted to all other slave chips in time, and the initialization processes of the same firmware by the multiple chips are similar, so that the other slave chips do not need to perform repeated validity verification on the same firmware, and the safe starting time is further shortened.
In a specific embodiment, the status register is a register integrated in the main chip, which facilitates the main chip to rapidly change the status of the status register.
In a specific embodiment, the high-speed storage device supports concurrent access of at least two chips, so that multiple chips can concurrently acquire firmware codes of the same firmware from the high-speed storage device, and therefore, as the number of slave chips increases, the overall system boot time of the technical scheme does not increase.
In a particular embodiment, the firmware execution data includes firmware code and independent variable data for each chip. The high-speed storage device is divided into a first storage space and at least two second storage spaces. The first storage space is used for storing firmware codes; the at least two second storage spaces correspond to the at least two chips one by one, and each second storage space is used for storing independent variable data of the corresponding chip. And the first storage space address and the second storage space address corresponding to the chip are mapped into the same virtual address in each chip. The method facilitates the concurrent normal execution of the same firmware code in a plurality of chips.
In a specific embodiment, each chip is provided with a cryptographic module, and key agreement is supported between the cryptographic modules in at least two chips. Each chip encrypts a plaintext to be written into the high-speed storage device into a ciphertext through a password module in the chip and writes the ciphertext into the high-speed storage device; each chip also reads and decrypts the ciphertext stored in the high-speed storage device through the cipher module in the chip. By adding the cryptographic module in each chip and supporting key negotiation among the cryptographic modules of a plurality of chips, the negotiated keys are correspondingly configured in the cryptographic modules, so that all the keys stored in the high-speed storage device are ciphertexts. Not only can an attacker not guess the key to decrypt the ciphertext in the high-speed storage device, but also can prevent the attacker from playing the ciphertext back to the high-speed storage device after tampering. And if an attacker directly tampers with the ciphertext, the decrypted content is usually not a correct instruction, so that the system is directly halted, and the attack of the attacker is prevented.
In a specific embodiment, a shared key is generated between cryptographic modules in at least two chips through key agreement; the shared secret key is used for each cryptographic module to encrypt plaintext into ciphertext or decrypt ciphertext into plaintext.
In one particular embodiment, the cryptographic module also encrypts address information to be stored in the high-speed storage device as an address ciphertext. The address of the data to be stored is also involved in the encryption calculation, so an attacker cannot attack by repeatedly placing the firmware ciphertext data.
In a specific embodiment, the high-speed storage device is arranged outside the chips of the at least two chips, so that the slave chips can select whether to access the high-speed storage device through the master chip, and each slave chip can conveniently access the high-speed storage device through an optimal access path. Or the high-speed storage device is arranged in the main chip, so that the main chip can conveniently load the same firmware from the firmware storage device to the high-speed storage device.
In a second aspect, the present invention further provides a secure booting method based on any of the above multichip interconnection systems, including: the main chip loads the same firmware stored in the firmware storage device to the high-speed storage device; the main chip verifies the validity of the same firmware loaded into the high-speed storage device; the master chip and each slave chip acquire firmware execution data of the same firmware from the high-speed storage device.
In the above solution, by providing a high-speed storage device accessing a chip interconnection bus, in a scenario where the same firmware used by all chips is stored in the firmware storage device, a master chip only needs to access the low-speed firmware storage device once to load the same firmware from the firmware storage device to the high-speed storage device, so that the master chip and other slave chips all use the chip interconnection bus to obtain firmware execution data of the same firmware from the high-speed storage device in a process of performing security verification or execution on the same firmware. The main chip carries out validity verification on the same firmware after loading the same firmware to the high-speed storage device, so that an interaction process of validity verification also runs between a chip interconnection bus and the high-speed storage device, validity verification time is shortened, and validity verification efficiency is improved. Compared with the prior art that a plurality of chips repeatedly read the firmware executing data of the same firmware from the firmware storage device through the chip interconnection bus, the scheme of the application is optimized to read the firmware executing data of the same firmware from the high-speed storage device by using the chip interconnection bus, the reading speed of the data read from the firmware storage device is increased from 100Mbps magnitude to 10Gbps magnitude, and the time for reading the firmware executing data by each chip is greatly shortened by utilizing the advantage that the transmission speed between the chip and the shared high-speed storage device is more than 100 times of the access speed of the low-speed firmware storage device. Namely, under the multi-chip scene that the same firmware is used for a plurality of chips, the scheme of the application can effectively shorten the safe starting time of the whole system. Because a multi-chip structure in the field of processors, whether the structure is a homogeneous structure or a heterogeneous structure, a large number of identical chips exist in the whole system, and the identical chips are similar in initialization flow and generally use the same firmware. When the scheme is applied to the multi-chip structure in the field of processors, the loading time of the same firmware can be shortened, the validity verification time is shortened, the validity verification efficiency is improved, and the safe starting time of the whole system is greatly shortened.
In a specific embodiment, status registers for synchronous use are provided in at least two chips. After the master chip finishes verifying the validity of the same firmware loaded into the high-speed storage device, the secure boot method further comprises: the master chip changes the status register from the first state to the second state to broadcast a notification to all slave chips. After the master chip completes the validity verification, the information is broadcasted to all other slave chips in time, and the initialization processes of the same firmware by the multiple chips are similar, so that the other slave chips do not need to perform repeated validity verification on the same firmware, and the safe starting time is further shortened.
In a specific embodiment, the main chip and each of the slave chips obtaining the firmware execution data of the same firmware from the high-speed storage device comprises: the main chip and each slave chip access the high-speed storage device concurrently to acquire the firmware execution data of the same firmware, so that the plurality of chips can acquire the firmware code of the same firmware from the high-speed storage device concurrently, and therefore, with the increase of the number of the slave chips, the whole system starting time of the technical scheme is not increased accordingly.
In a particular embodiment, the firmware execution data includes firmware code and independent variable data for each chip. The master chip and each slave chip concurrently accessing the high speed storage device includes: all chips are divided into the same first storage space in the high-speed storage device, and the first storage space is used for storing firmware codes; each chip is also divided into a second storage space corresponding to the chip in the high-speed storage device, and the second storage space is used for storing independent variable data of the corresponding chip; and mapping the first storage space address and the second storage space address corresponding to the chip into the same virtual address in each chip. The method facilitates the concurrent normal execution of the same firmware code in a plurality of chips.
In a specific embodiment, each chip is provided with a cryptographic module, and key agreement is supported between the cryptographic modules in at least two chips. The secure boot method further comprises: carrying out key agreement between the cryptographic modules in at least two chips; each chip encrypts a plaintext to be written into the high-speed storage device into a ciphertext through a password module in the chip and writes the ciphertext into the high-speed storage device; each chip also reads and decrypts the ciphertext stored in the high-speed storage device through the cipher module in the chip. By adding the cryptographic module in each chip and supporting key negotiation among the cryptographic modules of a plurality of chips, the negotiated keys are correspondingly configured in the cryptographic modules, so that all the keys stored in the high-speed storage device are ciphertexts. Not only can an attacker not guess the key to decrypt the ciphertext in the high-speed storage device, but also can prevent the attacker from playing the ciphertext back to the high-speed storage device after tampering. And if an attacker directly tampers with the ciphertext, the decrypted content is usually not a correct instruction, so that the system is directly halted, and the attack of the attacker is prevented.
In a specific embodiment, the key agreement between the cryptographic modules in the at least two chips comprises: and carrying out key agreement between the cryptographic modules in at least two chips to generate a shared key. The writing of the encrypted plaintext into the high-speed storage device comprises: the plaintext to be written into the high-speed storage device is encrypted into ciphertext by using the shared key and then written into the high-speed storage device. Reading and decrypting a ciphertext stored in a high-speed storage device comprises: the shared key is read and used to decrypt the ciphertext stored in the high-speed storage device.
In a specific embodiment, the writing of the encrypted plaintext to the high-speed storage device into the ciphertext further comprises: the address information to be stored in the high-speed storage device is also encrypted as an address ciphertext. The address of the data to be stored is also involved in the encryption calculation, so an attacker cannot attack by repeatedly placing the firmware ciphertext data.
Drawings
Fig. 1 is a schematic block diagram of a multichip interconnection system according to an embodiment of the invention;
FIG. 2 is a schematic block diagram of another multichip interconnect system provided by an embodiment of the invention;
FIG. 3 is a schematic block diagram of the multi-chip interconnect system workflow shown in FIG. 2;
FIG. 4 is a flowchart illustrating operation of the multichip interconnect system shown in FIG. 2;
fig. 5 is a schematic block diagram of a work flow of another multichip interconnection system according to an embodiment of the invention.
Reference numerals:
10-firmware storage device 20-master chip 21-slave chip
201-cipher module 202-control module 30-high speed storage device
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
To facilitate understanding of the multichip interconnection system provided by the embodiment of the invention, an application scenario of the multichip interconnection system provided by the embodiment of the invention is first described below, and the multichip interconnection system is applied to a system formed by interconnecting a plurality of chips. The multichip interconnect system is described in detail below with reference to the accompanying drawings.
Referring to fig. 1, a multichip interconnection system according to an embodiment of the invention includes a circuit board (not shown) on which a firmware storage device 10 and at least two chips are disposed. At least two chips are interconnected by a chip interconnection bus (the thicker line width of the chip interconnection bus in fig. 1-3 and 5 indicates the chip interconnection bus), and at least two chips comprise a master chip 20 and other slave chips 21. The master chip 20 is directly connected to the firmware storage device 10, and each slave chip 21 is directly connected to the master chip 20 or indirectly connected to the master chip 20 through another slave chip 21. The multichip interconnect system also includes a high speed memory device 30 that accesses the chip interconnect bus, with all chips sharing the high speed memory device 30. The same firmware used by all chips is stored in the firmware storage device 10, and the master chip 20 is used for loading the same firmware from the firmware storage device 10 to the high-speed storage device 30, so that the master chip 20 and each slave chip 21 obtain firmware execution data of the same firmware from the high-speed storage device 30. A validity verifying module for verifying the validity of the same firmware loaded into the high-speed storage device 30 is provided in the main chip 20.
In the above solution, by providing the high-speed storage device 30 accessing the chip interconnection bus, in a scenario where the same firmware used by all chips is stored in the firmware storage device 10, the main chip 20 only needs to access the low-speed firmware storage device 10 once to load the same firmware from the firmware storage device 10 to the high-speed storage device 30, so that the main chip 20 and the other slave chips 21 all use the chip interconnection bus to obtain the firmware execution data of the same firmware from the high-speed storage device 30 in the process of performing security verification or execution on the same firmware. And the main chip 20 carries out validity verification on the same firmware after loading the same firmware into the high-speed storage device 30, so that an interaction process of validity verification also runs between the chip interconnection bus of high-speed transmission and the high-speed storage device 30, the validity verification time is shortened, and the validity verification efficiency is improved. Compared with the prior art that a plurality of chips repeatedly read the firmware executing data of the same firmware from the firmware storage device 10 through the chip interconnection bus, the scheme of the application is optimized to read the firmware executing data of the same firmware from the high-speed storage device 30 by using the chip interconnection bus, the reading rate of reading the data from the firmware storage device 10 is increased from 100Mbps magnitude to 10Gbps magnitude, and the time for reading the firmware executing data by each chip is greatly shortened by utilizing the advantage that the transmission rate between the chip and the shared high-speed storage device 30 is more than 100 times of the access rate of the low-speed firmware storage device 10. Namely, under the multi-chip scene that the same firmware is used for a plurality of chips, the scheme of the application can effectively shorten the safe starting time of the whole system. Because a multi-chip structure in the field of processors, whether the structure is a homogeneous structure or a heterogeneous structure, a large number of identical chips exist in the whole system, and the identical chips are similar in initialization flow and generally use the same firmware. When the scheme is applied to the multi-chip structure in the field of processors, the loading time of the same firmware can be shortened, the validity verification time is shortened, the validity verification efficiency is improved, and the safe starting time of the whole system is greatly shortened. The above-described respective structures will be described in detail with reference to the accompanying drawings.
When the circuit board is arranged, the circuit board can be a mainboard in a server, and can also be a circuit board formed by wiring and via holes in other scenes. The circuit board is a carrying and interconnecting structure for arranging the firmware storage device 10 and the chip, and can be realized by adopting a printed circuit board.
Referring to fig. 1, a firmware storage device 10 is disposed on a circuit board, and the firmware storage device 10 serves as a storage medium to store off-chip firmware of each chip, so that when the chip is started, each chip loads corresponding firmware from the firmware storage device 10 to implement a corresponding function. In a specific setting, the firmware storage device 10 may employ a memory such as, but not limited to, a Flash memory (Flash). The firmware storage device 10 typically employs an SPI interface with a transmission rate on the order of 100 Mbps. In the present application, the firmware storage device 10 stores the same firmware used by all the chips, that is, each of at least two chips needs to load the same firmware in the starting process to implement the corresponding function.
Referring to fig. 1, at least two chips are further disposed on the circuit board, and the at least two chips are interconnected through a chip interconnection bus. Each chip in the package may be a single chip package (SCM), a homogeneous multi-chip package (MCM), or one chip in the homogeneous multi-chip package. Even more, each chip may be a heterogeneous multi-chip package (SIP) or one chip of a heterogeneous multi-chip package. That is, each chip in the present application may specifically be a package formed by packaging a single and multiple homogeneous or heterogeneous chips, and may also be one chip in a package formed by packaging multiple homogeneous or heterogeneous chips. The present application does not limit whether a chip is a package or a die within a package, but rather defines the manner in which multiple chips are connected by a chip interconnect bus. The chip interconnection bus may particularly be a chip interconnection bus formed within a package to interconnect different dies within the same package; it is also possible to provide a chip interconnect bus formed on a package substrate or circuit board outside the package to connect different packages or chips within different packages. The data transmission rate of the chip interconnection bus is much greater than the data transmission rate between the chip and other devices outside the at least two chip systems. Specifically, the data transmission rate of the chip interconnection bus can be set to be more than 10Gbps magnitude, that is, the chip interconnection bus interface used between chips is a high-speed interface.
With continued reference to fig. 1, the at least two chips include a main chip 20, and the main chip 20 is directly connected to the firmware storage device 10, and may specifically be directly connected to the firmware storage device 10 through an SPI bus. The data transfer rate of the bus directly connected between the firmware storage device 10 and the main chip 20 is lower than that of the chip interconnection bus. As shown in fig. 1, the chips of the at least two chips except the master chip 20 are all used as slave chips 21, and are directly connected with the master chip 20 through a chip interconnection bus, or are indirectly connected with the master chip 20 through the chip interconnection bus and other slave chips 21. Note that, even if the slave chip 21 is indirectly connected to the master chip 20 through the chip interconnection bus and the other slave chips 21, the data transfer rate between the slave chip 21 and the master chip 20 is much greater than the data transfer rate between the master chip 20 and the firmware storage device 10. When the interconnection between the slave chip 21 and the master chip 20 is realized, at least two chips may be interconnected by using an interconnection manner such as, but not limited to, a line type, a ring type, a star type, and the like. At least two chips shown in fig. 1 are interconnected by a chip interconnection bus line type, that is, at least two chips are connected by a chip interconnection bus in a line type topology. It should be noted that the manner of interconnecting at least two chips is not limited to the line type of interconnection shown in fig. 1, and other interconnection manners may be adopted.
Referring to fig. 1, the multichip interconnect system further includes a high-speed memory device 30, and the high-speed memory device 30 is connected to the chip interconnect bus, so that the high-speed memory device 30 has a globally independent address. And all of the at least two chips share the high speed memory device 30 so that each chip can access the high speed memory device 30. The high speed memory device 30 has high speed data access capability, thereby enabling each chip to access the high speed memory device 30 at a higher data transfer rate when accessing the chip interconnect bus. In a specific arrangement, a Random Access Memory (RAM) such as, but not limited to, a Cache Memory (Cache) may be used as the high-speed storage device 30, so that each chip can Access the high-speed storage device 30 at a high-speed data transfer rate through a chip interconnection bus.
Referring to fig. 1, the high speed memory device 30 may be disposed off-chip of at least two chips, i.e., not within each chip, so that the slave chip 21 may select whether to access the high speed memory device 30 through the master chip 20, facilitating each slave chip 21 to access the high speed memory device 30 with an optimal access path. Of course, referring to fig. 5, the high speed storage device 30 may also be disposed within the main chip 20, so that the main chip 20 can load the same firmware from the firmware storage device 10 into the high speed storage device 30. It should be understood that the present application does not limit the location of the high speed memory device 30, but primarily limits the access of the high speed memory device 30 to the chip interconnect bus, enables multiple chips to share the high speed memory device 30, and enables access to the high speed memory device 30 at a high speed number transfer rate.
In the secure boot process, referring to fig. 1 and 4, the master chip 20 can load the same firmware from the firmware storage 10 to the high-speed storage 30, specifically, the master chip 20 loads the same firmware stored in the firmware storage 10 and writes the same firmware into the high-speed storage 30, so that the master chip 20 and each slave chip 21 obtain firmware execution data of the same firmware from the high-speed storage 30 to perform an execution operation such as verification, loading, and the like. By providing the high-speed storage device 30 connected to the chip interconnection bus, in a scenario where the same firmware used by all chips is stored in the firmware storage device 10, the main chip 20 only needs to access the low-speed firmware storage device 10 once to load the same firmware from the firmware storage device 10 to the high-speed storage device 30, so that the main chip 20 and the other slave chips 21 all use the chip interconnection bus to obtain the firmware execution data of the same firmware from the high-speed storage device 30 in a process of performing security verification or execution on the same firmware. Compared with the prior art that a plurality of chips repeatedly read the firmware executing data of the same firmware from the firmware storage device 10 through the chip interconnection bus, the scheme of the application is optimized to read the firmware executing data of the same firmware from the high-speed storage device 30 by using the chip interconnection bus, the reading rate of reading the data from the firmware storage device 10 is increased from 100Mbps magnitude to 10Gbps magnitude, and the time for reading the firmware executing data by each chip is greatly shortened by utilizing the advantage that the transmission rate between the chip and the shared high-speed storage device 30 is more than 100 times of the access rate of the low-speed firmware storage device 10. Namely, under the multi-chip scene that the same firmware is used for a plurality of chips, the scheme of the application can effectively shorten the safe starting time of the whole system. Because a multi-chip structure in the field of processors, whether the structure is a homogeneous structure or a heterogeneous structure, a large number of identical chips exist in the whole system, and the identical chips are similar in initialization flow and generally use the same firmware. When the scheme is applied to a multi-chip structure in the field of processors, the safe starting time of the whole system can be greatly shortened.
In addition, the main chip 20 may also perform validity verification on the same firmware by interacting with the same firmware in the high-speed storage device 30 after loading the same firmware from the firmware storage device 10 into the high-speed storage device 30. Specifically, a validity verifying module may be provided in the main chip 20, and when the same firmware is loaded into the high-speed storage device 30, the validity verifying module is used to verify the validity of the same firmware loaded into the high-speed storage device 30. The main chip 20 performs validity verification on the same firmware after loading the same firmware into the high-speed storage device 30, so that an interaction process of validity verification also runs between the chip interconnection bus and the high-speed storage device 30 in high-speed transmission, validity verification time is shortened, and validity verification efficiency is improved. It should be understood that the main chip 20 is not limited to implementations in which the validity verification is performed by interacting with the same firmware loaded into the high-speed storage device 30, but other approaches may be used. For example, the main chip 20 may interact with the same firmware in the firmware storage 10 to verify the validity thereof, that is, the main chip 20 verifies the validity of the same firmware before loading the same firmware in the firmware storage 10, and loads the same firmware into the high-speed storage 30 only after the validity verification passes.
Further, at least two chips may be provided with a status register for synchronous use, and whether the master chip 20 completes validity verification on the same firmware is identified by a status change of the status register, so as to notify other slave chips 21 to determine whether to perform validity verification on the same firmware again according to requirements. Specifically, after the master chip 20 completes the verification of the validity of the same firmware loaded into the high-speed storage device 30, the master chip 20 needs to change the status register from the first state to the second state, where the first state may be binary "0", and the second state may be binary "1", and of course, the opposite definition may also be adopted to broadcast all the slave chips 21, and the master chip 20 completes the validity verification of the same firmware. After the master chip 20 completes the validity verification, the information is timely broadcast to all the other slave chips 21, and since the initialization processes of the same firmware by the multiple chips are similar, the other slave chips 21 do not need to perform repeated validity verification on the same firmware, thereby further shortening the safe starting time. When the status register is specifically selected, the master chip 20 may negotiate with each of the other slave chips 21 to use one register in the master chip 20 as the status register, so that the master chip 20 can change the status of the status register quickly. Of course, the status register may also be located in a register of any slave chip 21.
When the main chip 20 and the slave chip 21 share and access the high-speed storage device 30, the high-speed storage device 30 can support concurrent access of at least two chips by adjusting software and hardware, so that a plurality of chips can concurrently acquire firmware codes of the same firmware from the high-speed storage device 30, and therefore, with the increase of the number of the slave chips 21, the whole system starting time of the technical scheme is not increased. Taking fig. 3 and fig. 4 as an example, for the main chip 20, the time of the whole firmware loading process of the same firmware is: the main chip 20 loads the same firmware from the firmware storage 10 to the shared high speed storage 30 through the path 1 → 2 → 3. For each of the other following master chips 20 and the slave chips 21, the following master chip 20 passes through the path 2 → 3, the slave chip 1 (slave chip 1 of the slave chips 1, 2, 3 …, n in fig. 3 and 4) passes through the path 4 → 5, and the slave chip 2 (slave chip 2 of the slave chips 1, 2, 3 …, n in fig. 3 and 4) passes through the path 6 → 7, and concurrently, from the shared high-speed storage 30, to acquire the corresponding firmware execution data. When the master chip 20 and the slave chip 21 access the firmware execution data of the same firmware in the high-speed storage device 30, the firmware execution data may include firmware codes and independent variable data for each chip. Therefore, when concurrent access is realized, the same firmware code of the same firmware needs to be accessed by multiple chips concurrently. When the master chip 20 and the slave chip 21 are implemented to concurrently share and access the high-speed storage device 30, various implementations may be adopted. One implementation is shown illustratively as follows.
The high-speed storage device 30 may be divided into a first storage space and at least two second storage spaces. The first storage space is used for storing a copy of firmware codes of the same firmware. The at least two second storage spaces correspond to the at least two chips one by one, and each second storage space is used for storing independent variable data of the corresponding chip. At this time, software inside each chip including the master chip 20 and the slave chip 21 needs to be adjusted, so that the first memory space address and the second memory space address corresponding to the chip are mapped to the same virtual address inside each chip, which is convenient for the concurrent normal execution of the same firmware code in multiple chips. It should be understood that the above only illustrates one implementation that supports multiple chips concurrently accessing the high speed storage device 30, and that other implementations may be employed.
Furthermore, functional blocks for securing security may be additionally provided, and when the firmware executes data transfer between the high-speed storage device 30 and the chip, the security of the data transfer may be secured by these functional blocks. Specifically, referring to fig. 2, fig. 3 and fig. 5, a cryptographic module 201 may be disposed in each chip, and key agreement is supported between the cryptographic modules 201 in at least two chips, so that a symmetric key can be shared between all chips. Then, each chip encrypts the plaintext to be written into the high-speed storage device 30 into ciphertext through the cryptographic module 201 therein, and writes the ciphertext into the high-speed storage device 30. Each chip also reads and decrypts the ciphertext stored in the high-speed storage device 30 through the cryptographic module 201 therein. That is, when each chip writes the same firmware, such as but not limited to the same firmware, into the high-speed storage device 30, it needs to encrypt plaintext into ciphertext before writing into the high-speed storage device 30. Specifically, referring to fig. 2, 3 and 5, a control module 202 is further disposed in each chip and connected to the cryptographic module 201 to control corresponding operations. As shown in fig. 2, after loading the same firmware from the firmware storage device 10, the control module 202 of the main chip 20 first passes the cipher module 201 in the main chip 20 to encrypt the same firmware into a cipher text, and then writes the cipher text into the high-speed storage device 30. After the main chip 20 or each slave chip 21 loads the firmware code such as but not limited to the same firmware or the independent variable data for each chip from the high-speed storage device 30, it needs to be decrypted by the cryptographic module 201 before being handed to the control module 202 in each chip for corresponding operation. By adding the cryptographic module 201 in each chip and supporting key negotiation among the cryptographic modules 201 of a plurality of chips, the negotiated keys are correspondingly configured in the cryptographic modules 201, so that all the keys stored in the high-speed storage device 30 are ciphertexts. Not only can an attacker not guess the key to decrypt the ciphertext in the high-speed storage device 30, but also the attacker is prevented from tampering and then encrypting and returning the ciphertext to the high-speed storage device 30. And if an attacker directly tampers with the ciphertext, the decrypted content is usually not a correct instruction, so that the system is directly halted, and the attack of the attacker is prevented. In a more preferred embodiment, the cryptographic module 201 may encrypt the address information to be stored in the high-speed storage device 30 as the address ciphertext, that is, encrypt the address information of the data to be stored in the high-speed storage device 30, and make the address to be stored participate in the encryption calculation, so that an attacker cannot attack by repeatedly placing the firmware ciphertext data.
When the cryptographic modules 201 in the at least two chips perform key agreement, the cryptographic modules 201 in the at least two chips may generate a shared key through the key agreement, where the shared key is used for each cryptographic module 201 to encrypt a plaintext into a ciphertext or decrypt the ciphertext into the plaintext.
In the above-described scheme, by providing the high-speed storage device 30 accessing the chip interconnection bus, in a scenario where the same firmware used by all chips is stored in the firmware storage device 10, the main chip 20 only needs to access the low-speed firmware storage device 10 once to load the same firmware from the firmware storage device 10 to the high-speed storage device 30, so that the main chip 20 and the other slave chips 21 all use the chip interconnection bus to obtain the firmware execution data of the same firmware from the high-speed storage device 30 in the process of performing security verification or execution on the same firmware. And the main chip 20 carries out validity verification on the same firmware after loading the same firmware into the high-speed storage device 30, so that an interaction process of validity verification also runs between the chip interconnection bus of high-speed transmission and the high-speed storage device 30, the validity verification time is shortened, and the validity verification efficiency is improved. Compared with the prior art that a plurality of chips repeatedly read the firmware executing data of the same firmware from the firmware storage device 10 through the chip interconnection bus, the scheme of the application is optimized to read the firmware executing data of the same firmware from the high-speed storage device 30 by using the chip interconnection bus, the reading rate of reading the data from the firmware storage device 10 is increased from 100Mbps magnitude to 10Gbps magnitude, and the time for reading the firmware executing data by each chip is greatly shortened by utilizing the advantage that the transmission rate between the chip and the shared high-speed storage device 30 is more than 100 times of the access rate of the low-speed firmware storage device 10. Namely, under the multi-chip scene that the same firmware is used for a plurality of chips, the scheme of the application can effectively shorten the safe starting time of the whole system. Because a multi-chip structure in the field of processors, whether the structure is a homogeneous structure or a heterogeneous structure, a large number of identical chips exist in the whole system, and the identical chips are similar in initialization flow and generally use the same firmware. When the scheme is applied to the multi-chip structure in the field of processors, the loading time of the same firmware can be shortened, the validity verification time is shortened, the validity verification efficiency is improved, and the safe starting time of the whole system is greatly shortened.
In addition, an embodiment of the present invention further provides a secure boot method based on any of the above multichip interconnection systems, and referring to fig. 1, the secure boot method includes: the main chip 20 loads the same firmware stored in the firmware storage 10 to the high-speed storage 30; the main chip 20 verifies the validity of the same firmware loaded into the high-speed storage device 30; the master chip 20 and each slave chip 21 acquire firmware execution data of the same firmware from the high-speed storage device 30.
In the above solution, by providing the high-speed storage device 30 accessing the chip interconnection bus, in a scenario where the same firmware used by all chips is stored in the firmware storage device 10, the main chip 20 only needs to access the low-speed firmware storage device 10 once to load the same firmware from the firmware storage device 10 to the high-speed storage device 30, so that the main chip 20 and the other slave chips 21 all use the chip interconnection bus to obtain the firmware execution data of the same firmware from the high-speed storage device 30 in the process of performing security verification or execution on the same firmware. And the main chip 20 carries out validity verification on the same firmware after loading the same firmware into the high-speed storage device 30, so that an interaction process of validity verification also runs between the chip interconnection bus of high-speed transmission and the high-speed storage device 30, the validity verification time is shortened, and the validity verification efficiency is improved. Compared with the prior art that a plurality of chips repeatedly read the firmware executing data of the same firmware from the firmware storage device 10 through the chip interconnection bus, the scheme of the application is optimized to read the firmware executing data of the same firmware from the high-speed storage device 30 by using the chip interconnection bus, the reading rate of reading the data from the firmware storage device 10 is increased from 100Mbps magnitude to 10Gbps magnitude, and the time for reading the firmware executing data by each chip is greatly shortened by utilizing the advantage that the transmission rate between the chip and the shared high-speed storage device 30 is more than 100 times of the access rate of the low-speed firmware storage device 10. Namely, under the multi-chip scene that the same firmware is used for a plurality of chips, the scheme of the application can effectively shorten the safe starting time of the whole system. Because a multi-chip structure in the field of processors, whether the structure is a homogeneous structure or a heterogeneous structure, a large number of identical chips exist in the whole system, and the identical chips are similar in initialization flow and generally use the same firmware. When the scheme is applied to the multi-chip structure in the field of processors, the loading time of the same firmware can be shortened, the validity verification time is shortened, the validity verification efficiency is improved, and the safe starting time of the whole system is greatly shortened. The above steps will be described in detail with reference to the accompanying drawings.
First, the main chip 20 loads the same firmware stored in the firmware storage 10 to the high-speed storage 30. For a specific implementation, reference is made to the foregoing description of the multichip interconnection system, and details are not repeated herein.
Further, referring to fig. 4, after the main chip 20 loads the same firmware stored in the firmware storage 10 to the high-speed storage 30, the main chip 20 verifies the validity of the same firmware loaded in the high-speed storage 30. For a specific implementation, reference is made to the foregoing description of the multichip interconnection system, and details are not repeated herein.
As described above with respect to the multichip interconnect system portion, status registers for synchronous use may also be provided in at least two chips. The specific way of using the status register may be: after the master chip 20 finishes verifying the validity of the same firmware loaded into the high-speed storage device 30, the master chip 20 also changes the status register from the first state to the second state to broadcast all the slave chips 21. After the master chip 20 completes the validity verification, the information is timely broadcast to all the other slave chips 21, and since the initialization processes of the same firmware by the multiple chips are similar, the other slave chips 21 do not need to perform repeated validity verification on the same firmware, thereby further shortening the safe starting time.
Next, referring to fig. 3 and 4, the master chip 20 and each slave chip 21 acquire firmware execution data of the same firmware from the high-speed storage device 30.
As described above with respect to the multi-chip interconnection system, when the master chip 20 and each slave chip 21 both obtain the firmware execution data of the same firmware from the high-speed storage device 30, the master chip 20 and each slave chip 21 can concurrently access the high-speed storage device 30 to obtain the firmware execution data of the same firmware, so that multiple chips can concurrently obtain the firmware code of the same firmware from the high-speed storage device 30, and therefore, as the number of slave chips 21 increases, the overall system boot time of the present technical solution does not increase. When the master chip 20 and the slave chip 21 access the firmware execution data of the same firmware in the high-speed storage device 30, the firmware execution data may include firmware codes and independent variable data for each chip. Therefore, when concurrent access is realized, the same firmware code of the same firmware needs to be accessed by multiple chips concurrently. When the master chip 20 and the slave chip 21 are implemented to concurrently share and access the high-speed storage device 30, various implementations may be adopted. One implementation is shown illustratively as follows.
When the master chip 20 and each slave chip 21 are implemented to access the high-speed storage device 30 concurrently, all the chips divide the same first storage space in the high-speed storage device 30, and the first storage space is used for storing firmware codes; each chip is further divided into a second storage space corresponding to the chip in the high-speed storage device 30, and the second storage space is used for storing independent variable data of the corresponding chip; and mapping the first storage space address and the second storage space address corresponding to the chip into the same virtual address in each chip. The method facilitates the concurrent normal execution of the same firmware code in a plurality of chips. For a specific implementation, reference is made to the foregoing description of the multichip interconnection system, and details are not repeated herein.
In addition, referring to fig. 2, fig. 3 and fig. 5, each chip may further be provided with a cryptographic module 201, and the cryptographic modules 201 in at least two chips support key agreement. At this time, the secure boot method may further include: the cryptographic modules 201 in at least two chips perform key agreement; each chip encrypts a plaintext to be written into the high-speed storage device 30 into a ciphertext through a cipher module 201 in the chip and writes the ciphertext into the high-speed storage device 30; each chip also reads and decrypts the ciphertext stored in the high-speed storage device 30 through the cryptographic module 201 therein. By adding the cryptographic module 201 in each chip and supporting key negotiation among the cryptographic modules 201 of a plurality of chips, the negotiated keys are correspondingly configured in the cryptographic modules 201, so that all the keys stored in the high-speed storage device 30 are ciphertexts. Not only can an attacker not guess the key to decrypt the ciphertext in the high-speed storage device 30, but also the attacker is prevented from tampering and then encrypting and returning the ciphertext to the high-speed storage device 30. And if an attacker directly tampers with the ciphertext, the decrypted content is usually not a correct instruction, so that the system is directly halted, and the attack of the attacker is prevented. For a specific implementation, reference is made to the foregoing description of the multichip interconnection system, and details are not repeated herein.
When the cryptographic modules 201 in at least two chips perform key agreement, the cryptographic modules 201 in at least two chips may perform key agreement to generate a shared key. At this time, encrypting the plaintext to be written into the high-speed storage device 30 into the ciphertext and writing into the high-speed storage device 30 includes: plaintext to be written into the high-speed storage device 30 is encrypted into ciphertext using the shared key and then written into the high-speed storage device 30. At this time, reading and decrypting the ciphertext stored in the high-speed storage device 30 includes: the ciphertext stored in the high speed storage device 30 is read and decrypted using the shared key.
Further, when the plaintext to be written into the high-speed storage device 30 is encrypted into the ciphertext and then written into the high-speed storage device 30, the address information to be stored in the high-speed storage device 30 may also be encrypted into the address ciphertext, so that the address of the data to be stored is also involved in the encryption calculation, and therefore an attacker cannot attack by repeatedly placing the firmware ciphertext data.
The above description is only for the specific embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (16)
1. A multichip interconnect system, comprising:
a circuit board;
a firmware storage device disposed on the circuit board;
at least two chips arranged on the circuit board and interconnected through a chip interconnection bus, wherein the at least two chips comprise a master chip and other slave chips; the main chip is directly connected with the firmware storage device, and each slave chip is directly connected with the main chip or indirectly connected with the main chip through other slave chips;
a high speed storage device accessing the chip interconnect bus and shared by all of the chips;
the firmware storage device stores the same firmware used by all the chips;
the main chip is used for loading the same firmware from the firmware storage device to the high-speed storage device so that the main chip and each slave chip can acquire firmware execution data of the same firmware from the high-speed storage device;
and a validity verification module is also arranged in the main chip and used for verifying the validity of the same firmware loaded in the high-speed storage device.
2. The multichip interconnect system according to claim 1, wherein status registers for synchronous use are provided in said at least two chips;
after the master chip finishes verifying the validity of the same firmware loaded into the high-speed storage device, the master chip also changes the status register from the first state to the second state to broadcast a notification to all slave chips.
3. The multichip interconnect system of claim 2, wherein the status register is a register integrated within the master chip.
4. The multichip interconnect system of claim 1, wherein the high speed memory device supports concurrent access by the at least two chips.
5. The multichip interconnect system according to claim 4, wherein the firmware execution data includes firmware code and independent variable data for each chip;
the high-speed storage device is divided into a first storage space and at least two second storage spaces; wherein the first storage space is used for storing the firmware codes; the at least two second storage spaces correspond to the at least two chips one by one, and each second storage space is used for storing the independent variable data of the corresponding chip;
and mapping the first storage space address and a second storage space address corresponding to the chip into the same virtual address in each chip.
6. The multichip interconnect system according to claim 1, wherein a cryptographic module is disposed in each chip, and key agreement is supported between cryptographic modules in said at least two chips;
each chip encrypts a plaintext to be written into the high-speed storage device into a ciphertext through the cryptographic module in the chip and writes the ciphertext into the high-speed storage device; each chip also reads and decrypts the ciphertext stored in the high-speed storage device through the cryptographic module in the chip.
7. The multichip interconnect system according to claim 6, wherein a shared key is generated between the cryptographic modules in the at least two chips through key agreement;
the shared secret key is used for each cryptographic module to encrypt the plaintext into the ciphertext or decrypt the ciphertext into the plaintext.
8. The multichip interconnect system of claim 6, wherein the cryptographic module further encrypts the address information that the ciphertext is to be stored in the high-speed storage device as an address ciphertext.
9. The multichip interconnect system according to claim 1, wherein said high speed storage device is disposed off-chip of said at least two chips; or the like, or, alternatively,
the high-speed storage device is disposed within the main chip.
10. A secure boot method of the multichip interconnect system according to claim 1, comprising:
the main chip loads the same firmware stored in the firmware storage device to the high-speed storage device;
the main chip verifies the validity of the same firmware loaded into the high-speed storage device;
the master chip and each slave chip acquire firmware execution data of the same firmware from the high-speed storage device.
11. The secure boot method according to claim 10, wherein a status register for synchronous use is provided in the at least two chips;
after the master chip finishes verifying the validity of the same firmware loaded into the high-speed storage device, the secure boot method further comprises: the master chip changes the status register from a first state to a second state to broadcast a notification to all slave chips.
12. The secure boot method of claim 10, wherein the master chip and each slave chip obtaining firmware execution data of the same firmware from the high-speed storage device comprises:
the master chip and each slave chip concurrently access the high-speed storage device to obtain firmware execution data of the same firmware.
13. The secure boot method of claim 12, wherein the firmware execution data includes firmware code and independent variable data for each chip;
the master chip and each slave chip concurrently accessing the high-speed storage device includes:
all the chips divide the same first storage space in the high-speed storage device, wherein the first storage space is used for storing the firmware codes;
each chip is also divided into a second storage space corresponding to the chip in the high-speed storage device, and the second storage space is used for storing the independent variable data of the corresponding chip;
and mapping the first storage space address and a second storage space address corresponding to the chip into the same virtual address in each chip.
14. The secure boot method according to claim 10, wherein a cryptographic module is disposed in each chip, and key agreement is supported between the cryptographic modules in the at least two chips;
the secure boot method further comprises:
carrying out key agreement between the cryptographic modules in the at least two chips;
each chip encrypts a plaintext to be written into the high-speed storage device into a ciphertext through the cryptographic module in the chip and writes the ciphertext into the high-speed storage device;
each chip also reads and decrypts the ciphertext stored in the high-speed storage device through the cryptographic module in the chip.
15. The secure boot method of claim 14, wherein performing key agreement between the cryptographic modules in the at least two chips comprises: carrying out key agreement between the cryptographic modules in the at least two chips to generate a shared key;
the encrypting the plaintext to be written into the high-speed storage device into the ciphertext and then writing into the high-speed storage device comprises the following steps: encrypting the plaintext to be written into the high-speed storage device into ciphertext by using the shared secret key and writing the ciphertext into the high-speed storage device;
the reading and decrypting the ciphertext stored in the high-speed storage comprises: reading and decrypting the ciphertext stored in the high-speed storage using the shared key.
16. The secure boot method of claim 14, wherein said writing the plaintext to be written to the high-speed storage device after encrypting the plaintext to ciphertext further comprises:
the address information to be stored in the high-speed storage device is also encrypted as an address ciphertext.
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