CN201629762U - Multi-node network circuit based on RS485 bus mode - Google Patents
Multi-node network circuit based on RS485 bus mode Download PDFInfo
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- CN201629762U CN201629762U CN2009202059606U CN200920205960U CN201629762U CN 201629762 U CN201629762 U CN 201629762U CN 2009202059606 U CN2009202059606 U CN 2009202059606U CN 200920205960 U CN200920205960 U CN 200920205960U CN 201629762 U CN201629762 U CN 201629762U
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Abstract
The utility model discloses a multi-node network circuit based on an RS485 bus mode, which comprises a main node and at least two buses connected with a plurality of slave nodes, and is characterized by further comprising a controller for transmitting/receiving data, a signal selective module and an RS485 bus driving chip. A polling control program is internally arranged on the main node; the signal selective module controlled by the controller connects the main node and different buses; and the RS485 bus driving chip arranged between the bus and the signal selective module enables the bus to change data with the controller while in signal gating. Compared with the prior art, the number of nodes on the bus is increased and can reach 400 at most without reduction of transmission speed, and the multi-node network circuit is more widely and conveniently used.
Description
Technical field
The utility model relates to signal circuit, relates in particular to a kind of multinode network circuit based on the RS485 bus mode.
Background technology
In safety protection field, the center monitoring field, industrial control field, field of medical, numerous inductors, controller are arranged in the middle of the intelligent building field, monitor, card reader will be carried out data communication by serial port, the RS485 bus is because its wiring is simple, thus reliable and stable being used widely.RS485 adopts a twisted-pair cable to make bus, and each node is connected in series.RS485 adopts half-duplex operation, the general bus type structure that adopts the terminal coupling of bus network topology.In RS485 route bus process,, make RS485 bus maximum can support 32 nodes, make to promote the use to be subjected to very big restriction because a lot of reasons is arranged.
The utility model content
The utility model is that will to solve existing RS485 bus node quantity few, promotes the use the problem that is restricted, and proposes a kind of multinode network circuit based on the RS485 bus mode.
For solving the problems of the technologies described above, the technical scheme that the utility model proposes is: a kind of multinode network circuit based on the RS485 bus mode, comprise host node and at least two buses that are connected with some from node, it is characterized in that also comprising: the controller that is positioned at the transmission/reception data of the built-in poll control program on the host node, the signal gating module that is controlled by the controller and connects host node and different bus in turn is located at the RS485 bus driver chip that makes bus and controller swap data when gating between described bus and the signal gating module.
In preferred embodiment, establish the buffer of polling timer and temporary bus ephemeral data in the controller.Bus adopts the bus type structure of terminal coupling, and it comprises the some twisted-pair cables from node of serial connection; Described RS485 bus driver chip is located at the end of bus.
Compared with prior art, the number of nodes on the utility model bus increases, and transmission speed can not reduce, and it is more extensively convenient to use.
Description of drawings
Below in conjunction with drawings and Examples the utility model is made detailed explanation, wherein:
Fig. 1 is the utility model example theory diagram.
Embodiment
Fig. 1 shows the utility model example theory diagram, as can be seen from the figure the utility model comprises: host node and at least two buses that are connected with some from node, be positioned at the controller of the transmission/reception data of the built-in poll control program on the host node, the signal gating module that is controlled by the controller and connects host node and different bus in turn is located at the RS485 bus driver chip that makes bus and controller swap data when gating between described bus and the signal gating module.Described bus adopts the bus type structure of terminal coupling, and it comprises the some twisted-pair cables from node of serial connection; Described RS485 bus driver chip is located at the end of bus.
Essence of the present utility model is to increase RS485 bus driver chip, and all chip for driving are connected to the UART pin of controller by tristate bus line chip or separating component, and the normal pins of utilizing controller is controlled different RS485 bus driver chip access controllers, controller is connected with data/address bus, and with hang on the bus from the node switching data.Do not need to increase the quantity of the module of UART like this, and, do not need to utilize the control timing of normal pins simulation UART, reduced the workload of software.Because the transfer rate of RS485 bus is unhappy, so adopt the mode of this timesharing can not have influence on the transfer rate of bus.Make this mode can not form the speed bottleneck at this.
For illustrating the utility model course of work, two RS485 bus driver chips only are shown in the example theory diagram of Fig. 1.The one RS485 bus driver chip connects first bus (not drawing among the figure), and the 2nd RS485 bus driver chip connects second bus (not drawing among the figure).At first controller sends control signal and makes signal gating module gating the one RS485 bus driver chip, even TX_DATA is connected with TX_DATA_1, RX_DATA is connected with RX_DATA_1, this moment, controller received the data on first bus that a RS485 bus driver chip driven, and the 2nd RS485 bus driver chip is in idle condition.After the exchanges data of a controller and a RS485 bus driver chip is finished, controller changes controller signals gating the 2nd RS485 bus driver chip, even TX_DATA is connected with TX_DATA_2, RX_DATA is connected with RX_DATA_2, this moment, controller received the data on the 2nd RS485 bus driver chip, and a RS485 bus driver chip is in idle condition.After the exchanges data of controller and the 2nd RS485 bus driver chip was finished, controller changes controller signals made signal gating module gating the one RS485 bus driver chip, circulates with this, made continuous and two bus exchanging datas of controller.Expect easily, the signal gating module with RS485 bus driver chip and more than two covers of bus that are connected with chip for driving, have multiple bus to be connected with controller in this way among other embodiment.The utility model can be supported 400 nodes at most.
In preferred embodiment, establish the buffer of polling timer and temporary bus ephemeral data in the controller.When the data volume of bus switch is bigger, maybe to limit each poll time, can adopt the control mode of timesharing to make controller and bus exchanging data.If it is T that each RS485 bus driver chip takies the time of controller, arrive T after the time when the swap time of controller and bus 1, polling timer sends the time to signal, controller is kept in this bus ephemeral data, change gating signal simultaneously, controller is connected with next bar bus, and controller is by accessing the ephemeral data relevant with next bar bus in the buffer, and beginning and next bar bus exchanging data.So constantly circulation, controller just can be carried out the big data quantity exchange with all buses.
Better embodiment of the present utility model has more than been described, but the those of skill in the art in the present technique field are to be understood that, these only illustrate, and can make numerous variations or modification to these execution modes, and not deviate from principle of the present utility model and essence.The scope that all belongs to the utility model protection.
Claims (3)
1. multinode network circuit based on the RS485 bus mode, comprise host node and at least two buses that are connected with some from node, it is characterized in that also comprising: the controller that is positioned at the transmission/reception data of the built-in poll control program on the host node, the signal gating module that is controlled by the controller and connects host node and different bus in turn is located at the RS485 bus driver chip that makes bus and controller swap data when gating between described bus and the signal gating module.
2. multinode network circuit as claimed in claim 1 is characterized in that: the buffer of establishing polling timer and temporary bus ephemeral data in the described controller.
3. multinode network circuit as claimed in claim 2 is characterized in that: described bus adopts the bus type structure of terminal coupling, and it comprises the some twisted-pair cables from node of serial connection; Described RS485 bus driver chip is located at the end of bus.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009202059606U CN201629762U (en) | 2009-10-16 | 2009-10-16 | Multi-node network circuit based on RS485 bus mode |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009202059606U CN201629762U (en) | 2009-10-16 | 2009-10-16 | Multi-node network circuit based on RS485 bus mode |
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| CN201629762U true CN201629762U (en) | 2010-11-10 |
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| CN2009202059606U Expired - Fee Related CN201629762U (en) | 2009-10-16 | 2009-10-16 | Multi-node network circuit based on RS485 bus mode |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102841554A (en) * | 2011-06-24 | 2012-12-26 | 镇江华扬信息科技有限公司 | Intelligent remote control method for system |
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2009
- 2009-10-16 CN CN2009202059606U patent/CN201629762U/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102841554A (en) * | 2011-06-24 | 2012-12-26 | 镇江华扬信息科技有限公司 | Intelligent remote control method for system |
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| Date | Code | Title | Description |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20101110 Termination date: 20121016 |