CN201628959U

CN201628959U - Super-speed interface SOC control chip oriented to mobile FLASH memories

Info

Publication number: CN201628959U
Application number: CN2010200154469U
Authority: CN
Inventors: 刘昭麟; 任奇伟; 李宏志; 鄢俊兵; 戴绍新
Original assignee: Xian Sinochip Semiconductors Co Ltd; Shandong Sinochip Semiconductors Co Ltd
Current assignee: Xian Sinochip Semiconductors Co Ltd; Shandong Sinochip Semiconductors Co Ltd
Priority date: 2010-01-21
Filing date: 2010-01-21
Publication date: 2010-11-10
Anticipated expiration: 2020-01-21

Abstract

The utility model provides a super-speed interface SOC control chip oriented to mobile FLASH memories, which comprises a chip body, a USB 3.0 physical layer, a USB 3.0 equipment controller, a system encryption module, a FLASH storage controller, a 32-bit RISC processor, a ROM, a RAM, a memory controller, a memory, a real-time clock, and a RESET and a power supply management unit. The modules are all integrated onto on one chip body; a USB3.0 super-speed interface consists of the USB 3.0 physical layer and the USB 3.0 equipment controller; and the USB 3.0 super-speed interface is communicated with other module units through data wires and connected with the 32-bit RISC processor to be arranged on the chip body to form an SOC system on chip. Compared with the prior art, the super-speed interface SOC control chip has the advantages of high data transmission speed, high reliability of embedded system, low consumption of the embedded system, data safety encryption and the like, thereby achieving fine popularized and practical values.

Description

A kind of hypervelocity interface SOC control chip towards the mobile FLASH storer

Technical field

The utility model relates to microelectronics technology, can be used for towards the control and management of mobile Flash storer, specifically provides the SOC chip of the multiple IP kernel of a kind of integrated USB3.0 of comprising interface, Flash Memory Controller, system encryption module.

Background technology

Under the trend at present increasing, that price is but more and more lower, will become mainstream storage device in the personal hand-held terminal device based on the mobile storage of Flash storage chip at Flash storage medium single-chip capacity.On the one hand, along with the increase of storage capacity requirement, the deal with data amount is increasing, and is more and more higher to the requirement that data rate, storage control and management, data security are encrypted, the performance requirement that reliable and secure synchronous instantaneous transmission has necessitated.Such specification demand has had higher level requirement to the Flash storage control chip of the performance of decision Flash storer.

The utility model content

The purpose of this utility model is the growth requirement at above-mentioned mobile Flash storer, and a kind of SOC control chip towards mobile Flash storer of integrated multiple IP kernel is provided.

The Flash storage control chip is the core component of Flash storage, and (SOC (system on a chip), SOC) direction develops to single-chip by the multicore sheet through in a few years development Flash storage control chip.

A kind of hypervelocity interface SOC control chip of the present utility model towards mobile Flash storer, its structure is made up of chip body, USB3.0 Physical layer, USB3.0 device controller, system encryption module, Flash memory controller, 32 risc processors, ROM, RAM, Memory Controller Hub, internal memory, real-time clock, Reset and Power Management Unit, and above-mentioned module all integrates.

USB3.0 hypervelocity interface adds that by the USB3.0 Physical layer USB3.0 device controller forms, and USB3.0 hypervelocity interface, system encryption module, Flash memory controller, ROM, RAM, Memory Controller Hub, internal memory, real-time clock, Reset and Power Management Unit all link together to be arranged on by data line and 32 risc processors and form the SOC SOC (system on a chip) on the chip body.

The demand that a kind of hypervelocity interface SOC control chip towards mobile Flash storer of the present utility model is primarily aimed at mobile Flash storer is customized.Have following useful effect compared with prior art:

(1) adopt 65nm design and manufacturing process, power consumption is very low;

(2) combining of USB3.0 hypervelocity interface and Flash memory controller can effectively be brought into play the characteristic of Flash storage fast reading and writing, and optimizes power management, reduces system power dissipation;

(3) single interface protocol realization data are transmitted fast, reduce system complexity, improve system reliability;

(4) the integrated a large amount of IP of SOC have reduced peripheral chip, reduce the embedded system cost;

(5) can carry out the level of security setting to the storage data, significant data is carried out physical isolation.

Has the advantage that simple in structure, high data rate, low system power dissipation, high reliability and data security are encrypted.

Description of drawings

Fig. 1 is the system on chip structure synoptic diagram of hypervelocity interface SOC control chip.

Description of reference numerals:

Chip body 1, USB3.0 Physical layer 2, USB3.0 device controller 3, system encryption module 4, Flash memory controller 5,32 risc processors 6, ROM 7, RAM 8, Memory Controller Hub 9, internal memory 10, real-time clock 11, Reset and Power Management Unit 12.

Embodiment

Below in conjunction with the drawings and specific embodiments the utility model is further specified.But not as qualification of the present utility model.

A kind of hypervelocity interface SOC control chip towards mobile Flash storer is made of chip body 1, USB3.0 Physical layer 2, USB3.0 device controller 3, system encryption module 4, Flash memory controller 5,32 risc processors 6, ROM 7, RAM 8, Memory Controller Hub 9, internal memory 10, real-time clock 11, Reset and Power Management Unit 12.

USB3.0 Physical layer 2, USB3.0 device controller 3, system encryption module 4, Flash memory controller 5,32 risc processors 6, ROM 7, RAM 8, Memory Controller Hub 9, internal memory 10, real-time clock 11, Reset and Power Management Unit 12 are all on chip body 1.USB3.0 hypervelocity interface (USB3.0 Physical layer 2 adds USB3.0 device controller 3), system encryption module 4, Flash memory controller 5, ROM 7, RAM8, Memory Controller Hub 9, internal memory 10, real-time clock 11, Reset and Power Management Unit 12 all are connected with 32 risc processors 6 by system bus.

USB3.0 Physical layer 2 adds that USB3.0 device controller 3 has constituted complete USB3.0 hypervelocity interface, they are the high-speed data on the External cable (mxm. is 5Gbps), the DMA that carries by USB3.0 device controller 3 arrives system encryption module 4 to data transfer, behind hardware encipher, pass to purpose source Flash memory controller 5 again; 32 risc processors 6 play the effect of microprocessor here, be used for the guiding and the allotment sheet on resource.The boot and the configuration parameter of 32 risc processors 6 have been solidified 7 li of ROM.RAM 8 provides the space for program implementation; 10 pairs of internal memory 9 and Memory Controller Hub pass to Flash memory controller 5 data and play buffer memory; And real-time clock 11 is one group of PLL, and its effect is the clock of the required different frequency of generation system; Reset and Power Management Unit 12 produce the required reset signal in unit on the sheet according to the input of outside.Hypervelocity USB3.0 interface (USB3.0 Physical layer 2 adds USB3.0 device controller 3) has the data rate that mxm. is 5Gbps, has remarkable energy management, and can and optimize at the protocol efficiency of low energy consumption and Geng Gao, can give full play to the excellent reading of Flash storer; Encrypting module 4 can carry out the level of security setting to the storage data, and significant data is carried out physical isolation, improves the information security degree; Flash memory controller 5 realization data are reliably managed correcting data error and data abrasion equilibration technology.

The above embodiment is more preferably embodiment a kind of of the utility model, and the common variation that those skilled in the art carry out in the technical solutions of the utility model scope and replacing all should be included in the protection domain of the present utility model.

Claims

1. hypervelocity interface SOC control chip towards the mobile FLASH storer, it is characterized in that this chip is made up of chip body, USB3.0 Physical layer, USB3.0 device controller, system encryption module, Flash memory controller, 32 risc processors, ROM, RAM, Memory Controller Hub, internal memory, real-time clock, Reset and Power Management Unit;

Wherein, chip body, USB3.0 Physical layer, USB3.0 device controller, system encryption module, Flash memory controller, 32 risc processors, ROM, RAM, Memory Controller Hub, internal memory, real-time clock, Reset and Power Management Unit all integrate;

The USB3.0 Physical layer adds USB3.0 device controller composition USB3.0 hypervelocity interface, and USB3.0 hypervelocity interface, system encryption module, Flash memory controller, ROM, RAM, Memory Controller Hub, internal memory, real-time clock, Reset and Power Management Unit link together to be arranged on by data line and 32 risc processors and form the SOC SOC (system on a chip) on the chip body.