CN201623129U - Normal chip packaging structure with exposed substrate and heat sink having locking hole and connected with external radiator - Google Patents

Normal chip packaging structure with exposed substrate and heat sink having locking hole and connected with external radiator Download PDF

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Publication number
CN201623129U
CN201623129U CN 201020123227 CN201020123227U CN201623129U CN 201623129 U CN201623129 U CN 201623129U CN 201020123227 CN201020123227 CN 201020123227 CN 201020123227 U CN201020123227 U CN 201020123227U CN 201623129 U CN201623129 U CN 201623129U
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CN
China
Prior art keywords
chip
radiator
metal substrate
heat sink
heat
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN 201020123227
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Chinese (zh)
Inventor
王新潮
梁志忠
高盼盼
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
JCET Group Co Ltd
Original Assignee
Jiangsu Changjiang Electronics Technology Co Ltd
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Filing date
Publication date
Application filed by Jiangsu Changjiang Electronics Technology Co Ltd filed Critical Jiangsu Changjiang Electronics Technology Co Ltd
Priority to CN 201020123227 priority Critical patent/CN201623129U/en
Application granted granted Critical
Publication of CN201623129U publication Critical patent/CN201623129U/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73215—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors

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  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

The utility model relates to a normal chip packaging structure with an exposed substrate and a heat sink having a locking hole and connected with an external radiator. The normal chip packaging structure comprises a chip (3), a metal substrate (1), meal inner pins (4), metal wires (5), a conductive or non-conductive heat-transfer adhesive material I (2) and a plastic package (8), wherein the metal substrate (1) is exposed from the plastic package (8), the heat sink (7) with the locking hole (7.1) is disposed above the chip (3), a conductive or non-conductive heat-transfer adhesive material II (6) is embedded between the heat sink (7) and the chip (3), and the radiator (11) is disposed above the heat sink (7) and fixedly connected with the heat sink (7) through the locking hole (7.1) with a screw (12). The normal chip packaging structure can provide powerful heat dissipation capacity so as to quickly conduct heat of the chip to the outside of the package, thereby avoiding quick aging of the chip, and even burn or burnout.

Description

Base island exposed chip formal dress lock hole heat dissipation block externally connected with radiator encapsulating structure
(1) technical field
The utility model relates to a kind of base island exposed chip formal dress lock hole heat dissipation block externally connected with radiator encapsulating structure.Belong to the semiconductor packaging field.
(2) background technology
The radiating mode of traditional Chip Packaging form mainly be to have adopted the Metal Substrate island of chip below as heat radiation conduction instrument or approach, and there is following not enough point in the heat radiation of this conventional package mode conduction:
1, Metal Substrate island volume is too little
The Metal Substrate island is in the conventional package form, in order to pursue the reliability safety of packaging body, nearly all adopted the Metal Substrate island to be embedded in the packaging body, and in limited packaging body, to imbed the interior pin (as shown in Figures 1 and 2) of metal of Metal Substrate island and signal, power supply conduction usefulness simultaneously, very the little so effective area on Metal Substrate island and volume just seem, and the function of the heat radiation of high heat also will be served as in the Metal Substrate island simultaneously, will seem deficiency more.
2, baried type Metal Substrate island (as shown in Figures 1 and 2)
The Metal Substrate island is in the conventional package form, in order to pursue the reliability safety of packaging body, nearly all adopted the Metal Substrate island to be embedded in the packaging body, and the Metal Substrate island is about dependence or four fine support bars in corner fix or support metal Ji Dao, also because the characteristic of this fine support bar, the heat that has caused the Metal Substrate island to be absorbed from the chip, can't conduct out from fine support bar fast, so the heat of chip can't or be transmitted to the packaging body external world fast, caused the life-span quick aging of chip even burn or burnt out.
3, Metal Substrate island exposed type (as shown in Figures 3 and 4)
Though expose on the Metal Substrate island, can provide also will good heat-sinking capability than the heat sinking function of baried type, because the volume on Metal Substrate island and area still very little in packaging body, so heat dissipation capability can be provided, still very limited.
(3) summary of the invention
The purpose of this utility model is to overcome above-mentioned deficiency, and providing a kind of can provide heat dissipation capability strong base island exposed chip formal dress lock hole heat dissipation block externally connected with radiator encapsulating structure.
The purpose of this utility model is achieved in that a kind of base island exposed chip formal dress lock hole heat dissipation block externally connected with radiator encapsulating structure, include chip, the Metal Substrate island of being carried of chip below, pin in the metal, chip is to the wire of the signal interconnection of the interior pin of metal, conduction between chip and the Metal Substrate island or nonconducting heat conduction bonding material I and plastic-sealed body, the base island exposed plastic packaging material of described metal, it is characterized in that above described chip, being provided with radiating block, this radiating block has lock hole, is equipped with conduction or nonconducting heat conduction bonding material II between this radiating block and the described chip; Be provided with radiator above described radiating block, described radiator is fixedlyed connected with radiating block by described lock hole with screw.
The beneficial effects of the utility model are:
The utility model passes through addition radiating block above chip, and sets up radiator outside plastic-sealed body, serves as the function of the heat radiation of high heat, can provide heat dissipation capability strong, makes the heat of chip can be transmitted to the packaging body external world fast.Can be applied in and make it become height or superelevation heat radiation (High Thermal or Super High Thermal) ability on the packaging body of general packing forms and the packaging technology, can become SHT-FBP/QFN as FBP can become SHT-QFN/BGA and can become SHT-BGA/CSP and can become SHT-CSP ...Avoided the life-span quick aging of chip even burn or burnt out.
(4) description of drawings
Fig. 1 is Metal Substrate island baried type chip-packaging structure schematic diagram in the past.
Fig. 2 is the vertical view of Fig. 1.
Fig. 3 is Metal Substrate island exposed type chip-packaging structure schematic diagram in the past.
Fig. 4 is the vertical view of Fig. 3.
Fig. 5 is the utility model base island exposed chip formal dress lock hole heat dissipation block externally connected with radiator encapsulating structure schematic diagram.
Reference numeral among the figure:
Pin 4, wire 5, conduction or nonconducting heat conduction bonding material II6, radiating block 7, lock hole 7.1, plastic-sealed body 8, radiator 11, screw 12 in Metal Substrate island 1, conduction or nonconducting heat conduction bonding material I2, chip 3, the metal.
(5) embodiment
Referring to Fig. 5, Fig. 5 is the utility model base island exposed chip formal dress lock hole heat dissipation block externally connected with radiator encapsulating structure schematic diagram.As seen from Figure 5, the utility model base island exposed chip formal dress lock hole heat dissipation block externally connected with radiator encapsulating structure, include chip 3, the Metal Substrate island 1 of being carried of chip below, pin 4 in the metal, chip is to the wire 5 of the signal interconnection of the interior pin of metal, conduction between chip and the Metal Substrate island or nonconducting heat conduction bonding material I 2 and plastic-sealed body 8, plastic packaging material 8 is exposed on described Metal Substrate island 1, above described chip 3, be provided with radiating block 7, this radiating block 7 has lock hole 7.1, is equipped with conduction or nonconducting heat conduction bonding material II6 between this radiating block 7 and the described chip 3; Be provided with radiator 11 above described radiating block 7, described radiator 11 usefulness screws 12 are fixedlyed connected with radiating block 7 by described lock hole 7.1.
The material of described radiating block 7 can be copper, aluminium, pottery or alloy etc.
The material of described radiator 11 can be copper, aluminium, pottery or alloy etc.

Claims (3)

1. base island exposed chip formal dress lock hole heat dissipation block externally connected with radiator encapsulating structure, include chip (3), the Metal Substrate island (1) of being carried of chip below, pin (4) in the metal, chip is to the wire (5) of the signal interconnection of the interior pin of metal, conduction between chip and the Metal Substrate island or nonconducting heat conduction bonding material I (2) and plastic-sealed body (8), plastic packaging material (8) is exposed on described Metal Substrate island (1), it is characterized in that being provided with radiating block (7) in described chip (3) top, this radiating block (7) has lock hole (7.1), is equipped with conduction or nonconducting heat conduction bonding material II (6) between this radiating block (7) and the described chip (3); Be provided with radiator (11) in described radiating block (7) top, described radiator (11) is fixedlyed connected with radiating block (7) by described lock hole (7.1) with screw (12).
2. a kind of base island exposed chip formal dress lock hole heat dissipation block externally connected with radiator encapsulating structure according to claim 1, the material that it is characterized in that described radiating block (7) is copper, aluminium, pottery or alloy.
3. a kind of base island exposed chip formal dress lock hole heat dissipation block externally connected with radiator encapsulating structure according to claim 1, the material that it is characterized in that described radiator (11) is copper, aluminium, pottery or alloy.
CN 201020123227 2010-01-29 2010-01-29 Normal chip packaging structure with exposed substrate and heat sink having locking hole and connected with external radiator Expired - Fee Related CN201623129U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN 201020123227 CN201623129U (en) 2010-01-29 2010-01-29 Normal chip packaging structure with exposed substrate and heat sink having locking hole and connected with external radiator

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN 201020123227 CN201623129U (en) 2010-01-29 2010-01-29 Normal chip packaging structure with exposed substrate and heat sink having locking hole and connected with external radiator

Publications (1)

Publication Number Publication Date
CN201623129U true CN201623129U (en) 2010-11-03

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Family Applications (1)

Application Number Title Priority Date Filing Date
CN 201020123227 Expired - Fee Related CN201623129U (en) 2010-01-29 2010-01-29 Normal chip packaging structure with exposed substrate and heat sink having locking hole and connected with external radiator

Country Status (1)

Country Link
CN (1) CN201623129U (en)

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C14 Grant of patent or utility model
GR01 Patent grant
C17 Cessation of patent right
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20101103

Termination date: 20140129