CN201616094U - Host device with multiple connectors and protocol selection device - Google Patents
Host device with multiple connectors and protocol selection device Download PDFInfo
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- CN201616094U CN201616094U CN201020116611XU CN201020116611U CN201616094U CN 201616094 U CN201616094 U CN 201616094U CN 201020116611X U CN201020116611X U CN 201020116611XU CN 201020116611 U CN201020116611 U CN 201020116611U CN 201616094 U CN201616094 U CN 201616094U
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Abstract
The utility model relates to a host device with multiple connectors and a protocol selection device. The host device comprises multiple connectors, a CPU, a storage unit, an internal memory, a display controller, a power supply control unit, a port detection unit and a port selection unit, wherein the power supply control unit supplies power to each module of the storage unit, the port detection unit is connected with the multiple connectors respectively, sends velocity measurement data packets to the multiple connectors, detects transmission velocity of the multiple connectors according to velocity measurement data which is fed back and then selects one specified connector according to the velocity measurement result, the port selection unit selects the specified connector to be communicated with a peripheral device, and the host device selects the specified connector to be served as a connector for a data channel connected between the peripheral device and the storage unit. The connector with fastest transmission velocity is selected according to time for receiving and transmitting velocity measurement data packets, thereby effectively utilizing each interface and increasing data transmission velocity of the host device.
Description
Technical field
The utility model relates to a kind of host apparatus and agreement selecting arrangement, relates in particular to a kind of host apparatus with multiple different agreement connector, with the agreement selecting arrangement of selecting a kind of connector from the connector of different agreements.
Background technology
Under the prior art, the USB2.0 connector with plug-and-play feature is very universal on various digital equipments.Along with the increase of digital product memory capacity, the data rate of USB2.0 connector can not satisfy people's needs gradually.
In order to solve the bottleneck of USB2.0 connector data transmission, the connector of USB3.0 has appearred, and the ESATA connector that uses the SATA agreement.The USB3.0 standard can be supported the message transmission rate up to 4.8Gbps, and data rate surpasses 10 times of USB2.0.And the ESATA standard can reach the speed of 3Gbs even 6Gbs, also considerably beyond the message transmission rate of USB2.0 connector.
Use from product, have the two-in-one connector of USB2.0 and USB3.0, USB 2.0 and the two-in-one connector of ESATA, and USB2.0, USB3.0, the three-in-one company's machine of ESATA, various products also begin to occur.
On memory storage and host apparatus, use three-in-one connector, the perhaps connector of agreement more than three kinds, how do memory storage and host apparatus select only connector from the connector more than three kinds? it is problem demanding prompt solution.
Therefore, prior art has difficulties, and needs further improvement and develops.
The utility model content
The purpose of this utility model is to provide a kind of host apparatus and agreement selecting arrangement with multiple connector, when making host apparatus pass through multiple connector to be connected with same external device, can select only connector to carry out data transmission.
The technical solution of the utility model is as follows:
A kind of host apparatus with multiple connector comprises multiple connector, CPU, storage unit, internal memory and display controller, and is the power control unit of each module for power supply of memory storage, wherein,
Also comprise the port detecting unit, be connected with described multiple connector respectively; Send the measurement data bag to multiple connector respectively, detect the transmission speed of each connector, utilize the result that tests the speed to select to specify connector according to the measurement data bag that returns;
The port selected cell selects described appointment connector and external device to be communicated with;
Described host apparatus selects to specify the connector of connector as data channel between external device and the storage unit.
Described host apparatus, wherein, described appointment connector is the slowest connector or the most stable connector of transmission speed of transmission speed the fastest connector, transmission speed.
Described host apparatus, wherein, described port detecting unit comprises the speed measuring module by the transmission speed of each connector of time detecting of transmitting-receiving measurement data bag.
Described host apparatus, wherein, described speed measuring module comprises: computation subunit, calculate transmission speed by the measurement data bag of the connector that tests the speed; Relatively subelement compares the speed that each connector transmits data.
Described host apparatus, wherein, described port detecting unit connectivity port switch unit, described port switch unit is connected on the described storage unit by second microprocessor, the different host-host protocol of the described second microprocessor control transformation; Described internal memory and display controller are connected to first microprocessor, and described second microprocessor is connected on the CPU by described first microprocessor.
Described host apparatus, wherein, described port detecting unit connectivity port switch unit, described port switch unit is connected on the described storage unit by second microprocessor, the different host-host protocol of the described second microprocessor control transformation; Described internal memory, display controller and second microprocessor are connected on the described CPU.
Described host apparatus, wherein, described port detecting unit connects described port switch unit, and described port switch unit connects described CPU, and described internal memory and display controller are connected on the described CPU.
Described host apparatus, wherein, described first microprocessor is a north bridge chips, second microprocessor is a South Bridge chip.
Described host apparatus, wherein, described speed measuring module, port detecting unit, second microprocessor or CPU comprise the transmission submodule and receive submodule.
Described host apparatus, wherein, described speed measuring module is arranged among storage unit, second microprocessor or the CPU of host apparatus.
Described host apparatus, wherein, described speed measuring module, port detecting unit, microprocessor or CPU comprise the judgement submodule of selecting connector.
Described host apparatus, wherein, described multiple connector comprises USB2.0 interface, USB3.0 interface and ESATA interface, infrared interface, 1394 interfaces, blue tooth interface, WIFI interface.
Described host apparatus, wherein, described USB2.0 interface, USB3.0 interface and ESATA interface are three-in-one plug or socket.
Described host apparatus, wherein, described USB3.0 interface or ESATA are communicated with power supply for the selected the fastest data-interface of transmission data, the power supply terminal in the described USB2.0 interface, as the power end of described USB3.0 interface or ESATA interface.
A kind of agreement selecting arrangement comprises: the measurement data bag that returns to multiple connector transmission measurement data bag basis detects the port detecting unit of the transmission speed of each connector respectively,
Described port detecting unit comprises computation subunit, calculates the transmission speed by the measurement data bag of connector; Subelement relatively, relatively the speed of each connector transmission data result that tests the speed selects to specify connector port;
Described protocol conversion apparatus also comprises the interface that is connected with multiple connector, and the interface that is connected with South Bridge chip or CPU.
Described agreement selecting arrangement, wherein, described port detecting unit also comprises the judgement submodule of selecting connector.
Prior art is compared, host apparatus that the utility model provides and agreement selecting arrangement with multiple connector, port detecting unit by host apparatus sends the measurement data bag by each connector to external device, selection of time by transmitting-receiving measurement data bag goes out to specify the connector interface of memory storage and external device transmission data the most, effectively utilize each connector, improve the speed of memory storage transmission data.
Description of drawings
Fig. 1 is the functional block diagram of first embodiment of the utility model memory storage;
Fig. 2 is the functional block diagram of second embodiment of the utility model memory storage;
Fig. 3 is the functional block diagram of the 3rd embodiment of the utility model memory storage;
Fig. 4 is the functional block diagram of the 4th embodiment of the utility model memory storage;
Fig. 5 is the functional block diagram of the 5th embodiment of the utility model memory storage;
Fig. 6 is the functional block diagram of first embodiment that the utlity model has the host apparatus of a plurality of connectors;
Fig. 7 is the functional block diagram of second embodiment that the utlity model has the host apparatus of a plurality of connectors;
Fig. 8 is the functional block diagram of the 3rd embodiment that the utlity model has the host apparatus of a plurality of connectors;
Fig. 9 is the functional block diagram of the 4th embodiment that the utlity model has the host apparatus of a plurality of connectors;
Figure 10 selects the process flow diagram of first embodiment of connector for the utility model memory storage;
Figure 11 selects the process flow diagram of connector second embodiment for the utility model memory storage;
Figure 12 selects the process flow diagram of connector the 3rd embodiment for the utility model memory storage;
Figure 13 the utility model host apparatus is selected the process flow diagram of connector method.
Embodiment
Below in conjunction with accompanying drawing, preferred embodiment of the present utility model is described in further detail.
The connector that comprises various host-host protocols such as USB2.0 interface 111, USB3.0 interface 112 and ESATA interface 113, infrared interface, 1394 interfaces, blue tooth interface, WIFI interface on the memory storage that the utility model provides with multiple connector.Described USB2.0 interface 111, USB3.0 interface 112 and 113 3 interfaces of ESATA interface can be arranged on same plug or the socket, can also be that described USB2.0 interface 111 and USB3.0 interface 112 are arranged on same plug or the socket, can also be that described USB2.0 interface 111 and ESATA interface 113 interfaces are arranged on same plug or the socket, concrete set-up mode limit.Multiple interfaces is arranged on same plug or the socket, the memory storage that the utlity model has this interface is carrying out data transmission with external device, can select the fastest interface of data rate to carry out data transmission automatically, or the transmission speed of each connector presented, manually, rationally utilize the connector of the various protocols that has on the memory storage, so that the data transmission efficiency of memory storage to be provided.
First embodiment of the utility model memory storage, be memory storage 100 as shown in Figure 1, described memory storage 100 comprises USB2.0 interface 111, USB3.0 interface 112 and ESATA interface 113, described three kinds of interfaces are connected on the port detecting unit 121 of described memory storage, the port detecting unit 121 of described memory storage detects connected connector and whether realizes physical connection in external device, the step of the going forward side by side speed measuring module that is stored in memory storage second storage unit 140, send packet to external device, measure the speed of three connectors transmission data according to the time of transceive data bag, select to specify the excuse of connector as described memory storage 100 and external device data channel.Described appointment connector can be the fastest connector of transmission speed, or the slowest connector of transmission speed, or the most stable connector of transmission speed, as long as the result can learn according to testing the speed, here do not limit, the utility model serves as to specify connector to select the fastest connector of transmission speed.
Described port detecting unit 121 can obtain the fastest of which connector transmission data according to the time of transmitting-receiving measurement data bag, and the information of the connector that the transmission data speed is the fastest sends to port selected cell 122.Described port selected cell 122 will transmit the pairing data channel of the fastest connector of data speed and connect, and agreement selected cell 123 is the fastest pairing host-host protocol of connector of transmission data speed with the transport protocol conversion of data channel.The storage unit 130 of described memory storage 100 is connected with described agreement selected cell 123, described storage unit 130 also comprises the control module 131 that the read-write of control store unit is handled, and described storage unit 130 can be hard disk, FLASH or FLASH array, SSD etc.Described memory storage also comprises power control unit 150, is used to each module for power supply of memory storage, and the connecting line of described power control unit 150 power supplies all is not shown among the figure.Described second memory module 140 can be the FLASH that is connected with the port detecting unit.
The protocol conversion that agreement selected cell 123 described in the utility model also is responsible for described storage unit 130 is used is the host-host protocol of each data channel, for example when described storage unit 130 was connected with described agreement selected cell 123 usefulness SATA data lines, described agreement selected cell 123 can carry out data between described agreement selected cell 123 and the described storage unit 130 conversion between disk read-write form and the SATA agreement.This is that prior art repeats no more.
The utlity model has second embodiment of the memory storage of a plurality of connectors, it is memory storage 200, as shown in Figure 2, with the difference of described memory storage 100, the port detecting unit 121 of described memory storage 200, port selected cell 122 and agreement selected cell 123 are arranged in the microprocessor 120 of memory storage 200.Which realizes physical connection in port detecting unit 121 its a plurality of connectors of detecting of described microprocessor 120, if it is a plurality of to realize that the connector of physical connection has, just further detects described a plurality of connectors and whether connects same external device.If the connector that described port detecting unit 121 detects described a plurality of realization physical connections connects same external device, described microprocessor 120 sends instruction, makes described port detecting unit 121 send the measurement data bag by the connector of realizing physical connection to external device respectively.After described port detecting unit 121 receives the measurement data bag that described external device returns, the data rate of measuring that connector by the time of transmitting-receiving measurement data bag is the fastest, and the information of the connector that this data rate is the fastest sends to described port selected cell 122.The information of the connector that described port selected cell 122 is the fastest with data rate sends to described agreement selected cell 123.
Described agreement selected cell 123 is the fastest pairing host-host protocol of connector of transmission speed with the transport protocol conversion on the data channel between described connector and the described microprocessor 120; Described agreement selected cell 123 can also be changed the host-host protocol on the data channel between described microprocessor 120 and the storage unit 130 simultaneously, the protocol conversion of just being responsible for described storage unit 130 is used is the host-host protocol of each data channel, and this also is a prior art.The protocol conversion function of described agreement selected cell 123 also can be realized by described microprocessor 120.
The utlity model has the 3rd embodiment of the memory storage of a plurality of connectors, it is memory storage 300, as shown in Figure 2, be with the difference of described memory storage 200, described microprocessor 120 has very strong arithmetic capability, and the control module that the microprocessor 120 of described memory storage 300 will be controlled described storage unit 130 read-write operations is arranged in the described microprocessor 120.Described memory storage 300 is connected with second storage unit 140 of storage speed measuring module.Which connector the microprocessor 120 of described memory storage 300 can detect in a plurality of connectors by port detecting unit 121 chip circuit connection states and realize physical connection, further the described port detecting unit of control calls the speed measuring module of storing among the FLASH140, with the connector of speed measuring module by a plurality of realization physical connections respectively to the host apparatus transmission measurement data bag that is connected with described memory storage 300.Described port detecting unit 121 is received the measurement data bag that external device returns, and goes out the message transmission rate of each connector with described speed measuring module according to the Time Calculation that each connector transmits data, and selects the fastest connector of transmission data.The information that the microprocessor 120 of described memory storage 300 will transmit the fastest connector of data sends to described port selected cell 122 and agreement selected cell 123 respectively.Described port selected cell 122 is responsible for the specified interface of physical connection is realized signal communication that promptly the fastest connector of transmission speed is realized signal communication.
The microprocessor 120 of described memory storage 300 is by the read-write operation of the described storage unit 130 of control module 131 controls.Described control module 131 can also be arranged between described microprocessor 120 and the storage unit 130, memory storage 400 as shown in Figure 4.
The utlity model has the 5th embodiment of the memory storage of a plurality of connectors, promptly memory storage 500, and as shown in Figure 5, the FLASH140 that the microprocessor 120 of described memory storage 500 is stored speed measuring module is set to one.The microprocessor 120 of described memory storage 500 is the read-write operation of the described storage unit 130 of control directly.
The utlity model has a plurality of connector memory storages and select the method for connector that three embodiment are arranged, first embodiment as shown in figure 10.After described memory storage was powered, described memory storage was detected which connector realization physical connection in a plurality of connectors, and concrete can carry out by the port detecting unit or the microprocessor of described memory storage.After determining to realize the connector of physical connection, whether what a plurality of connectors of the port detecting unit of memory storage or microprocessor detection realization physical connection connected is same external device.If what a plurality of connectors of memory storage connected is same external device, the port detecting unit of described memory storage or microprocessor send the measurement data bag to this external device.The port detecting unit of described memory storage or microprocessor receive the measurement data bag that described external device returns, the measurement data bag that described external device returns can be the measurement data bag that described memory storage sends, also may be the newly-generated packet of described external device, not limit here.The port detecting unit of described memory storage or microprocessor are selected the fastest connector of transmission data by receiving the time of packet.Described memory storage switches to the fastest connector of data rate with connector, and Data Transport Protocol is converted to the pairing host-host protocol of the fastest connector of data rate.
Described memory storage is selected second embodiment of connector method, as shown in figure 11.Described second method and the different of first method are, after described memory storage is powered, its port detecting unit or microprocessor send packet by all connectors of described memory storage respectively, and which connector realization physical connection of memory storage is judged in described port detecting unit or little processing according to the packet that sends.The port detecting unit of described memory storage and microprocessor utilize speed measuring module to send the measurement data bag to external device afterwards, by selecting the fastest connector of data rate.
Described memory storage is selected the 3rd embodiment of connector method, and as shown in figure 12, described memory storage is selected the third method of connector, describes the solution that may go wrong in the transmission in detail, and is specific as follows:
After described memory storage was powered, the port detecting unit of memory storage or microprocessor sent the measurement data bag to the port detecting unit of external device every the set time respectively by all connectors of memory storage.External device returns the measurement data bag to the port detecting unit or the microprocessor of described memory storage.The port detecting unit of described memory storage or microprocessor are selected the fastest connector of data rate according to the measurement data bag by the transmission time of different connector.The information of the connector that described port detecting unit or microprocessor are the fastest with transmission speed sends to port selected cell and agreement selected cell.Whether the port detecting unit or the microprocessor judges data channel of memory storage exist data transmission, and if not, the port selected cell of described memory storage is connected the data channel at the fastest connector place of data transmission; If, the agreement selected cell of described memory storage judges whether the agreement of the agreement of transmitting data and selected connector is identical, if it is different, described memory storage is waited for the end of transmission that is transmitting data, after finishing, memory storage carries out the switching of connector and the conversion of Data Transport Protocol again, if identical, described memory storage is not done the switching of connector and the conversion of Data Transport Protocol.
When described USB2.0 interface 111, USB3.0 interface 112 and ESATA interface 113 are arranged on same plug or socket, if described three interfaces are all realized physical connection, described memory storage selects described USB3.0 interface 112 to be fastest data transmission interface, and described USB3.0 interface 112 can be used power supply terminal in the described USB2.0 interface 111 as the power supply terminal of USB3.0 interface 112.Equally, described memory storage selects described ESATA interface 113 to be fastest data transmission interface, and described ESATA interface 113 can be used power supply terminal in the described USB2.0 interface 111 as the power supply terminal of ESATA interface 113.
The port detecting unit or the microprocessor of memory storage described in the utility model were just once detected its interface every the regular hour, and detecting continues the whole time period that memory storage is powered.The utility model can also change the detecting time of port detecting unit and microprocessor within a few minutes of memory storage power supply, for example within 3 minutes, because translation interface is the most frequently used when bringing into use memory storage, in 3 minutes after memory storage is powered, carry out the detecting of connector and selection automatically, to save the resource of described microprocessor, provide the processing quick-frozen of described memory storage microprocessor.
The speed measuring module of memory storage described in the utility model can be stored among the described FLASH140, when described port detecting unit 121 carries out velocity test, transfers the speed measuring module among the described FLASH140.Described speed measuring module also can not be stored among the described FLASH140, and is set directly at port detecting unit 121 inside of described memory storage, perhaps is arranged on described memory storage microprocessor 120 inside.
The host apparatus with multiple connector that the utility model provides has multiple connector, comprises the connector of various host-host protocols such as USB2.0 interface 211, USB3.0 interface 212, ESATA interface 213, infrared interface, 1394 interfaces, blue tooth interface, WIFI interface.。Three kinds of connectors on the described host apparatus, for example USB2.0 interface 211, USB3.0 interface 212, ESATA interface 213, can be the plug or the socket of three kinds of interface unifications, can be USB2.0 interface 211 and USB3.0 interface 212 two-in-one plug or socket, can be USB2.0 interface 211 and ESATA interface two-in-one plug or socket, the set-up mode of three kinds of connectors on described host apparatus do not limit.Described host apparatus of the present utility model can be the device that desktop computer, notebook computer, hand-held palm PC, audio/video player etc. can be used as host apparatus, and concrete form does not limit.
First embodiment of host apparatus described in the utility model, promptly host apparatus 600, as shown in Figure 6.Described host apparatus 600 comprises CPU (central processing unit) 220, is connected the microprocessor 230 on the described CPU220, and described microprocessor 230 is also referred to as the first microprocessor of host apparatus 600, and described microprocessor 230 connects internal memory and display controller.Described microprocessor 230 also connects the another one microprocessor 240 of host apparatus 600, described microprocessor 240 is also referred to as second microprocessor of host apparatus 600, described microprocessor 240 connects the storage unit 250 of host apparatus 600, the USB2.0 interface 211 of described host apparatus 600, USB3.0 interface 212, ESATA interface 213 are connected on the port detecting unit 241 of described host apparatus, and the port detecting unit 241 of described host apparatus is connected on the described microprocessor 240 by port selected cell 242.Described host apparatus also comprises power control unit 260, and described power control unit 260 is each module for power supply of host apparatus, and not shown power control unit 260 is the connecting line of whole module for power supply.
Which connector the port detecting unit 241 of described host apparatus or microprocessor 240 can be discerned by the chip circuit connection state and realize physical connection.The connector that is provided with on the described host apparatus is three-in-one connector, promptly a connector is integrated under the situation of USB2.0 interface 211, USB3.0 interface 212 and 213 3 kinds of connectors of ESATA interface, the three-in-one interface of the three-in-one connector of described host apparatus 600 and external device realizes whether the three-in-one interface that described port detecting unit 241 or microprocessor 240 or CPU220 can discern on the described host apparatus automatically realizes physical connection under the situation of physical connection.
Described host apparatus 600 realizes under the situation of physical connection at the described three kinds of connectors of identification, and port detecting unit 241 by described host apparatus or microprocessor 240 or CPU220 judge whether the external device of described three kinds of connector physical connections is same external devices.External device in described three kinds of connector physical connections is under the situation of same external device, and the port detecting unit 241 of described host apparatus sends packet by described three connectors to external device respectively.The time of the packet that described port detecting unit 241 or microprocessor 240 return by external device, judge the speed of described three connectors transmission data, and therefrom select to specify the excuse of connector as described host apparatus 600 and external device data channel.Described appointment connector can be the fastest connector of transmission speed, or the slowest connector of transmission speed, or the most stable connector of transmission speed, as long as the result can learn according to testing the speed, here do not limit, the utility model serves as to specify connector to select the fastest connector of transmission speed.
The port detecting unit 121 of described host apparatus 600 can draw a fastest connector of transmission data according to the time of transmitting-receiving measurement data bag.The information that the port detecting unit 241 of described host apparatus will transmit the fastest connector of data sends to the port selected cell 242 of described host apparatus, will select the interface of the fastest connector of transmission data as data channel by the port selected cell 242 of described host apparatus.The connector of described microprocessor 240 or CPU220 connection variety of protocol can be realized the transport protocol conversion of different connector automatically, behind the fastest connector of selected transmission data, described microprocessor 240 or CPU220 finish the task of data channel transmitted data protocol conversion automatically.
Second embodiment of host apparatus described in the utility model, promptly host apparatus 700, as shown in Figure 7.The difference of described host apparatus 700 and host apparatus 600 is, the port detecting unit 241 of described host apparatus and port selected cell 242 are arranged at described microprocessor 240 simultaneously, described microprocessor 240 can be the South Bridge chip of host apparatus, and described microprocessor 230 can be the north bridge chips of host apparatus.
The 3rd embodiment of host apparatus described in the utility model, promptly host apparatus 800, as shown in Figure 8.Described host apparatus 800 is with the difference of described host apparatus 600, has saved microprocessor 230, and the internal memory and the display controller of host apparatus directly is connected on the described CPU220, and described microprocessor 240 directly is connected with described CPU220.Described host apparatus 800 also can save north bridge chips, the port detecting unit 241 and the port selected cell 242 of host apparatus are arranged at South Bridge chip, direct and the described CPU220 of this South Bridge chip is connected, a plurality of connectors of described host apparatus are connected on the described host apparatus South Bridge chip, and South Bridge chip also connects storage unit 250.Saved a microprocessor 230 among the embodiment of described host apparatus 800, host apparatus 800 volume inside have been saved, enhancing along with the CPU computing power, the function of microprocessor 230 can be replaced by described CPU220, make the integrated level of host apparatus inner member higher, help saving the cost of host apparatus.
North bridge chips is responsible for the data transmission of CPU and internal memory, and South Bridge chip is responsible for the communication between the I/O bus, comprises the access of keyboard, mouse and the conversion of respective data transfer agreement, and this is that prior art repeats no more here.
The 4th embodiment of host apparatus described in the utility model, promptly host apparatus 900, as shown in Figure 9.The difference of described host apparatus 900 and host apparatus 800 is, further saved microprocessor 240, described internal memory, display controller and storage unit 250 are connected on the described CPU220, described a plurality of connector is connected on the described port detecting unit 241, and described port detecting unit 241 is connected on the described CPU220 by port selected cell 242.The port detecting unit 241 of described host apparatus recognizes after which connector in a plurality of connectors realizes physical connection, and described port detecting unit 241 sends the measurement data bag by the connector of physical connection to external device respectively.After described port detecting unit 241 received the packet that external device returns, described port detecting unit went out the speed of each connector transmission data according to the Time Calculation of transmitting-receiving measurement data bag.The fastest interface of described port detecting unit 241 or CPU selected transmission data, by the port selected cell 242 of described host apparatus the connector of data channel is switched to the fastest connector of transmission data, and finish by CPU220 host-host protocol on the data channel is converted to the fastest pairing host-host protocol of connector of described transmission data.
The utility model can also be integrated in described CPU220 with the port detecting unit 241 and the port selected cell 242 of described host apparatus, the microprocessor 240 and/or 230 of described host apparatus can also be integrated in described CPU220, just South Bridge chip and/or north bridge chips be integrated in described CPU220.
Described port detecting unit 241 detected a plurality of data connect realize physical connection with external device after, all can send packet by each connector of realizing physical connection to external device respectively at regular intervals, just carry out the velocity test of a connector at regular intervals, carry out the selection of a connector that data rate is the fastest at regular intervals, guarantee that effectively host apparatus carries out data transmission with the fastest data channel all the time.
In the host apparatus port detecting unit 241 described in the utility model speed measuring module can be set, described speed measuring module can also be arranged among South Bridge chip or the host apparatus CPU, when described port detecting unit 121 carries out velocity test, transfer the velocity test that the speed measuring module among described South Bridge chip or the host apparatus CPU carries out.
The port detecting unit 121 of memory storage described in the utility model and the port detecting unit of host apparatus 241 are selected the fastest connector of transmission speed, comprise following choice criteria:
The first, the transmission of port detecting unit sends single appointment size by a plurality of connectors, and for example the measurement data bag of 4k compares the time that each connector returns the measurement data bag, and what the selection measurement data pack receiving and transmitting time was the shortest is the fastest connector of transmission speed.
The second, the port detecting unit sends by a plurality of connectors and repeatedly sends a plurality of measurement data bags of specifying size respectively, for example send 4k measurement data bag to each connector, and then transmission 8k measurement data bag, relatively each connector returns the time of different measurement data bags, calculate connector and repeatedly transmit the mean value of measurement data bag time, selecting the connector of measurement data pack receiving and transmitting time average minimum is the fastest connector of transmission speed.
Three, the port detecting unit sends by a plurality of connectors and sends a plurality of measurement data bags of specifying size respectively, for example send 4k measurement data bag to each connector, and then transmission 8k measurement data bag, relatively each connector returns the time of different measurement data bags, calculate connector and repeatedly transmit the weighted mean value of measurement data time, selecting the connector of measurement data pack receiving and transmitting weighted mean value minimum is the fastest connector of transmission speed.
Select the fastest standard of transmission speed to be not limited to above description, above choice criteria can be carried out by the port detecting unit 121 of described memory storage and the port detecting unit 241 of host apparatus, is perhaps carried out by the speed measuring module of described memory storage and the speed measuring module of host apparatus.
The speed measuring module of memory storage described in the utility model and the speed measuring module of host apparatus comprise: clock unit is used to calculate the time of receiving and dispatching the time bag that tests the speed; Computation subunit according to the time that each connector transmitting-receiving time of testing the speed wraps, is calculated the transmission speed by the measurement data bag of the connector that tests the speed; Subelement relatively also, the speed of each connector transmission data relatively, comparison rule transmission speed as previously discussed is the choice criteria of fast connector, repeats no more here.Described speed measuring module can also be stored in the storage unit of described memory storage and the storage unit of host apparatus, for example is stored in the independent partitions of each storage unit, and described port detecting unit can call the speed measuring module in the storage unit.
The transmission speed of each connector that speed measuring module described in the utility model can calculate calculating sub module is presented on the display screen of memory storage, or on the display screen of host apparatus, by manually selecting by modes such as the button on memory storage or the host apparatus, button or touch-screens, select to specify connector, and will specify the information of connector to return to described speed measuring module, port detecting unit or microprocessor.
The speed measuring module of memory storage described in the utility model or host apparatus, port detecting unit or microprocessor can also comprise transmission submodule that sends the measurement data bag and the reception submodule that receives sub-measurement data bag, and described transmission submodule can also be connected the clock that is used to calculate the measurement data pack receiving and transmitting time with the reception submodule.
With described memory storage unanimity, on host apparatus, when described USB2.0 interface 211, USB3.0 interface 212 and ESATA interface 213 are arranged on same plug or socket, if described three interfaces are with realizing physical connection, described host apparatus selects described USB3.0 interface 212 to be fastest data transmission interface, and described USB3.0 interface 212 can be used power supply terminal in the described USB2.0 interface 211 as the power supply terminal of USB3.0 interface 212.Equally, described host apparatus selects described ESATA interface 213 to be fastest data transmission interface, and described ESATA interface 213 can be used power supply terminal in the described USB2.0 interface 211 as the power supply terminal of ESATA interface 213.
Host apparatus described in the utility model can be when its a plurality of connectors be connected same external device, select to transmit the fastest connector of data by the mode of velocity test and carry out the passage of data transmission, effectively improve the work efficiency of host apparatus as host apparatus and external device.
The utility model host apparatus is selected the specific embodiment of the fastest connector method, as shown in figure 13, may further comprise the steps:
At first, host apparatus detects its a plurality of connectors and realizes physical connection; Judge then whether two above connectors realizing physical connection connect same external device.
If it is respectively different external devices that two above connectors connect, described host apparatus is realized each connector and each external device respectively the UNICOM of data-signal with prior art.
If two above connector connections is same external device, host apparatus can send the measurement data bag to external device respectively by a plurality of connectors every special time.External device returns the measurement data bag by each connector to described host apparatus, the described measurement data bag that returns can be the measurement data bag that described host apparatus sends, and also can be described external device according to the measurement data bag of the host apparatus that receives and newly-generated packet.Test the speed of each connector transmission data by the mode that connector is sent packet.The port detecting unit of described host apparatus can be used for receiving and sending the measurement data bag, according to the time of measurement data pack receiving and transmitting, calculates the speed of each connector transmission data.
The port detecting unit of described host apparatus or South Bridge chip or CPU select transmission data speed the fastest connector, and the information that will transmit the fastest connector of data sends to the port selected cell.
After having selected the fastest connector of transmission data, the South Bridge chip of described host apparatus and/or CPU judge whether the data channel of current connection exists data transmission.
If there is not data transmission in data channel, the port selected cell of described host apparatus is connected the pairing data channel of connector of the tool of data rate, and the south bridge process chip of described host apparatus and/or CPU switch to the pairing Data Transport Protocol of the fastest connector of data rate with Data Transport Protocol afterwards.
If there is data transmission in data channel, the south bridge process chip of described host apparatus and/or CPU judge the host-host protocol that transmitting data and whether selected to transmit the fastest pairing host-host protocol of connector of data identical.
If it is identical with the corresponding host-host protocol of selected connector to transmit the host-host protocol of data, then host apparatus is not done port switching and protocol conversion.
If it is different with the corresponding host-host protocol of selected connector to transmit the host-host protocol of data, after described host apparatus waits for that the data transmission of transmitting finishes, the port selected cell of described host apparatus is connected the fastest pairing data channel of connector of data transmission, then finish protocol conversion, carry out data transmission with fastest connector at last.
Host apparatus of the present utility model connects same external device simultaneously with three-in-one connector on the host apparatus and illustrate that host apparatus selects the fastest connector of transmission data speed as selected connector from three-in-one connector, two-in-one interfaces connects the connector selection of same external device simultaneously on the host apparatus, or the connector that four unification interfaces connect same external device simultaneously on the host apparatus selects, and the system of selection of host apparatus of the present utility model and host apparatus is identical not limiting here.Described connector is not limited to USB2.0 interface, USB3.0 interface and ESATA interface
The agreement selecting arrangement that the utility model provides comprises the port detecting unit, in the port detecting unit speed measuring module is set.
Second embodiment of described agreement selecting arrangement is with the difference of first embodiment, also comprises: first connector is respectively applied for the connector that connects on host apparatus South Bridge chip or the CPU; First power interface is respectively applied for the power interface that connects on host apparatus South Bridge chip or the CPU; Second connector, the connector of the variety of protocol of connection host apparatus, second source interface, the power interface in the variety of protocol connector of connection host apparatus.
The 3rd embodiment of described agreement selecting arrangement is with the difference of first embodiment, also comprises: first data connecting line is respectively applied for the data terminal that connection host apparatus South Bridge chip or CPU go up connector; First electric power connection line is respectively applied for the power supply terminal that connects the power interface on host apparatus South Bridge chip or the CPU; Second data connecting line, the data terminal of the connector of the variety of protocol of connection host apparatus, second source connecting line, the power supply terminal of the power interface in the variety of protocol connector of connection host apparatus.
The 4th embodiment of described agreement selecting arrangement is with the difference of the 3rd embodiment, described first data connecting line replaces with first data terminal, first electric power connection line replaces with first power supply terminal, second data connecting line replaces with second data terminal, and the second source connecting line is the second source terminal.
Described agreement selecting arrangement can be added between active computer South Bridge chip and the various protocols connector, and the function of active computer is got a promotion, and with low cost.
Should be understood that above-mentioned statement at the utility model preferred embodiment is comparatively detailed, can not therefore think the restriction to the utility model scope of patent protection, scope of patent protection of the present utility model should be as the criterion with claims.
Claims (16)
1. the host apparatus with multiple connector comprises multiple connector, CPU, storage unit, internal memory and display controller, and is the power control unit of each module for power supply of memory storage, it is characterized in that,
Also comprise the port detecting unit, be connected with described multiple connector respectively; Send the measurement data bag to multiple connector respectively, detect the transmission speed of each connector, utilize the result that tests the speed to select to specify connector according to the measurement data bag that returns;
The port selected cell selects described appointment connector and external device to be communicated with;
Described host apparatus selects to specify the connector of connector as data channel between external device and the storage unit.
2. host apparatus according to claim 1 is characterized in that, described appointment connector is the slowest connector or the most stable connector of transmission speed of transmission speed the fastest connector, transmission speed.
3. host apparatus according to claim 2 is characterized in that, described port detecting unit comprises the speed measuring module by the transmission speed of each connector of time detecting of transmitting-receiving measurement data bag.
4. host apparatus according to claim 3 is characterized in that, described speed measuring module comprises: computation subunit, calculate transmission speed by the measurement data bag of the connector that tests the speed; Relatively subelement compares the speed that each connector transmits data.
5. host apparatus according to claim 4, it is characterized in that, described port detecting unit connectivity port switch unit, described port switch unit is connected on the described storage unit by second microprocessor, the different host-host protocol of the described second microprocessor control transformation; Described internal memory and display controller are connected to first microprocessor, and described second microprocessor is connected on the CPU by described first microprocessor.
6. host apparatus according to claim 4, it is characterized in that, described port detecting unit connectivity port switch unit, described port switch unit is connected on the described storage unit by second microprocessor, the different host-host protocol of the described second microprocessor control transformation; Described internal memory, display controller and second microprocessor are connected on the described CPU.
7. host apparatus according to claim 4 is characterized in that, described port detecting unit connects described port switch unit, and described port switch unit connects described CPU, and described internal memory and display controller are connected on the described CPU.
8. according to claim 5 or 6 or 7 described host apparatus, it is characterized in that described first microprocessor is a north bridge chips, second microprocessor is a South Bridge chip.
9. host apparatus according to claim 8 is characterized in that, described speed measuring module, port detecting unit, second microprocessor or CPU comprise the transmission submodule and receive submodule.
10. host apparatus according to claim 9 is characterized in that, described speed measuring module is arranged among storage unit, second microprocessor or the CPU of host apparatus.
11. host apparatus according to claim 10 is characterized in that, described speed measuring module, port detecting unit, microprocessor or CPU comprise the judgement submodule of selecting connector.
12. host apparatus according to claim 4 is characterized in that, described multiple connector comprises USB2.0 interface, USB3.0 interface and ESATA interface, infrared interface, 1394 interfaces, blue tooth interface, WIFI interface.
13. host apparatus according to claim 12 is characterized in that, described USB2.0 interface, USB3.0 interface and ESATA interface are three-in-one plug or socket.
14. host apparatus according to claim 13, it is characterized in that, described USB3.0 interface or ESATA are communicated with power supply for the selected the fastest data-interface of transmission data, the power supply terminal in the described USB2.0 interface, as the power end of described USB3.0 interface or ESATA interface.
15. an agreement selecting arrangement comprises: the measurement data bag that returns to multiple connector transmission measurement data bag basis detects the port detecting unit of the transmission speed of each connector respectively,
Described port detecting unit comprises computation subunit, calculates the transmission speed by the measurement data bag of connector; Subelement relatively, relatively the speed of each connector transmission data result that tests the speed selects to specify connector port;
Described protocol conversion apparatus also comprises the interface that is connected with multiple connector, and the interface that is connected with South Bridge chip or CPU.
16. agreement selecting arrangement according to claim 15 is characterized in that, described port detecting unit also comprises the judgement submodule of selecting connector.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201020116611XU CN201616094U (en) | 2010-02-11 | 2010-02-11 | Host device with multiple connectors and protocol selection device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201020116611XU CN201616094U (en) | 2010-02-11 | 2010-02-11 | Host device with multiple connectors and protocol selection device |
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| Publication Number | Publication Date |
|---|---|
| CN201616094U true CN201616094U (en) | 2010-10-27 |
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| CN201020116611XU Expired - Lifetime CN201616094U (en) | 2010-02-11 | 2010-02-11 | Host device with multiple connectors and protocol selection device |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2016009250A1 (en) * | 2014-07-14 | 2016-01-21 | Pismo Labs Technology Limited | Methods and systems for transmitting data packets |
| CN106292847A (en) * | 2015-05-22 | 2017-01-04 | 鸿富锦精密工业(武汉)有限公司 | Mainboard |
| CN107402898A (en) * | 2012-08-29 | 2017-11-28 | 联想(北京)有限公司 | The method and electronic equipment of a kind of information processing |
| US10511522B2 (en) | 2014-07-14 | 2019-12-17 | Pismo Labs Technology Limited | Methods and systems for evaluating network performance of and transmitting packets through an aggregated connection |
-
2010
- 2010-02-11 CN CN201020116611XU patent/CN201616094U/en not_active Expired - Lifetime
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107402898A (en) * | 2012-08-29 | 2017-11-28 | 联想(北京)有限公司 | The method and electronic equipment of a kind of information processing |
| CN107402898B (en) * | 2012-08-29 | 2020-08-25 | 联想(北京)有限公司 | Information processing method and electronic equipment |
| WO2016009250A1 (en) * | 2014-07-14 | 2016-01-21 | Pismo Labs Technology Limited | Methods and systems for transmitting data packets |
| GB2534259A (en) * | 2014-07-14 | 2016-07-20 | Pismo Labs Technology Ltd | Methods and Systems for Transmitting Data Packets |
| US9602412B2 (en) | 2014-07-14 | 2017-03-21 | Pismo Labs Technology Limited | Methods and systems for transmitting data packets |
| US10511522B2 (en) | 2014-07-14 | 2019-12-17 | Pismo Labs Technology Limited | Methods and systems for evaluating network performance of and transmitting packets through an aggregated connection |
| GB2534259B (en) * | 2014-07-14 | 2021-04-21 | Pismo Labs Technology Ltd | Methods and systems for transmitting data packets |
| CN106292847A (en) * | 2015-05-22 | 2017-01-04 | 鸿富锦精密工业(武汉)有限公司 | Mainboard |
| CN106292847B (en) * | 2015-05-22 | 2019-03-08 | 鸿富锦精密工业(武汉)有限公司 | Mainboard |
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| C14 | Grant of patent or utility model | ||
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| C56 | Change in the name or address of the patentee |
Owner name: AIGO ELECTRONICS TECHNOLOGY CO., LTD. Free format text: FORMER NAME: BEIJING AIGO DIGITAL STORAGE TECHNOLOGY CO., LTD. |
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| CP01 | Change in the name or title of a patent holder |
Address after: 100080 Beijing, North Fourth Ring Road West, No. 58, International Building, ideal level 11, Patentee after: Aigo Electronic Technology Co., Ltd. Address before: 100080 Beijing, North Fourth Ring Road West, No. 58, International Building, ideal level 11, Patentee before: Beijing Aigo Digital Storage Technology Co., Ltd. |
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| CX01 | Expiry of patent term | ||
| CX01 | Expiry of patent term |
Granted publication date: 20101027 |