CN201499172U - Frequency modulation digital exciter based on FPGA - Google Patents
Frequency modulation digital exciter based on FPGA Download PDFInfo
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- CN201499172U CN201499172U CN2009201071899U CN200920107189U CN201499172U CN 201499172 U CN201499172 U CN 201499172U CN 2009201071899 U CN2009201071899 U CN 2009201071899U CN 200920107189 U CN200920107189 U CN 200920107189U CN 201499172 U CN201499172 U CN 201499172U
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Abstract
The utility model relates to frequency modulation broadcast radiation equipment, in particular to a frequency modulation digital exciter based on an FPGA and used in a frequency modulation broadcast radiation system, which comprises a digital preprocessing unit, a digital signal processing unit, a modulation unit and a control unit, wherein the digital signal processing unit consists of an FPGA and a memory PROM, wherein the memory PROM is connected with the FPGA, the FPGA carries out amplitude control, low-pass wave filtering, audio time delay, audio preemphasis, interpolation wave filtering, stereo modulation and modulation regulation on digital audio signals sent by the digital preprocessing module after the format regulation and velocity conversion through a built-in function module, the digital audio signals are sent to the modulation unit for generating radio-frequency signals of the frequency modulation broadcast, the FPGA is connected with the control unit, and a program forming the function module in the FPG is solidified in the memory PROM. The FPGA has the advantages of flexible configuration, high work efficiency, simple programming and the like, and the frequency modulation digital exciter has strong performance price ratio advantage when being used as a main design chip.
Description
Technical field
The utility model relates to a kind of FM broadcasting transmitter, particularly a kind of FM Digital Exciter based on FPGA that is used for the FM broadcasting emission system.
Background technology
At present, the FM exciter in most of broadcasting station is (as shown in Figure 1) of adopting analog and frequency modulation modulation technology, to carry out stereo coding formation baseband signal through the preliminary treatment audio analog signals and send into generation carrier wave (the frequency interleaved modulation modulator modulation of 87.0～108MHz) PLCC frequency synthesizer, antennas emission after amplifying again.Owing to itself just there are differences between the components and parts of analog (preliminary treatment, preemphasis, stereo coding) and frequency modulation(FM) (phase-locked loop), external environment condition is arranged in actual applications all the time all changing again, cause analog and warbled technical indicator consistency low.Modulation degree between every exciter differs ± and 15%, carrier deviation 1 * 10
-5The order of magnitude more than, (frequency departure requires≤1 * 10 not meet the specification requirement of the national standard " GY/T154-2000 synchronous frequency-modulating broadcast systems technology standard " of synchronous frequency-modulating broadcast
-9The audio frequency phase deviation requires≤5 μ s; The modulation degree deviation requires≤2.5%), can not be used to make up high-quality synchronous frequency-modulating broadcast network.
For addressing the above problem, the patent No. 200620108907.0 utility model patents provide the technical scheme of the digital frequency modulation broadcast transmitter of a kind of employing high speed numerical processor (DSP), its structure as shown in Figure 2, adopt analog to digital converter that simulated audio signal sampling or AES audio signal decoding are become digital signal, send into carry out digital preliminary treatment, digital difference filtering, preemphasis, numeral produces the 19kHz pilot tone and becomes composite signal with 38kHz subcarrier frequency, stereo coding, the composite signal that high speed numerical processor produces is sent the modulation of DDS frequency synthesizer.Control section adopts microprocessor, touch-screen to carry out the response and the processing of information.
It is not high that this patent adopts the DSP high speed numerical processor that digital signal is handled its cost performance.Because the DSP high speed numerical processor exists power consumption big and be not suitable for parallel processing.The FM Digital Exciter how a kind of high performance-price ratio is provided is the eternal target of broadcasting equipment manufacturing.
Great mass of data shows, requires in the harshest Digital Signal Processing (DSP) systems design and development current, and FPGA is playing the part of more and more important role.Research and development through two more than ten years, FPGA has developed and has been impayable high value DSP solution platform, all having risen to high level aspect performance, flexibility, Time To Market and the life of product, also greatly reduce overall system cost and power consumption simultaneously.
The key that the DSP performance of FPGA is leading is its inherent parallel mechanism, promptly utilizes parallel architecture to realize the function of DSP function.
Not only relate to filtering in the application, independently benchmark test shows, even under the real work load, FPGA also has very big performance advantage.
FPGA can accomplish very high effect.The FPGA platform does not need the outer logical resource of the amount of consumption just can finish signal processing function, so the designer can be issued to performance and cost objective in the situation that obtains higher effect.FPGA is leading over DSP aspect performance and the effect simultaneously.
Because the defective that above-mentioned existing digital frequency modulation broadcast transmitter exists, the design people is based on being engaged in this type of product design manufacturing abundant for many years practical experience and professional knowledge, and cooperate the utilization of scientific principle, and actively studied innovation, make it have more practicality in the hope of what found a kind of new structure.Through constantly research, design, and, create the utility model that has practical value finally through after studying sample and improvement repeatedly.
Summary of the invention
The purpose of this utility model be for the consistency of the technical indicator that overcomes existing FM exciter low, the problem of poor stability, provide a kind of cost performance high FM Digital Exciter based on FPGA, adopt on-site programmable gate array FPGA to carry out digital processing, realize stereo coding modulation and frequency modulation modulation by digital frequency synthesis technology, realized the radio frequency output and the carrier synchronization of high stability.
The purpose of this utility model and to solve its technical problem be to adopt following technical scheme to realize.According to a kind of FM Digital Exciter that the utility model proposes based on FPGA, comprise digital pretreatment unit, digital signal processing unit, modulating unit and control unit, wherein said digital signal processing unit is to be made of with the memory PROM that is connected FPGA FPGA, the digital audio and video signals after form adjustment and rate transition that described FPGA sends digital pretreatment unit here by interior functional module of establishing carries out amplitude control, low-pass filtering, audio delay, audio preemphasis, interpolation filtering, stereo modulation and modulation are adjusted, send described modulating unit to generate the radiofrequency signal of FM broadcasting, described FPGA connects described control unit, is solidified with the program that forms the functional module among the FPGA among the described memory PROM.
The purpose of this utility model and solve its technical problem and can also be further achieved by the following technical measures.
Aforesaid FM Digital Exciter based on FPGA, wherein said digital pretreatment unit comprises audio A C stereophonic signal sampler, microphone signal sampler, digital audio interface transducer, described audio A C stereophonic signal sampler mainly is to be made of the audio frequency modulus conversion chip, and the left and right acoustic channels audio signal of input is sampled becomes digital signal with analog signal conversion; The microphone signal sampler mainly is to be made of modulus conversion chip, and the microphone signal sampling also becomes digital signal with analog signal conversion; Described digital audio interface transducer mainly is to be made of the digital audio conversion chip, receives the digital audio code stream of AES3 or S/PDIF form, carry out the conversion of the form adjustment of digital audio and sampling rate after, send FPGA.
Aforesaid FM Digital Exciter based on FPGA, wherein said control unit is a high speed microprocessor, whole system realizes man-machine interaction by button and LCD MODULE.
Aforesaid FM Digital Exciter based on FPGA, the functional module of establishing in the wherein said on-site programmable gate array FPGA comprises: signal type selector, audio delay module, time division multiplexing module, preemphasis filter module, interpolation filter module, stereo synthesis module, DDS and PLL control interface and Single-chip Controlling interface, wherein
Described signal type selector connects described audio A C stereophonic signal sampler, microphone signal sampler, digital audio interface transducer as audio input port, with about the data of two sound channels select to send the audio delay module, and each all corresponding preparation pulse signal (ready signal) of a clock cycle that provides of new data as indication;
Left and right sound track signals and preparation pulse signal (ready signal) that described audio delay module is sent the signal type selector here are delayed time, and the audio delay scope is from 0-999 μ s, and stepping is 1 μ s; And with the time-delay audio signal send the time division multiplexing module;
Described time division multiplexing module connects described audio delay module, and the left and right sound track signals and the preparation pulse signal of delaying time was interweaved in the different time periods, sends the preemphasis filter module to along same channel;
Described preemphasis filter module is carried out preemphasis filtering to the HFS in the signal that transmits and is sent interpose module;
Described interpose module connects described preemphasis filter module, will carry out the sample frequency that interpolation improves modulation back baseband signal through the signal of preemphasis, and the output of described interpose module connects described stereo synthesis module;
Described stereo synthesis module is modulated to required stereo composite signal with filtered left and right acoustic channels and send modulating unit by described DDS and PLL control interface;
Baseband signal that described DDS and PLL control interface obtain stereo composite part and centre frequency numerical value carry out compose operation and obtain the required control word of Direct Digital Frequency Synthesizers DDS, send modulating unit Direct Digital Frequency Synthesizers DDS;
Described signal type selector, audio delay module, preemphasis filter module, stereo synthesis module connect the single-chip microcomputer of described control unit by described Single-chip Controlling interface, FPGA receives the control command of single-chip microcomputer, can control in real time input signal types, audio delay number, preemphasis filtering parameter and modulation system according to order; Simultaneously, FPGA returns to single-chip microcomputer with current relevant information and shows.
Aforesaid FM Digital Exciter based on FPGA, wherein said time delay module comprises main time delay module and B delay module, and described main time delay module realizes that by peripheral memory SRAM stepping is the time-delay of 20 μ s, and promptly amount of delay is 0/20/40/60... μ s; Described B delay module realizes that stepping is 1 μ s time-delay in that FPGA is inner, and reference time delay realizes the audio delay scope from 0-999 μ s from 0 μ s to 19 μ s, and stepping is 1 μ s.
Aforesaid FM Digital Exciter based on FPGA, the FIR filter that wherein said preemphasis filter is 64 rank carries out convolution by time domain to audio signal and realizes preemphasis; The preemphasis time constant of described preemphasis filter is three kinds of 0 μ s, 25 μ s and 50 μ s, and its amplitude-frequency characteristic is: differ in the range value of each Frequency point pre-emphasis curve and standard value and be no more than ± 1dB; Phase characteristic is a linear phase; Output voltage when being located at audio frequency and being zero is V
1, the output voltage V when audio frequency front end frequency is Ω/2 π
2, then
Aforesaid FM Digital Exciter based on FPGA, the FIR filter that wherein said interpose module is 508 rank, its interpolation factor are 32, frequency is 1.6MHz after the interpolation, and band connection frequency is 15kHz, and stop-band frequency is 25kHz, passband ripple is 0.1dB, and stopband attenuation is 75dB.
Aforesaid FM Digital Exciter based on FPGA, comprise amplitude adjusting module, pilot tone and carrier wave generation module, stereo modulation module in the wherein said stereo synthesis module and select synthesis module, the left and right sound track signals that described amplitude adjusting module is come out interpolation filter is adjusted parameter according to the single-chip microcomputer amplitude and is carried out the amplitude adjustment, to meet the needs of modulation degree, and send described stereo modulation module with the adjusted left and right sound track signals of amplitude, also left channel signals is sent to be elected simultaneously and select synthesis module; Phase control parameter generating 19kHz pilot signal and 38kHz subcarrier signal that described pilot tone and carrier wave generation module transmit according to single-chip microcomputer, and they are synchronous, and send described stereo modulation module with 19kHz pilot signal and the 38kHz subcarrier signal that is produced; Described stereo modulation module is adjusted parameter according to the pilot amplitude of single-chip microcomputer the adjusted left and right sound track signals of described amplitude is handled, and mixes the required stereo composite signal of generation with the 19kHz pilot tone and send to be elected and select synthesis module; The microphone signal that microphone signal sampler in left channel signals that the stereo composite signal that described selection synthesis module is sent described stereo modulation module here, described amplitude adjusting module are sent here and the described digital pretreatment unit is sent here selects synthetic synthetic baseband signal of generation monophony+microphone or the synthetic baseband signal of stereo+microphone to send Direct Digital Frequency Synthesizers DDS.
Aforesaid FM Digital Exciter based on FPGA, wherein said modulating unit comprise DDS clock generating module, Direct Digital Frequency Synthesizers DDS, filtering and amplification, power amplifier and power control; Described DDS clock generating module is a phase-locked loop, and it is the sinusoidal signal of 1GHz that described phase-locked loop produces frequency, send Direct Digital Frequency Synthesizers DDS as work clock, thereby realizes Frequency Synchronization; The baseband signal that described Direct Digital Frequency Synthesizers DDS sends FPGA in the digital signal processing unit here is modulated into the analog signal of the broadcasting channel of carrier frequency 87～108MHz, and exports described filtering and amplifying circuit to; Harmonic components in described filtering and the amplifying circuit filtering analog signal and spuious composition also send power amplifier with its amplification.
The utility model compared with prior art has tangible advantage and beneficial effect.By technique scheme, the utility model can reach suitable technological progress and practicality based on the FM Digital Exciter of FPGA, and has the extensive value on the industry, and it has following advantage at least:
1, the utility model adopts FPGA as main signal processing module, FPGA is as a kind of programmable logic device, have advantages such as flexible configuration, high efficiency, programming be simple, and in recent years, the low-end product price is more and more cheaper, and its main separation chip as design is had very strong superiority of effectiveness.
2, the speed of service is fast, and FPGA is two kinds of different treatment systems with DSP, and FPGA inside is that hardwired is realized entirely, duplicates by functional module, realizes that the parallel processing of large-scale data amount is advantageous; And DSP is the instruction collecting system, generally realizes serial algorithm, and is slower than FPGA on the speed.This parallel mechanism makes FPGA be specially adapted to finish the repeated DSP task as filtering.Therefore, framework is carried out in the serial of the far super general dsp processor of FPGA performance for highly-parallel is carried out the DSP task.For example, each clock cycle of traditional dsp processor can be finished 8 MAC operations at most.Carry out the filter of one 256 tap, traditional dsp processor need be carried out 32 clock cycle under the 1GHz clock, just can reach the sampling processing performance of 31.25MSPS.Compare therewith, under the 500MHz clock, can reach the performance of 500MSPS at 512 the parallel FPGA that have of this employing.Therefore the time doppio lunghezza di tempo situation under, the performance height that FPGA provides more than magnitude.
3, preemphasis filtering is realized preemphasis by designing a linear phase FIR filter among the FPGA, and the range value of filter frequency domain response pre-emphasis curve on each Frequency point and standard value differ maximum and be no more than ± 0.5dB.And DSP realizes it being earlier signal to be changed to frequency domain to multiply each other with the preemphasis window function and become time domain again again, and operand is bigger, and can introduce must error, what phase response neither linearity.
4, all computings of stereo composite part all are to carry out on the basis of 1.6MHz sample rate, and the 196kHz sample rate can obtain higher precision when DSP realizes, thereby the signal quality that produces is better.
5, the audio signal bit wide remains 24bit, has guaranteed accuracy.
In sum, the utility model has above-mentioned plurality of advantages and practical value based on the FM Digital Exciter of FPGA, no matter it all has bigger improvement on the structure of product or function, obvious improvement is arranged technically, and produced handy and practical effect, and more existing FM Digital Exciter has the outstanding multinomial effect of enhancement, thus be suitable for practicality more, and have the extensive value of industry, really be a new and innovative, progressive, practical new design.
Above-mentioned explanation only is the general introduction of technical solutions of the utility model, for can clearer understanding technological means of the present utility model, and can be implemented according to the content of specification, and for above-mentioned and other purposes, feature and advantage of the present utility model can be become apparent, below especially exemplified by preferred embodiment, and conjunction with figs., be described in detail as follows.
Description of drawings
Fig. 1 is the existing circuit diagram that adopts the broadcast modulation exciter of analog and frequency modulation modulation technique.
Fig. 2 is the existing circuit theory diagrams that adopt the digital frequency modulation broadcast transmitter of high speed numerical processor (DSP).
Fig. 3 is the circuit diagram of the utility model based on the FM Digital Exciter of FPGA.
Fig. 4 establishes circuit diagram in the on-site programmable gate array FPGA in the utility model FM Digital Exciter.
Fig. 5 is the interior audio delay modular circuit structure chart of the on-site programmable gate array FPGA in the utility model FM Digital Exciter.
Fig. 6 is the interior stereo synthesis module circuit structure diagram of the on-site programmable gate array FPGA in the utility model FM Digital Exciter.
Embodiment
For further setting forth the utility model is to reach technological means and the effect that predetermined utility model purpose is taked, below in conjunction with accompanying drawing and preferred embodiment, to according to its embodiment of FM Digital Exciter, structure, feature and the effect thereof that the utility model proposes based on FPGA, describe in detail as after.
See also shown in Figure 3, the utility model preferred embodiment it mainly comprises based on the FM Digital Exciter of FPGA: digital pretreatment unit, digital signal processing unit, modulating unit and control unit, wherein said digital signal processing unit is to be made of with the memory PROM that is connected FPGA FPGA, the digital audio and video signals after form adjustment and rate transition that described FPGA sends digital pretreatment unit here by interior functional module of establishing carries out amplitude control, low-pass filtering, audio delay, audio preemphasis, interpolation filtering, stereo modulation and modulation are adjusted, send described modulating unit to generate the radiofrequency signal of FM broadcasting, described FPGA connects described control unit, is solidified with the program that forms the functional module among the FPGA among the described memory PROM.
Described digital pretreatment unit comprises audio A C stereophonic signal sampler, microphone signal sampler, digital audio interface transducer; Wherein
Described audio A C stereophonic signal sampler mainly is to be made of the audio frequency modulus conversion chip, and the left and right acoustic channels audio signal of input is sampled becomes the 50kHz digital signal with analog signal conversion, specifically is to have adopted 24bit audio A C chip PCM4202.This chip adopts ∑ Δ modulation technique, uses 256 times of over-samplings and noise shaped technology, reduced voiced band interior (noise of 20Hz～20kHz), thus improved the signal to noise ratio of chip.The clock of its over-sampling adopts the unified clock of system, and frequency is 12.8MHz.Simultaneously, integrated decimation filter of digital function has quite high filtering performance and low delay in this chip block; And this part chip can be sampled simultaneously to the signal of left and right sound channels, and by left-justify, Right Aligns and I
2The S form spreads out of voice data, and the utility model has adopted left-Aligned mode.
Described microphone signal sampler mainly is to be made of modulus conversion chip, and the microphone signal sampling also becomes the 50kHz digital signal with analog signal conversion; This part circuit mainly is to additional channel language broadcast singal, and promptly microphone signal is nursed one's health with low pass and sampled.By conditioning, make full use of the number of significant digit of 16 ADC, also played the certain protection effect simultaneously.Specifically be to adopt 16-Bit ADC chip AD7686, support that high sampling rate is 500kSPS.This chip block can be supported the pseudo-differential analog signal input of 0～5V, can support the digital output interface of 1.8V～5.0V simultaneously; Its volume is very little, and control is simple, uses the mode of serial to transmit sampled data.
Described digital audio interface transducer mainly is to be made of the digital audio conversion chip, receives the digital audio code stream of AES3 or S/PDIF form, carry out the conversion of the form adjustment of digital audio and sampling rate after, send FPGA.Digital audio and video signals is by AES3, the input of S/PDIF form, simultaneously because the sampling rate of external digital audio signal may be different from the audio sampling frequency of native system, so will carry out the form adjustment of digital audio and the conversion of sampling rate.Here 24 digital bit audio sample rate conversion chip CS8420 have been adopted, it can realize the mutual conversion between AES3, S/PDIF audio data format and the serial audio data format, and can extract the sample frequency of input audio signal, by SRC (Sampling Rate Converter) module, realize that sampling rate transforms simultaneously.In addition, it is also to realize that by configuration register AES3, S/PDIF tear frame open and framing is handled.The serial audio data format of this chip industry has left-justify, Right Aligns and I
2The S form has adopted left-Aligned mode here.
Described control unit is a high speed microprocessor, and whole system realizes the demonstration at man-machine interaction LCD MODULE complete operation interface by button and LCD MODULE.The user can revise system operational parameters by serial line interface by button or from distance host, and system preserves the running parameter that the user is provided with, and the assurance power down is not lost.Simultaneously, system also passes to digital signal processing unit with running parameter, makes it carry out work according to the parameter that is provided with, and system detects the operating state of Digit FM Exciter intermediate power amplifier in real time, and by the size of adjusting control voltage it is controlled.In addition, system can read and be provided with the work at present time by real-time clock.
As shown in Figure 4, the functional module of establishing in the described on-site programmable gate array FPGA comprises: signal type selector, audio delay module, time division multiplexing module, preemphasis filter module, interpolation filter module, stereo synthesis module, DDS and PLL control interface and Single-chip Controlling interface, wherein
Described signal type selector connects described audio A C stereophonic signal sampler, microphone signal sampler, digital audio interface transducer as audio input port, with about two sound channel speed be that the data of 50kHz select to send the audio delay module, and all corresponding preparation pulse signal (ready signal) conduct indication that provides a clock cycle of new data each, and left and right sides two paths of signals new data goes out to differ now 128 clock cycle; The external audio input mainly is divided into two classes: analogue audio frequency and digital audio.For analogue audio frequency, utilize the PCM4202 chip that left and right sound track signals is carried out 50kHz sampling respectively, obtain digital signal and enter among the FPGA and handle; For digital audio, utilize the CS8420 chip to carry out sampling rate conversion, obtain 50kHz left and right sides two-way sampled signal equally and enter among the FPGA.
Left and right sound track signals and preparation pulse signal (ready signal) that described audio delay module is sent the signal type selector here are delayed time, and the audio delay scope is from 0-999 μ s, and stepping is 1 μ s; And with the time-delay audio signal send the time division multiplexing module;
Described time division multiplexing module connects described audio delay module, and the left and right sound track signals and the preparation pulse signal of delaying time was interweaved in the different time periods, sends the preemphasis filter module to along same channel;
Described preemphasis filter module is carried out preemphasis filtering to the HFS in the signal that transmits and is sent interpose module;
Described interpose module connects described preemphasis filter module, will carry out the sample frequency that interpolation improves modulation back baseband signal through the signal of preemphasis, and the output of described interpose module connects described stereo synthesis module;
Described stereo synthesis module is modulated to required stereo composite signal with filtered left and right acoustic channels and send modulating unit by described DDS and PLL control interface;
Baseband signal that described DDS and PLL control interface obtain stereo composite part and centre frequency numerical value carry out compose operation and obtain the required control word of Direct Digital Frequency Synthesizers DDS, send modulating unit Direct Digital Frequency Synthesizers DDS;
Described signal type selector, audio delay module, preemphasis filter module, stereo synthesis module connect the single-chip microcomputer of described control unit by described Single-chip Controlling interface, FPGA receives the control command of single-chip microcomputer, can control in real time input signal types, audio delay number, preemphasis filtering parameter and modulation system according to order; Simultaneously, FPGA returns to single-chip microcomputer with current relevant information and shows.
As shown in Figure 5, described time delay module comprises main time delay module and B delay module, and described main time delay module realizes that by peripheral memory SRAM stepping is the time-delay of 20 μ s, and promptly amount of delay is 0/20/40/60... μ s; Described B delay module is 1 μ s time-delay in the inner realization of FPGA stepping, and reference time delay is from 0 μ s to 19 μ s, realize that the audio delay scope is from 0-999 μ s, number T can be expressed as T=20*k1+k2 because delay time arbitrarily in the 0-999 μ s scope, 0≤k1≤49 wherein, 0≤k2≤19 are so just can realize required accurate delay number as long as suitably regulate the main time-delay and the B delay parameter of two modules.
Described preemphasis filter is the FIR filter on 64 rank, by time domain audio signal is carried out convolution and realizes preemphasis; The preemphasis time constant of described preemphasis filter is three kinds of 0 μ s, 25 μ s and 50 μ s, and its amplitude-frequency characteristic is: at each Frequency point, the range value of pre-emphasis curve and standard value differ and are no more than ± 1dB; Phase characteristic is a linear phase; Output voltage when being located at audio frequency and being zero is V
1, the output voltage V when audio frequency front end frequency is Ω/2 π
2, then
Described interpose module is the FIR filter on 508 rank, and its interpolation factor is 32, and frequency is 1.6MHz after the interpolation, and band connection frequency is 15kHz, and stop-band frequency is 25kHz, and passband ripple is 0.1dB, and stopband attenuation is 75dB.
As shown in Figure 7, described stereo synthesis module mainly is modulated to left and right acoustic channels required stereo composite signal.Be input as filtering signal and associated control signal afterwards, be output as the data after modulation is synthesized, its physical circuit comprises: amplitude adjusting module, pilot tone and carrier wave generation module, stereo modulation module and selection synthesis module; Wherein:
The left and right sound track signals that described amplitude adjusting module is come out interpolation filter is adjusted parameter according to the single-chip microcomputer amplitude and is carried out the amplitude adjustment, to meet the needs of modulation degree, and send described stereo modulation module with the adjusted left and right sound track signals of amplitude, also left channel signals is sent to be elected simultaneously and select synthesis module; Described audio signal (L, R) to input is carried out the amplitude adjustment, comprises input impedance selection (balance or uneven mode), and the attenuation setting of controlled audio frequency attenuator.Controlled audio frequency attenuator makes the interior audio signal of certain level range all can be set to nominal value (reference level).During the nominal level input, the output baseband signal is 75kHz to the frequency modulation of carrier wave.
Phase control parameter generating 19kHz pilot signal and 38kHz subcarrier signal that described pilot tone and carrier wave generation module transmit according to single-chip microcomputer, specifically be to produce subcarrier (38kHz) by phase control words, 38kHz is carried out 1/2 frequency division produces 19kHz, it as pilot signal.And they are synchronous, and send described stereo modulation module with 19kHz pilot signal and the 38kHz subcarrier signal that is produced;
In the middle of pilot tone and carrier wave generation module, the algorithm that has used similar DDS signal to produce, establishing clock frequency is f
Clk, phase control words is W
p, bit wide N
p, frequency control word is W
f, bit wide N
f, the sine look up table degree of depth is 2^N
p, then under the constant situation of phase control words, clock cycle of every mistake, output sinusoidal signal phase change is
Thereby the output sinusoidal signal frequency is
Here, f
Clk=12.8MHz, N
f=24, f
Out=19kHz and 38kHz, substitution following formula can calculate frequency control word W
fBe respectively 24904 (19kHz) and 49808 (38kHz).In addition, establishing phase delay is p
Delay(rad), phase control words W then
pComputing formula is as follows
Described stereo modulation module is adjusted parameter according to the pilot amplitude of single-chip microcomputer the adjusted left and right sound track signals of described amplitude is handled, and mix with the 19kHz pilot tone and to produce required stereo composite signal (Stereo_data), comprising left and right sides road signal and, left and right sides road signal difference and pilot tone after suppressed subcarrier (38kHz) amplitude modulation, send to be elected and select synthesis module;
Stereo_data＝(L·adj_L-R·adj_R)·Carrier_38k+(L·adj_L+R·adj_R)+Pilot_19k·adj_P
In the formula, L is a left road signal, and R is the right wing signal, and adj_L is left road attenuation (amplitude adjustment), and adj_R is right wing audio damping amount (amplitude adjustment), and Carrier_38k is the 38k subcarrier, and Pilot_19k is a pilot signal, and adj_P is that pilot amplitude is adjusted parameter.
Described selection synthesis module is selected monophone pattern or stereo mode by the modulation relative parameters setting, synthesizes with the microphone signal sampling then.Specifically be stereo composite signal that described stereo modulation module is sent here, the microphone signal sent here of left channel signals that described amplitude adjusting module is sent here and the microphone signal sampler in the described digital pretreatment unit selects syntheticly to generate the synthetic baseband signal of monophony+microphone or the synthetic baseband signal of stereo+microphone is sent Direct Digital Frequency Synthesizers DDS.
Described modulating unit comprises DDS clock generating module, Direct Digital Frequency Synthesizers DDS, filtering and amplification, power amplifier and power control; Described DDS clock generating module is a phase-locked loop, and it is the sinusoidal signal of 1GHz that described phase-locked loop produces frequency, send Direct Digital Frequency Synthesizers DDS as work clock, thereby realizes Frequency Synchronization; The baseband signal that described Direct Digital Frequency Synthesizers DDS sends FPGA in the digital signal processing unit here is modulated into the analog signal of the broadcasting channel of carrier frequency 87～108MHz, and exports described filtering and amplifying circuit to; Harmonic components in described filtering and the amplifying circuit filtering analog signal and spuious composition also send power amplifier with its amplification.
The above, it only is preferred embodiment of the present utility model, be not that the utility model is done any pro forma restriction, though the utility model discloses as above with preferred embodiment, yet be not in order to limit the utility model, any those skilled in the art, in not breaking away from the technical solutions of the utility model scope, when the technology contents that can utilize above-mentioned announcement is made a little change or is modified to the equivalent embodiment of equivalent variations, in every case be the content that does not break away from technical solutions of the utility model, according to technical spirit of the present utility model to any simple modification that above embodiment did, equivalent variations and modification all still belong in the scope of technical solutions of the utility model.
Claims (9)
1. FM Digital Exciter based on FPGA, comprise digital pretreatment unit, digital signal processing unit, modulating unit and control unit, it is characterized in that described digital signal processing unit is to be made of with the memory PROM that is connected FPGA FPGA, the digital audio and video signals after form adjustment and rate transition that described FPGA sends digital pretreatment unit here by interior functional module of establishing carries out amplitude control, low-pass filtering, audio delay, audio preemphasis, interpolation filtering, stereo modulation and modulation are adjusted, send described modulating unit to generate the radiofrequency signal of FM broadcasting, described FPGA connects described control unit, is solidified with the program that forms the functional module among the FPGA among the described memory PROM.
2. the FM Digital Exciter based on FPGA according to claim 1, it is characterized in that described digital pretreatment unit comprises audio A C stereophonic signal sampler, microphone signal sampler, digital audio interface transducer, described audio A C stereophonic signal sampler mainly is to be made of the audio frequency modulus conversion chip, and the left and right acoustic channels audio signal of input is sampled becomes the 50kHz digital signal with analog signal conversion; The microphone signal sampler mainly is to be made of modulus conversion chip, and the microphone signal sampling also becomes digital signal with analog signal conversion; Described digital audio interface transducer mainly is to be made of the digital audio conversion chip, receives the digital audio code stream of AES3 or S/PDIF form, carry out the conversion of the form adjustment of digital audio and sampling rate after, send FPGA.
3. the FM Digital Exciter based on FPGA according to claim 1 is characterized in that described control unit is a high speed microprocessor, and whole system realizes man-machine interaction by button and LCD MODULE.
4. the FM Digital Exciter based on FPGA according to claim 1, the functional module of establishing in it is characterized in that in the described on-site programmable gate array FPGA comprises: signal type selector, audio delay module, time division multiplexing module, preemphasis filter module, interpolation filter module, stereo synthesis module, DDS and PLL control interface and Single-chip Controlling interface, wherein
Described signal type selector connects described audio A C stereophonic signal sampler, microphone signal sampler, digital audio interface transducer as audio input port, with about the data of two sound channels select to send the audio delay module, and each all corresponding preparation pulse signal of a clock cycle that provides of new data as indication;
Left and right sound track signals and preparation pulse signal that described audio delay module is sent the signal type selector here are delayed time, and the audio delay scope is from 0-999 μ s, and stepping is 1 μ s; And with the time-delay audio signal send the time division multiplexing module;
Described time division multiplexing module connects described audio delay module, and the left and right sound track signals and the preparation pulse signal of delaying time was interweaved in the different time periods, sends the preemphasis filter module to along same channel;
Described preemphasis filter module is carried out preemphasis filtering to the HFS in the signal that transmits and is sent interpose module;
Described interpose module connects described preemphasis filter module, will carry out the sample frequency that interpolation improves modulation back baseband signal through the signal of preemphasis, and the output of described interpose module connects described stereo synthesis module;
Described stereo synthesis module is modulated to required stereo composite signal with filtered left and right acoustic channels and send modulating unit by described DDS and PLL control interface;
Baseband signal that described DDS and PLL control interface obtain stereo composite part and centre frequency numerical value carry out compose operation and obtain the required control word of DDS chip, send the Direct Digital Frequency Synthesizers DDS of modulating unit;
Described signal type selector, audio delay module, preemphasis filter module, stereo synthesis module connect the single-chip microcomputer of described control unit by described Single-chip Controlling interface, FPGA receives the control command of single-chip microcomputer, can control in real time input signal types, audio delay number, preemphasis filtering parameter and modulation system according to order; Simultaneously, FPGA returns to single-chip microcomputer with current relevant information and shows.
5. the FM Digital Exciter based on FPGA according to claim 4, it is characterized in that described time delay module comprises main time delay module and B delay module, described main time delay module realizes that by peripheral memory SRAM stepping is the time-delay of 20 μ s, and promptly amount of delay is 0/20/40/60... μ s; Described B delay module realizes that stepping is 1 μ s time-delay in that FPGA is inner, and reference time delay realizes the audio delay scope from 0-999 μ s from 0 μ s to 19 μ s, and stepping is 1 μ s.
6. the FM Digital Exciter based on FPGA according to claim 4 is characterized in that described preemphasis filter is the FIR filter on 64 rank, by time domain audio signal is carried out convolution and realizes preemphasis; The preemphasis time constant of described preemphasis filter is three kinds of 0 μ s, 25 μ s and 50 μ s, and its amplitude-frequency characteristic is: at each Frequency point, the range value of pre-emphasis curve and standard value differ and are no more than ± 1dB; Phase characteristic is a linear phase; Output voltage when being located at audio frequency and being zero is V
1, the output voltage V when audio frequency front end frequency is Ω/2 π
2, then
7. the FM Digital Exciter based on FPGA according to claim 4, it is characterized in that described interpose module is the FIR filter on 508 rank, its interpolation factor is 32, frequency is 1.6MHz after the interpolation, band connection frequency is 15kHz, stop-band frequency is 25kHz, and passband ripple is 0.1dB, and stopband attenuation is 75dB.
8. the FM Digital Exciter based on FPGA according to claim 4, it is characterized in that comprising in the described stereo synthesis module amplitude adjusting module, pilot tone and carrier wave generation module, stereo modulation module and select synthesis module, the left and right sound track signals that described amplitude adjusting module is come out interpolation filter is adjusted parameter according to the single-chip microcomputer amplitude and is carried out the amplitude adjustment, to meet the needs of modulation degree, and send described stereo modulation module with the adjusted left and right sound track signals of amplitude, also left channel signals is sent to be elected simultaneously and select synthesis module; Phase control parameter generating 19kHz pilot signal and 38kHz subcarrier signal that described pilot tone and carrier wave generation module transmit according to single-chip microcomputer, and they are synchronous, and send described stereo modulation module with 19kHz pilot signal and the 38kHz subcarrier signal that is produced; Described stereo modulation module is adjusted parameter according to the pilot amplitude of single-chip microcomputer the adjusted left and right sound track signals of described amplitude is handled, and mixes the required stereo composite signal of generation with the 19kHz pilot tone and send to be elected and select synthesis module; The microphone signal that microphone signal sampler in left channel signals that the stereo composite signal that described selection synthesis module is sent described stereo modulation module here, described amplitude adjusting module are sent here and the described digital pretreatment unit is sent here selects synthetic synthetic baseband signal of generation monophony+microphone or the synthetic baseband signal of stereo+microphone to send Direct Digital Frequency Synthesizers DDS.
9. the FM Digital Exciter based on FPGA according to claim 1 is characterized in that described modulating unit comprises DDS clock generating module, Direct Digital Frequency Synthesizers DDS, filtering and amplification, power amplifier and power control; Described DDS clock generating module is a phase-locked loop, and it is the sinusoidal signal of 1GHz that described phase-locked loop produces frequency, send Direct Digital Frequency Synthesizers DDS as work clock, thereby realizes Frequency Synchronization; The baseband signal that described Direct Digital Frequency Synthesizers DDS sends FPGA in the digital signal processing unit here is modulated into the analog signal of the broadcasting channel of carrier frequency 87～108MHz, and exports described filtering and amplifying circuit to; Harmonic components in described filtering and the amplifying circuit filtering analog signal and spuious composition also send power amplifier with its amplification.
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| CN109120283A (en) * | 2017-06-26 | 2019-01-01 | 上海数字电视国家工程研究中心有限公司 | digital frequency modulation transmitter |
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