CN201417760Y - Chip packaging structure - Google Patents

Chip packaging structure Download PDF

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Publication number
CN201417760Y
CN201417760Y CN2009201506316U CN200920150631U CN201417760Y CN 201417760 Y CN201417760 Y CN 201417760Y CN 2009201506316 U CN2009201506316 U CN 2009201506316U CN 200920150631 U CN200920150631 U CN 200920150631U CN 201417760 Y CN201417760 Y CN 201417760Y
Authority
CN
China
Prior art keywords
circuit board
recessed groove
metal wire
wafer
connect
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN2009201506316U
Other languages
Chinese (zh)
Inventor
许俊杰
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Haojia Electronics (Shenzhen) Co. Ltd.
Original Assignee
HAOJIA ELECTRONIC CO Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by HAOJIA ELECTRONIC CO Ltd filed Critical HAOJIA ELECTRONIC CO Ltd
Priority to CN2009201506316U priority Critical patent/CN201417760Y/en
Application granted granted Critical
Publication of CN201417760Y publication Critical patent/CN201417760Y/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01078Platinum [Pt]

Abstract

The utility model provides a chip packaging structure, especially a chip packaging structure for digital and optical lens. The structure comprises a circuit board, a chip, metal wire, lens frame and lens etc., characterized in that the circuit board is provided with a recess at specific position for accommodating chip and metal wire, then circuit board at the recess is connected with a package structure such as lens frame and lens for lowering the height of whole set of packaging structure.

Description

A kind of chip package structure
Technical field
The utility model relates to a kind of encapsulating structure, relates in particular to a kind of chip package structure, and the height of whole group of encapsulating structure after the improvement is significantly reduced.
Background technology
See also the form that Figure 1 shows that existing chip package structure, mainly be connect on a circuit board 10 plate faces establish a wafer 20 and many metal wires 30 after, on circuit board 10 plate faces, connect again and establish with encapsulating structure, for example be a lens mount 30, covering wafer 20 and metal wire 30, and finish encapsulation.Yet stressing compact digital electronic product, as if the height of the whole group of this kind encapsulating structure slightly dislikes higher, if can allow the height of whole group encapsulating structure reduce, Ying Gengneng meets the requirement of trend again, therefore, existing chip package structure still remains to be improved.
Summary of the invention
Main purpose of the present utility model is to provide a kind of chip package structure, and the height of whole group of encapsulating structure after the improvement is significantly reduced.
In order to achieve the above object, the utility model provides a kind of chip package structure, for example can be the chip package structure that a kind of digit optical camera lens is used, described chip package structure includes members such as circuit board, wafer, metal wire, lens mount and lens, be characterized in forming between a recessed groove at the ad-hoc location on the circuit board, provide wafer and metal wire ccontaining its inside, connect on the circuit board plate face between recessed groove again establish the encapsulation purposes lens mount with capping wafer and metal wire, in addition, on lens mount, be equipped with lens.
Compared with prior art, chip package structure described in the utility model significantly reduces the height of whole group of encapsulating structure after the improvement.
Description of drawings
Fig. 1 is existing chip package structure schematic diagram;
Fig. 2 is chip package structure first embodiment of the present utility model;
Fig. 3 is chip package structure second embodiment of the present utility model;
Fig. 4 is chip package structure the 3rd embodiment of the present utility model;
Fig. 5 is chip package structure the 4th embodiment of the present utility model.
Description of reference numerals: 10-circuit board; Between the 11-recessed groove; The 20-wafer; The 30-metal wire; The 40-lens mount; The 50-lens; The 60-daughter board.
Embodiment
See also shown in Figure 2, be chip package structure first embodiment of the present utility model, described encapsulating structure includes circuit board 10, wafer 20, metal wire 30, members such as lens mount 40 and lens 50, forming between a saturating empty recessed groove 11 on the circuit board 10, and the affixed thin type daughter board 60 of circuit board 10 plate basifacials at place, 11 bottoms between recessed groove, described daughter board material can be metal, soft board, hardboard, the plastic cement hard board, glass etc., establish wafer 20 and metal wire 30 to connect, wherein the routing Copper Foil can utilize plating mode or perforation mode to spread copper and finish, on the circuit board 10 plate faces on 11 between recessed groove, connect again and establish lens mount 40, with capping wafer 20 and metal wire 30, lens mount 40 is provided with lens 50, by 11 ccontaining wafer 20 and metal wires 30 between recessed groove, compare the height that directly is arranged in the packaged type on the circuit board 10 plate faces and then more reduce.
See also and Figure 3 shows that chip package structure second embodiment of the present utility model, described encapsulating structure includes circuit board 10, wafer 20, metal wire 30, members such as lens mount 40 and lens 50, form between a saturating empty recessed groove 11 at the ad-hoc location on the circuit board 10, an and affixed thin type daughter board 60 in 11 bottoms between recessed groove, establish wafer 20 and metal wire 30 for connecing, on the circuit board 10 plate faces on 11 between recessed groove, connect again and establish lens mount 40 with capping wafer 20 and metal wire 30, by 11 ccontaining wafer 20 and metal wires 30 between recessed groove, compare the height that directly is arranged in the packaged type on the circuit board 10 plate faces and then more reduce.
See also and Figure 4 shows that chip package structure the 3rd embodiment of the present utility model, described encapsulating structure includes circuit board 10, wafer 20, metal wire 30, members such as lens mount 40 and lens 50, form between a saturating empty recessed groove 11 at the ad-hoc location on the circuit board 10, and between recessed groove circuit board 10 plates at 11 bottoms places towards the interior engaging groove 12 of an area that slightly cave in greater than 11 area between recessed groove, an affixed thin type daughter board 60 in engaging groove 12, establish wafer 20 and metal wire 30 to connect, on the circuit board 10 plate faces on 11 between recessed groove, connect again and establish lens mount 40 with capping wafer 20 and metal wire 30, this compares the height that directly is arranged in the packaged type on the circuit board 10 plate faces and then more reduces by 11 ccontaining wafer 20 and metal wires 30 between recessed groove.
See also and Figure 5 shows that chip package structure the 4th embodiment of the present utility model, described encapsulating structure includes circuit board 10, wafer 20, metal wire 30, members such as lens mount 40 and lens 50, forming between saturating empty recessed groove 11 on the circuit board 10, and 11 bottom inner plate surfaces connect and establish wafer 20 and metal wire 30 between recessed groove, on the circuit board 10 plate faces on 11 between recessed groove, connect again and establish lens mount 40, compare the height that directly is arranged in the packaged type on the circuit board 10 plate faces by 11 ccontaining wafers 20 and metal wire 30 between recessed groove and then more reduce with capping wafer 20 and metal wire 30.
Therefore, of the present utility model being characterised in that when setting up wafer at circuit board, if with between a recessed groove, to reduce whole height, promptly use the method for packing of sunk, make circuit board have thinner thickness, and it is convenient when being applied to electronic product, can make the littler structure of finished product, obtain practical improvement, meet patent requirement.
More than explanation is just illustrative for the utility model; and it is nonrestrictive; those of ordinary skills understand; under the situation of the spirit and scope that do not break away from following claims and limited; can make many modifications, variation or equivalence, but all will fall in the protection range of the present utility model.

Claims (5)

1. chip package structure, it includes circuit board, wafer, metal wire, reaches encapsulating structure, it is characterized in that, forming on the described circuit board between a recessed groove, ccontaining between described recessed groove for described wafer and described metal wire, the described encapsulating structure of combination on the circuit board between described recessed groove again.
2. chip package structure according to claim 1 is characterized in that, on the described circuit board recessed groove between be empty, and between described recessed groove the affixed thin slice daughter board of circuit board plate face at place, bottom, establish described wafer and described metal wire to connect; Connect the lens mount of establishing encapsulation usefulness on the circuit board plate face between described recessed groove again, with described wafer of capping and described metal wire.
3. chip package structure according to claim 1, it is characterized in that, be empty between the recessed groove on the described circuit board, and between described recessed groove in the bottom an affixed thin type daughter board connect and establish described wafer and described metal wire, connect on the circuit board plate face between described recessed groove again establish encapsulate usefulness lens mount with described wafer of capping and described metal wire.
4. chip package structure according to claim 1, it is characterized in that, be empty between the recessed groove on the described circuit board, and the circuit board plate that the bottom is located between described recessed groove is towards the interior engaging groove that is depression one area greater than the area between recessed groove, an affixed thin type daughter board is established described wafer and described metal wire to connect in described engaging groove, connect on the circuit board plate face between described recessed groove again establish encapsulation usefulness lens mount with described wafer of capping and described metal wire.
5. chip package structure according to claim 1, it is characterized in that, it between the recessed groove on the described circuit board non-sky, and the bottom inner plate surface connects and establishes described wafer and described metal wire between described recessed groove, connect on the circuit board plate face between described recessed groove again establish encapsulation usefulness lens mount with described wafer of capping and described metal wire.
CN2009201506316U 2009-05-05 2009-05-05 Chip packaging structure Expired - Fee Related CN201417760Y (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN2009201506316U CN201417760Y (en) 2009-05-05 2009-05-05 Chip packaging structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN2009201506316U CN201417760Y (en) 2009-05-05 2009-05-05 Chip packaging structure

Publications (1)

Publication Number Publication Date
CN201417760Y true CN201417760Y (en) 2010-03-03

Family

ID=41794187

Family Applications (1)

Application Number Title Priority Date Filing Date
CN2009201506316U Expired - Fee Related CN201417760Y (en) 2009-05-05 2009-05-05 Chip packaging structure

Country Status (1)

Country Link
CN (1) CN201417760Y (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104052910A (en) * 2014-06-25 2014-09-17 解春慧 Packaging structure of optical lens
WO2020034144A1 (en) * 2018-08-16 2020-02-20 深圳市汇顶科技股份有限公司 Optical sensing module and manufacturing method therefor
WO2020034171A1 (en) * 2018-08-17 2020-02-20 深圳市汇顶科技股份有限公司 Optical sensing module and manufacturing method therefor

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104052910A (en) * 2014-06-25 2014-09-17 解春慧 Packaging structure of optical lens
WO2020034144A1 (en) * 2018-08-16 2020-02-20 深圳市汇顶科技股份有限公司 Optical sensing module and manufacturing method therefor
WO2020034171A1 (en) * 2018-08-17 2020-02-20 深圳市汇顶科技股份有限公司 Optical sensing module and manufacturing method therefor

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Legal Events

Date Code Title Description
C14 Grant of patent or utility model
GR01 Patent grant
ASS Succession or assignment of patent right

Owner name: CRS ELECTRONIC (SHENZHEN) CO., LTD.

Free format text: FORMER OWNER: HAOJIA ELECTRONIC CO., LTD.

Effective date: 20110412

C41 Transfer of patent application or patent right or utility model
COR Change of bibliographic data

Free format text: CORRECT: ADDRESS; FROM: TAIPEI COUNTY, TAIWAN, CHINA TO: 518110 NO. 28, GUIHUAQIAO PARK, GUIHUA COMMUNITY, GUANLAN SUBDISTRICT, BAOAN DISTRICT, SHENZHEN CITY, GUANGDONG PROVINCE

TR01 Transfer of patent right

Effective date of registration: 20110412

Address after: 518110, Guihua bridge community, Guihua community, Guanlan street, Shenzhen, Guangdong, Baoan District 28

Patentee after: Haojia Electronics (Shenzhen) Co. Ltd.

Address before: Taiwan County, Taipei, China

Patentee before: Haojia Electronic Co., Ltd.

C17 Cessation of patent right
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20100303

Termination date: 20140505