CN201376891Y

CN201376891Y - Multi-layer circuit conducting wafer-level MEMS chip

Info

Publication number: CN201376891Y
Application number: CN200920040415U
Authority: CN
Inventors: 陈闯
Original assignee: KUNSHAN XITAI MICROELECTRONICS TECHNOLOGY Co Ltd
Current assignee: KUNSHAN XITAI MICROELECTRONICS TECHNOLOGY Co Ltd
Priority date: 2009-04-22
Filing date: 2009-04-22
Publication date: 2010-01-06
Anticipated expiration: 2019-04-22

Abstract

The utility model discloses a multi-layer circuit conducting wafer-level MEMS (micro electro mechanical system) chip; an integrated circuit welding pad and a light focusing area are arranged on the upper end surface of a wafer; two sides of integrated circuit welding pad are filled with glue layers; the integrated circuit welding pad and the glue layers are bonded with glass through resin; at least two layers of circuits conducted with the integrated circuit welding pad are arranged at the lower part of the wafer; all layers of circuits of the wafer are conducted according to the design; an insulating layer is arranged at the non-conducting part of the layer of circuit close to the integrated circuit welding pad and the integrated circuit welding pad and plays a separation role, and the insulating layers are also arranged at the non-conducting parts of all layers of circuits and play a separation role; a plurality of solder ball welding pad are formed on the layer of circuit close to the lower end surface of the wafer as designed; the lower end surface of the wafer adopts the insulating layer; a solder ball exposed out of the lower end surface of the wafer is arranged at the part of the lower end surface of the wafer corresponding to the solder ball welding pad; and the solder ball is conducted with the solder ball welding pad. At least two layers of mutually-conducted circuits arranged at the lower part of the wafer to replace the original single layer circuit, so as to meet demands of the client in respects of small size, multiple circuits, wide circuits, small spacing of the welding pad.

Description

The multilayer line conduction type wafer-level chip of micro-electro-mechanical system

Technical field

The utility model relates to the wafer-level chip of micro-electro-mechanical system technical field, especially a kind of multilayer line conduction type wafer-level chip of micro-electro-mechanical system.

Background technology

(the English abbreviation: MEMS) (English is called for short the chip through-silicon-via wafer current level micro electromechanical system: TSV) in the encapsulation technology manufacturing process, generally adopt individual layer line layout form, expose wafer inner conductive piece (English abbreviation: pad) by preceding operation, sputtering aluminum, photoresistance coating exposure imaging, nickel plating, remove photoresist, deluster and carve the aluminium of glue-line, etching, the nickel plating gold, welding resisting layer coating exposure imaging, paste solder printing, technologies such as Reflow Soldering make the wafer inside and outside electrically interconnected, produce needed circuit and BGA (English abbreviation: BGA) weld pad, wafer-level micro electromechanical system (MEMS) chip of producing by above-mentioned technology contains the circuit of one deck and conducting block conducting, general line width and circuit or weld pad spacing are at the 40-100 micrometer range, spacing between the weld pad edge is many about 300 microns, electrically interconnectedly in the spacing about 300 microns go out three to four circuits from the wafer inside and outside, and satisfy the requirement of live width line-spacing, operation faces various problems under the prior art condition, there is etching unclean during as etching, disconnected short circuit problem etc., it is extremely difficult to avoid bad problem, directly influences output and yield, and the design of customer line must be drawn three or above circuit sometimes in spacing between the weld pad edge, make production technology face adverse conditions, the yield cost advantage no longer, thereby the restriction competitiveness of product.

Summary of the invention

In order to overcome above-mentioned defective, the utility model provides a kind of multilayer line conduction type wafer-level chip of micro-electro-mechanical system, can reach multi-line on the customer requirement product small size, wide circuit and little weld pad spacing each side needs.

The utility model for the technical scheme that solves its technical problem and adopt is:

A kind of multilayer line conduction type wafer-level chip of micro-electro-mechanical system, comprise glass and wafer, (the English abbreviation: IC) face is the upper surface with the integrated circuit of wafer, the upper surface of described wafer is provided with integrated circuit weld pad and extraction regions, the integrated circuit weld pad part both sides of described wafer are filled with glue and form glue-line, the integrated circuit weld pad of the upper surface of wafer and glue-line are by resin and glass bonding, the bottom of described wafer is provided with the circuit that the integrated circuit weld pad with wafer is conducted, the bottom of described wafer is provided with two-layer at least circuit, press the design conducting between each layer line road of wafer, near the circuit of integrated circuit weld pad and the non-conduction place obstruct of integrated circuit weld pad insulating barrier is arranged, non-conduction place between each layer line road intercepts insulating barrier, circuit near the wafer lower surface is formed with some tin ball pad by design, the wafer lower surface is an insulating barrier, the position of the corresponding tin ball pad in described wafer lower surface is provided with the tin ball that exposes outside the wafer lower surface, described tin ball and the conducting of tin ball pad.

The beneficial effects of the utility model are: because the bottom of wafer is provided with and two-layerly at least substitutes one deck circuit originally by design conducting mutual conduction line, thereby realized client's multi-line on small size, the each side needs of wide circuit and little weld pad spacing; Can adopt traditional circuit interlayer conduction technology during making, successfully manage product size downsizing and product circuit densification, improve the product yield.

Description of drawings

Fig. 1 is a cross-sectional view of the present utility model.

The specific embodiment

Embodiment: a kind of multilayer line conduction type wafer-level chip of micro-electro-mechanical system, comprise glass 1 and wafer, integrated circuit (IC) face with wafer is the upper surface, the upper surface of described wafer is provided with integrated circuit weld pad 2 and extraction regions 3, the integrated circuit weld pad part both sides of described wafer are filled with glue 4 and form glue-line, the integrated circuit weld pad 2 of the upper surface of wafer and glue-line are by resin 5 and glass bonding, the bottom of described wafer is provided with the circuit 6 that the integrated circuit weld pad 2 with wafer is conducted, the bottom of described wafer is provided with two-layer at least circuit 6, press the design conducting between each layer line road 6 of wafer, near the circuit of integrated circuit weld pad 2 and the non-conduction place obstruct of integrated circuit weld pad 2 insulating barrier 7 is arranged, non-conduction place between each layer line road 6 intercepts insulating barrier 7, circuit 6 near the wafer lower surface is formed with some tin ball pad 8 by design, the wafer lower surface is an insulating barrier 7, the position of the corresponding tin ball pad 8 in described wafer lower surface is provided with the tin ball 9 that exposes outside the wafer lower surface, described tin ball 9 and 8 conductings of tin ball pad.

Because the bottom of wafer is provided with and two-layerly at least substitutes one deck circuit originally by design conducting mutual conduction line, thereby has realized client's multi-line on small size, the each side needs of wide circuit and little weld pad spacing; Can adopt traditional circuit interlayer conduction technology during making, successfully manage product size downsizing and product circuit densification, improve the product yield.

Claims

1. multilayer line conduction type wafer-level chip of micro-electro-mechanical system, comprise glass (1) and wafer, integrated circuit face with wafer is the upper surface, the upper surface of described wafer is provided with integrated circuit weld pad (2) and extraction regions (3), the integrated circuit weld pad part both sides of described wafer are filled with glue (4) and form glue-line, the integrated circuit weld pad of the upper surface of wafer and glue-line are by resin (5) and glass bonding, the bottom of described wafer is provided with the circuit (6) that the integrated circuit weld pad with wafer is conducted, it is characterized in that: the bottom of described wafer is provided with two-layer at least circuit, press the design conducting between each layer line road of wafer, near the circuit of integrated circuit weld pad and the non-conduction place obstruct of integrated circuit weld pad insulating barrier (7) is arranged, non-conduction place between each layer line road intercepts insulating barrier, circuit near the wafer lower surface is formed with some tin ball pad (8) by design, the wafer lower surface is an insulating barrier, the position of the corresponding tin ball pad in described wafer lower surface is provided with the tin ball (9) that exposes outside the wafer lower surface, described tin ball and the conducting of tin ball pad.