CN201341159Y - Frequency drift compensation arrangement in MSK differential detection demodulator circuit - Google Patents

Abstract

The utility model discloses a Frequency drift compensation arrangement in MSK differential detection demodulator circuit, which belongs to the communication system frequency drift compensation field. The compensation arrangement of the utility model comprises a accumulator, a sequential controller, a constant divider, a constant subtracter, an offset register and a subtracter. The utility model has a simple structure, simplifies frequency drift compensation arrangement.

Description

MSK differential detection and demodulation circuit medium frequency drift compensation device

Technical field

The utility model relates to a kind of MSK differential detection and demodulation circuit medium frequency drift compensation device, belongs to frequency-drift compensation field to received signal in the communication system.

Background technology

The IEEE802.15.4 standard definition physical layer and two standards of media access control layer of low-speed wireless individual domain network (LR-WPAN).The characteristics of IEEE 802.15.4 low rate, low-power consumption and short-distance transmission make it be fit to be applied to the wireless sensor network field.IEEE 802.15.4 physical layer specifies two frequency ranges, i.e. 2.4GHz frequency range and 868/915MHz frequency range.In the 2.4GHz of global general-use frequency range, regulation and stipulation employing O-QPSK modulation scheme and direct sequence spread spectrum technology.

Because the O-QPSK modulation scheme that the IEEE802.15.4 standard adopts is the O-QPSK modulation scheme of band half-sine pulse shaping, so this modulation scheme is equivalent to minimum shift keying (MSK) modulation, can adopt the method for MSK differential detection and demodulation and certain encoding process to realize demodulation to the IEEE802.15.4 modulated signal.

Frequency drift is to drop on frequency place outside the expected frequence owing to the local oscillator of transmitter and receiver (LO) can't reach signal center frequency that desirable nominal frequency obtains the receiver down-conversion.Frequency drift has a strong impact on demodulation performance, therefore need compensate it.

Frequency-drift compensation needs two steps usually: at first, the centre frequency of estimating received signal.Want the centre frequency of estimating received signal to need frequency estimator, as Kay frequency estimator and Meyr frequency estimator, they all need to carry out complex multiplication, phase demodulation and operation such as add up.After estimating the centre frequency of received signal, need to compare, go to adjust the frequency of local oscillator according to this difference then or vector signal is rotated and make it get back to the position that does not have frequency drift with expected frequence.The frequency of adjusting local oscillator need produce the local carrier of frequency adjustable with Direct Digital Synthesizer (DDS), and carry out vector rotation then needs to carry out the complex multiplication operation or realize with cordic algorithm.

The utility model content

The technical problems to be solved in the utility model is to propose a kind of MSK differential detection and demodulation circuit medium frequency drift compensation device at the defective that prior art exists.

The utility model MSK differential detection and demodulation circuit medium frequency drift compensation device, it is characterized in that comprising accumulator, time schedule controller, the constant divider, the constant subtracter, offset register and subtracter, wherein the asynchronous reset end of time schedule controller respectively with the asynchronous reset end of accumulator, the asynchronous reset end of offset register connects, the clock signal terminal of time schedule controller respectively with the clock signal terminal of accumulator, the clock signal terminal of offset register connects, the input that enables of the enable signal termination accumulator that adds up of time schedule controller, the latch signal termination offset register of time schedule controller enable input, the data input pin of accumulator is connected with the data positive input terminal that connects subtracter, connect the positive input terminal of constant subtracter behind the output serial connection constant divider of accumulator, connect the data minus input of subtracter after the output serial connection offset register of constant subtracter.

The utility model has utilized the characteristics of MSK differential detection and demodulation method, has simplified the frequency-drift compensation device, has saved the Frequency Estimation device, only needs an accumulator, a subtracter and some simple control logics just can realize frequency-drift compensation.Constant subtracter and constant divider can be realized by simple logical circuit, save very much hardware resource.

Description of drawings

Fig. 1 is the structural representation of the utility model frequency compensator;

Fig. 2 is the flow chart of the utility model frequency compensation method.

Embodiment

As shown in Figure 1.The utility model MSK differential detection and demodulation circuit medium frequency drift compensation device, it is characterized in that comprising accumulator, time schedule controller, the constant divider, the constant subtracter, offset register and subtracter, wherein the asynchronous reset end of time schedule controller respectively with the asynchronous reset end of accumulator, the asynchronous reset end of offset register connects, the clock signal terminal of time schedule controller respectively with the clock signal terminal of accumulator, the clock signal terminal of offset register connects, the input that enables of the enable signal termination accumulator that adds up of time schedule controller, the latch signal termination offset register of time schedule controller enable input, the data input pin of accumulator and the data positive input terminal that connects subtracter, the data input pin of this device connects, connect the positive input terminal of constant subtracter behind the output serial connection constant divider of accumulator, connect the data minus input of subtracter after the output serial connection offset register of constant subtracter.

IEEE 802.15.4O-QPSK baseband signal can be expressed as:

X (t)=I (t)+jQ (t), wherein I (t), Q (t) they are that j is the imaginary part of symbol through the baseband signal of half-sine pulse shaping, t is indication cycle's time;

Signal amplitude is made as 1, and modulated signal can be expressed as:

s(t)＝I(t)cos(2πf _ct)-Q(t)sin(2πf _ct)

Make arg that (X (t))=θ (t) then

I(t)＝cosθ(t)，Q(t)＝sinθ(t)

s(t)＝cosθ(t)cos(2πf _ct)-sinθ(t)sin(2πf _ct)

＝cos(2πf _ct+θ(t))

And $\mathrm{\θ}\left(t\right)=\arctan \left(\frac{Q\left(t\right)}{I\left(t\right)}\right)=\arctan \left(\frac{\sin \mathrm{\θ}\left(t\right)}{\cos \mathrm{\θ}\left(t\right)}\right)$

As shown in Figure 2.Additive phase θ (t) has comprised the information of baseband signal, and MSK differential detection and demodulation method is extracted θ (t) and realized demodulation from received signal.Its process is as follows: at first detect the additive phase θ (t) of received signal with respect to carrier wave, then θ (t) is postponed a code-element period T and obtain θ (t-T), use θ (t) to deduct θ (t-T) then and obtain differential phase θ (t)-θ (t-T), can obtain demodulating data by the symbol of adjudicating differential phase θ (t)-θ (t-T).

When there being frequency drift, received signal can be expressed as:

r(t)＝cos(2πf _ct+θ(t)+Δωt)

＝cos(θ(t)+Δωt)·cos(2πf _ct)-sin(θ(t)+Δωt)·sin(2πf _ct)

Wherein Δ ω is the angular frequency drift value;

Make I (t)=cos (θ (t)+Δ ω t), Q (t)=sin (θ (t)+Δ ω t):

r(t)＝I(t)cos(2πf _ct)-Q(t)sin(2πf _ct)

So the detected additive phase of receiving terminal should be:

${\mathrm{\θ}}^{\′}\left(t\right)=\arctan \left(\frac{Q\left(t\right)}{I\left(t\right)}\right)=\arctan \left(\frac{\sin (\mathrm{\θ}\left(t\right)+\mathrm{\Δ\ωt})}{\cos (\mathrm{\θ}\left(t\right)+\mathrm{\Δ\ωt})}\right)=\mathrm{\θ}\left(t\right)+\mathrm{\Δ\ωt}$

Therefore have: θ ' (t)-θ ' (t-T)=(θ (t)+Δ ω t)-(θ (t-T)+Δ ω (t-T))=θ (t)-θ (t-T)+Δ ω T

Can find that from top analysis frequency drift is to make differential phase θ (t)-θ (t-T) translation Δ ω T phase place up or down to the influence of MSK differential detection and demodulation.IEEE 802.15.4 physical layer protocol data unit (PHY protocoldata unit, PPDU) 8 symbol0 are arranged as lead code, use the several symbol0 in front to finish energy measuring and AGC etc., remaining lead code is calculated the average of the differential phase of N (N is the positive integer less than 8) individual symbol time in the time, deduct the differential phase average of these lead codes when not having frequency drift then with this average, just can be in the hope of Δ ω T, the differential phase θ ' that makes useful data backward then (t)-θ ' (t-T) deducts Δ ω T phase place, just can obtain the differential phase after overcompensation, thereby compensated the differential phase skew that frequency drift causes, whole flow process as shown in Figure 2.Realize the device of this flow process, promptly frequency compensator as shown in Figure 1.In_resetn is the effective asynchronous reset signal of low level, and in_clk is a clock signal, and in_enable is the enable signal of frequency-drift compensation device, frequency-drift compensation device operate as normal when in_enable is high level, otherwise do not work.In_fcomp_on is the enabling signal of frequency-drift compensation, when in_fcomp_on is a high level, time schedule controller control add_en signal is put height, the accumulator differential phase in_data that begins to add up, counter in the time schedule controller begins counting simultaneously, when rolling counters forward to predetermined numerical value, counter stops counting, time schedule controller control add_en puts low, and accumulator stops the differential phase that adds up.The result of accumulator output be exactly added up N symbol time the lead code differential phase with, this result is sent to the constant divider, the constant divider obtains the output result of accumulator the mean value of lead code differential phase divided by accumulative frequency, this mean value is sent to the constant subtracter, the constant subtracter deducts the lead code differential phase standard average that no frequency drift noiseless influences with this mean value, obtains the side-play amount of received signal differential phase.This side-play amount is sent to offset register, when latch_en signal when being high, the side-play amount that offset register latchs input compensates in order to the differential phase to later arrival, and this compensation process is by subtracter the output that in_data deducts offset register to be obtained the out_data realization.The latch_en signal is controlled by time schedule controller.

Claims (1)

1. MSK differential detection and demodulation circuit medium frequency drift compensation device, it is characterized in that comprising accumulator, time schedule controller, the constant divider, the constant subtracter, offset register and subtracter, wherein the asynchronous reset end of time schedule controller respectively with the asynchronous reset end of accumulator, the asynchronous reset end of offset register connects, the clock signal terminal of time schedule controller respectively with the clock signal terminal of accumulator, the clock signal terminal of offset register connects, the input that enables of the enable signal termination accumulator that adds up of time schedule controller, the latch signal termination offset register of time schedule controller enable input, the data input pin of accumulator is connected with the data positive input terminal that connects subtracter, connect the positive input terminal of constant subtracter behind the output serial connection constant divider of accumulator, connect the data minus input of subtracter after the output serial connection offset register of constant subtracter.

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