CN201332394Y - Multimode frequency division device - Google Patents
Multimode frequency division device Download PDFInfo
- Publication number
- CN201332394Y CN201332394Y CN 200820124137 CN200820124137U CN201332394Y CN 201332394 Y CN201332394 Y CN 201332394Y CN 200820124137 CN200820124137 CN 200820124137 CN 200820124137 U CN200820124137 U CN 200820124137U CN 201332394 Y CN201332394 Y CN 201332394Y
- Authority
- CN
- China
- Prior art keywords
- control signal
- frequency divider
- dividing ratio
- frequency
- ratio control
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Images
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
The utility model provides a multimode frequency division device used for extending the frequency division range of a multimode frequency divider in a fraction phase-locked loop, which comprises the multimode frequency divider (302) and a circuit module (304) used for extending the frequency division range. The circuit module comprises a first selection control signal generator (3042), a first selector (3044), a second selection control signal generator (3046) and a second selector (3048), wherein the first selection control signal generator (3042) is used for comparing an nth stage output signal with an (n-1)th stage output signal of the frequency divider, and generating a first selection control signal according to the comparison result and a frequency dividing ratio control signal; the first selector (3044) is used for selecting and outputting the nth stage output signal or the reversed signal of the multimode frequency divider according to the first selection control signal; the second selection control signal generator (3046) is used for generating a second selection control signal according to the (n-1)th stage output signal of the multimode frequency divider and the frequency dividing ratio control signal; and the second selector (3048) is used for selecting and outputting the (n-1)th stage output signal and a signal output by the first selector according to the second selection control signal.
Description
Technical field
The utility model relates to fractional phase locked loop, relates in particular to a kind of multimode frequency divider that is used for expanding fractional phase locked loop multi-modulus frequency divider frequency division scope.
Background technology
Phase-locked loop can be divided into integral frequency divisioil phase-locked loop and fractional-n phase-locked loop two big classes by the loop divider type.Compare with the integral frequency divisioil phase-locked loop, fractional-n phase-locked loop has the advantage that lock speed is fast, the frequency synthesis precision is high and can adopt higher reference frequency, thereby has obtained application more and more widely in communication transceiver.
Traditional fractional-n phase-locked loop comprises as shown in Figure 1: multi-modulus frequency divider (MMD); Reference frequency source (Reference) is used to produce the basic comparison frequency of phase-locked loop; Voltage controlled oscillator (VCO) is used for output frequency and is the N signal of (N can be integer, also can be mark) doubly of the output frequency of reference source; Phase frequency detector (PFD) is used for the phase difference that comparison reference frequency and frequency divider feed back output frequency; Charge pump (CP) and loop filtering circuit (LPF) are used for the output frequency of voltage controlled oscillator is carried out negative feedback control to produce required output frequency; And mark modulator (Modulator), be used to control multi-modulus frequency divider to produce required fraction division ratio.
(Multi-Modulus-Divider MMD) as shown in Figure 2, is formed by the 3 frequency divider cascades of multistage mould 2 moulds traditional multi-modulus frequency divider.In cycle, each mould 2 moulds 3 frequency divider can only be done mould 2 frequency divisions or do one-off pattern 3 frequency divisions under the control of control bit at a frequency division, and all the other times are done mould 2 frequency divisions, thereby reach 2
nTo 2
(n+1)The purpose of continuous frequency division in-1 scope.Wherein, n is the progression of mould 2 moulds 3 frequency dividers.With the frequency divider of n=5 for instance, when wherein all moulds 2 moulds 3 frequency dividers when a frequency division all only removes 2 in the cycle, total frequency dividing ratio is 32.Remove 3 and do in the cycle once at a frequency division when first order mould 2 moulds 3 frequency dividers, and all do in all the other times when removing 2 frequency divisions, total frequency dividing ratio is 32+1=33.Similarly, this frequency divider externally effect of control bit realizes 32 to 63 down, that is, and and 2
5To 2
(5+1)-1 frequency dividing ratio.
Mark modulator commonly used is generally ∑-Δ structure, and for reducing spuious and improving the frequency division precision, the frequency dividing ratio that can control multi-modulus frequency divider when work is usually switched in the larger context fast.For example, when the target frequency dividing ratio was 55.6, the mark modulator can be controlled multi-modulus frequency divider and switch fast on 52,53,54,55,56,57,58,59 and 60 several frequency divisions, was 55.6 effect thereby reach relative long period frequency dividing ratio.
Yet there is a problem in existing frequency divider on a large scale, promptly when required frequency dividing ratio close 2
nThe time, the output of existing multi-modulus frequency divider by the output signal of (n-1) level to moment that the output signal of n level is switched, because the output signal frequency of (n-1) level output is the twice of the output signal frequency of n level output, so the output signal of n level output might be in high level and also might be in low level after switching, if the level that switches after preceding and the switching is inconsistent, then the output at frequency divider can produce an incorrect impulse waveform, the frequency dividing ratio mistake in first cycle after causing switching.For example, in the frequency division scope is 32 to 127 frequency divider, when required frequency dividing ratio near 2
6,, the mark modulation crosses over 2 back and forth at promptly 64 o'clock because can controlling the frequency dividing ratio of frequency divider
6Promptly 64, cause the output of frequency divider between the 5th grade and the 6th grade, to be switched fast, but might be in high level and also might be in the low level place owing to switch the 6th grade of moment of the 6th grade from the 5th grade, and the 5th grade level state is definite controlled, as the inconsistent phenomenon that will cause occurring the frequency division mistake of level state before and after switching.Though should mistake just first cycle after output stage is switched occur once, for fractional divider, remain unacceptable, because near 2
nFrequency dividing ratio, the frequency divider output can switch repeatedly fast at n level and (n+1) inter-stage.
Control by the designer to the opportunity that the n inter-stage switches by (n-1) level, that is to say the output level before switching and determine the opportunity of switching, and switch the back level state uncertain be the basic reason that causes switching the frequency dividing ratio mistake in first cycle of back.
If can not address this problem then unacceptable deviation can appear in final frequency dividing ratio.This defective in some applications can be by selecting different reference frequencies for use, partly solve to avoid the frequency divider output to switch at two inter-stages, but such one is the compatibility that has limited system, the 2nd, and this method is always ineffective, so this solution is in a lot of the application and be not suitable for.
The utility model content
The utility model aims to provide the multimode frequency divider of the frequency dividing ratio Problem-Error in first cycle that is used to solve multi-modulus frequency divider after the uncertain switching that causes of switching the back level state between (n-1) level and the n level.
According to an aspect of the present utility model, a kind of multimode frequency divider that is used for expanding fractional phase locked loop multi-modulus frequency divider frequency division scope is provided, comprise multi-modulus frequency divider, also comprise the circuit module that is used to expand the frequency division scope, this circuit module comprises: first selects the control signal generator, be used for the n level output signal of multi-modulus frequency divider and (n-1) level output signal are compared, and according to comparative result with produce first from the frequency dividing ratio control signal of outside and select control signal; First selector is used for selecting control signal to select to export the inversion signal of the n level output signal or the n level output signal of multi-modulus frequency divider according to first; Second selects the control signal generator, is used for producing the second selection control signal according to (n-1) the level output signal and the frequency dividing ratio control signal of multi-modulus frequency divider; And second selector, be used for selecting control signal to select to export (n-1) level output signal of multi-modulus frequency divider or the signal of exporting by first selector according to second.
Wherein, first selects the control signal generator to comprise: first comparator is used for the n level output signal of multi-modulus frequency divider and (n-1) level output signal are compared and export comparative result to first sampler; And first sampler, trigger by the frequency dividing ratio control signal, be used for the comparative result of first comparator is sampled, and the comparative result after will sample provides to first selector as the first selection signal.
Preferably, first comparator is a NOR gate circuit.
Preferably, first sampler is a d type flip flop.
Wherein, second selects the control signal generator to comprise: second sampler, inversion signal by (n-1) of multi-modulus frequency divider level output signal triggers, and be used for the frequency dividing ratio control signal is sampled, and the frequency dividing ratio control signal after will sampling exports the exclusive disjunction unit to; Delay cell is used to postpone the frequency dividing ratio control signal, and the frequency dividing ratio control signal after will postponing outputs to the exclusive disjunction unit; And the exclusive disjunction unit, be used for carrying out exclusive disjunction, and select control signal to export second selector to as second operation result by the frequency dividing ratio control signal of second sampler output with by the frequency dividing ratio control signal of delay cell output.
Preferably, second sampler is a d type flip flop.
Preferably, the exclusive disjunction unit is made up of the OR-NOT circuit and first inverter.
Wherein, delay cell comprises: second inverter, be used for carrying out anti-phasely from the frequency dividing ratio control signal of outside, and and anti-phase back frequency dividing ratio control signal is exported to an end of capacitor; Capacitor is used for the frequency dividing ratio control signal after second inverter is anti-phase is postponed; And the 3rd inverter, be used for the frequency dividing ratio control signal after postponing through capacitor is carried out anti-phase and selected control signal to export second selector to as second.
Utilize the technical solution of the utility model, level state to outputs at different levels before switching judges, and correctly controls switching time according to judged result, therefore, in the time of in being applied to the fractional frequency phase-locked loop, avoided the frequency division mistake under the specific frequency dividing ratio situation.
Description of drawings
Accompanying drawing described herein is used to provide further understanding of the present utility model, constitutes the application's a part, and illustrative examples of the present utility model and explanation thereof are used to explain the utility model, do not constitute improper qualification of the present utility model.In the accompanying drawings:
Fig. 1 is the block diagram of traditional fractional-n phase-locked loop circuit;
Fig. 2 is the schematic block circuit diagram of traditional multi-modulus frequency divider;
Fig. 3 is the block diagram of multimode frequency divider that is used for expanding fractional phase locked loop multi-modulus frequency divider frequency division scope according to the utility model embodiment;
Fig. 4 is the circuit diagram according to the multimode frequency divider of the utility model embodiment; And
Fig. 5 is the simulation waveform figure of the pulse signal of the main node in the circuit diagram shown in Figure 4.
Embodiment
Below in conjunction with accompanying drawing preferred embodiment of the present utility model is described, should be appreciated that preferred embodiment described herein only is used for description and interpretation the utility model, and be not used in qualification the utility model.In full, same reference numerals is represented same apparatus.
Fig. 3 is the block diagram of multimode frequency divider 300 that is used for expanding fractional phase locked loop multi-modulus frequency divider frequency division scope according to the utility model embodiment.
With reference to Fig. 3, the multimode frequency divider 300 that is used for expanding fractional phase locked loop multi-modulus frequency divider frequency division scope according to the utility model embodiment comprises multi-modulus frequency divider 302, also comprise the circuit module 304 that is used to expand the frequency division scope, this circuit module 304 comprises: first selects control signal generator 3042, be used for the n level output signal of multi-modulus frequency divider 302 and (n-1) level output signal are compared, and according to comparative result with produce first from the frequency dividing ratio control signal of outside and select control signal; First selector 3044 is used for selecting control signal to select to export the inversion signal of the n level output signal or the n level output signal of multi-modulus frequency divider 302 according to first; Second selects control signal generator 3046, is used for producing the second selection control signal according to (n-1) the level output signal and the frequency dividing ratio control signal of multi-modulus frequency divider 302; And second selector 3048, be used for selecting control signal to select to export (n-1) level output signal of multi-modulus frequency divider 302 or the signal of exporting by first selector 3044 according to second.
First selects control signal generator 3042 to comprise: first comparator is used for the n level output signal of multi-modulus frequency divider 302 and (n-1) level output signal are compared and export comparative result to first sampler; And first sampler, trigger by the frequency dividing ratio control signal, be used for the comparative result of first comparator is sampled, and the comparative result after will sample provides to first selector 3044 as the first selection signal.
Preferably, first comparator is a NOR gate circuit.
Preferably, first sampler is a d type flip flop.
Second selects control signal generator 3046 to comprise: second sampler, inversion signal by (n-1) of multi-modulus frequency divider 302 level output signal triggers, be used for the frequency dividing ratio control signal is sampled, and the frequency dividing ratio control signal after will sampling exports the exclusive disjunction unit to; Delay cell is used to postpone the frequency dividing ratio control signal, and the frequency dividing ratio control signal after will postponing outputs to the exclusive disjunction unit; And the exclusive disjunction unit, be used for carrying out exclusive disjunction, and select control signal to export second selector 3048 to as second operation result by the frequency dividing ratio control signal of second sampler output with by the frequency dividing ratio control signal of delay cell output.
Preferably, second sampler is a d type flip flop.
Delay cell comprises: second inverter, be used for carrying out anti-phasely from the frequency dividing ratio control signal of outside, and and anti-phase back frequency dividing ratio control signal is exported to an end of capacitor; Capacitor is used for the frequency dividing ratio control signal after second inverter is anti-phase is postponed; And the 3rd inverter, be used for the frequency dividing ratio control signal after postponing through capacitor is carried out anti-phase and selected control signal to export second selector 3048 to as second.
Fig. 4 is the circuit diagram according to the multimode frequency divider 300 of the utility model embodiment.
With reference to Fig. 4, multimode frequency divider 300 according to the utility model first embodiment comprises multi-modulus frequency divider 302, also comprise the circuit module 304 that is used to expand the frequency division scope, this circuit module 304 comprises: first selects control signal generator 3042, first selector 3044, second to select control signal generator 3046 and second selector 3048.
In the present embodiment, switching time is set at before the rising edge of frequency dividing ratio control signal Dn+1 arrives and finishes.
Can finish the function of the n level output of multi-modulus frequency divider 302 being judged and selected correct phase by the module that inverter 402, first selector 3044, XOR gate 404 and first d type flip flop 408 are formed.Particularly, switching according to the setting of front is to finish before the rising edge of (n-1) level arrives, so need before this to judge earlier whether the n level of multi-modulus frequency divider 302 this moment and the output signal of (n-1) level are in identical level state, selecting side as identical then first selector 3044 is a logical zero, and selecting Qn is the output signal of frequency divider; As difference then the selecting side of first selector 3044 be logical one, selecting the inversion signal of Qn is the output signal of frequency divider.Wherein, XOR gate 404 is used to finish level ratio function; The clock end of first d type flip flop 408 links to each other with frequency dividing ratio control signal Dn+1, be used for when the rising edge as Dn+1 arrives, the comparative result of XOR gate 408 being done once sampling, and keep this sampled result to switch up to the selection of doing once output when guaranteeing to make 3044 of first selectors rising edge that arrives of the rising edge of next Dn+1 at Dn+1, effectively prevent misoperation; Inverter 402 provides the inversion signal of Qn.
The module that second selector 3048, inverter 418, second d type flip flop 420, NOR gate 410, inverter 416, inverter 414, inverter 412 and electric capacity 422 are formed is used to produce the control signal of second selector 3048.Particularly, when the rising edge of frequency dividing ratio control signal Dn+1 arrives, can obtain through the signal of suitable delay as one of input of NOR gate 410 through inverter 416, electric capacity 422 and inverter 414.When the trailing edge of frequency dividing ratio control signal Dn+1 arrives, through another input behind Qn-1 synchronous of second d type flip flop 420 as NOR gate 410.The output of NOR gate 410 is connected with the control end of second selector 3048 after inverter 412 is anti-phase.The selection control signal of the second selector 3048 of Chan Shenging can avoid the output of multi-modulus frequency divider 302 pulse of mistake to occur because of conversion opportunity is improper when the rising and falling edges of Dn+1 arrives like this.
The value size of electric capacity 422 needs to take all factors into consideration the back setting according to the frequency of input signal and frequency dividing ratio, enough delays should be arranged in requirement so that second selector 3048 is finished at first selector 3044 selects once more to switch after select switching, again can not be too big and the rising edge that make the selection of second selector 3048 switch in Qn then still can not be finished and the mistake that causes exporting.
Fig. 5 is the simulation waveform figure of the pulse signal of the main node in the circuit diagram shown in Figure 4.
As shown in Figure 5, switch to Q4B in A point moment output waveform by Q3, constantly then switch back Q3 from Q4B at the B point, output can both guarantee that after switching frequency division is correct.
By above embodiment, the utility model has been realized following beneficial effect: the level state to outputs at different levels before switching is judged, and correctly control switching time according to judged result, therefore, in the time of in being applied to the fractional frequency phase-locked loop, avoided the frequency division mistake under the specific frequency dividing ratio situation.
The above is a preferred embodiment of the present utility model only, is not limited to the utility model, and for a person skilled in the art, the utility model can have various changes and variation.All within spirit of the present utility model and principle, any modification of being done, be equal to replacement, improvement etc., all should be included within the protection range of the present utility model.
Claims (8)
1. a multimode frequency divider that is used for expanding fractional phase locked loop multi-modulus frequency divider frequency division scope comprises multi-modulus frequency divider, it is characterized in that, also comprise the circuit module that is used to expand the frequency division scope, described circuit module comprises:
First selects the control signal generator, is used for n level output signal and the n-1 level output signal of described multi-modulus frequency divider are compared, and produces the first selection control signal according to comparative result with from the frequency dividing ratio control signal of outside;
First selector is used for selecting control signal to select to export the inversion signal of the n level output signal or the described n level output signal of described multi-modulus frequency divider according to described first;
Second selects the control signal generator, is used for producing the second selection control signal according to the n-1 level output signal and the described frequency dividing ratio control signal of described multi-modulus frequency divider; And
Second selector is used for selecting control signal to select to export the n-1 level output signal of described multi-modulus frequency divider or the signal of being exported by described first selector according to described second.
2. multimode frequency divider according to claim 1 is characterized in that, described first selects the control signal generator to comprise:
First comparator is used for the n level output signal and the n-1 level output signal of described multi-modulus frequency divider are compared and comparative result is exported; And
First sampler is triggered by described frequency dividing ratio control signal, be used for the described comparative result of described first comparator is sampled, and the described comparative result after will sampling selects signal to provide to described first selector as described first.
3. multimode frequency divider according to claim 2 is characterized in that, described first comparator is a NOR gate circuit.
4. multimode frequency divider according to claim 2 is characterized in that, described first sampler is a d type flip flop.
5. multimode frequency divider according to claim 1 is characterized in that, described second selects the control signal generator to comprise:
Second sampler is triggered by the inversion signal of the n-1 level output signal of described multi-modulus frequency divider, be used for described frequency dividing ratio control signal is sampled, and the described frequency dividing ratio control signal after will sampling exports the exclusive disjunction unit to;
Delay cell is used to postpone described frequency dividing ratio control signal, and the frequency dividing ratio control signal after will postponing outputs to described exclusive disjunction unit; And
Described exclusive disjunction unit, be used for carrying out exclusive disjunction, and select control signal to export described second selector to as described second operation result by the described frequency dividing ratio control signal of described second sampler output with by the described frequency dividing ratio control signal of described delay cell output.
6. multimode frequency divider according to claim 5 is characterized in that, described second sampler is a d type flip flop.
7. multimode frequency divider according to claim 5 is characterized in that, described exclusive disjunction unit is made up of the OR-NOT circuit and first inverter.
8. multimode frequency divider according to claim 5 is characterized in that, described delay cell comprises:
Second inverter is used for carrying out from the described frequency dividing ratio control signal of outside anti-phasely, and the described frequency dividing ratio control signal in anti-phase back is exported to an end of capacitor;
Described capacitor is used for the frequency dividing ratio control signal after described second inverter is anti-phase is postponed; And
The 3rd inverter is used for the described frequency dividing ratio control signal after postponing through described capacitor is carried out anti-phase and selected control signal to export described second selector to as described second.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200820124137 CN201332394Y (en) | 2008-11-25 | 2008-11-25 | Multimode frequency division device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200820124137 CN201332394Y (en) | 2008-11-25 | 2008-11-25 | Multimode frequency division device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN201332394Y true CN201332394Y (en) | 2009-10-21 |
Family
ID=41225779
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200820124137 Expired - Lifetime CN201332394Y (en) | 2008-11-25 | 2008-11-25 | Multimode frequency division device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN201332394Y (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101409555B (en) * | 2008-11-25 | 2011-01-19 | 北京朗波芯微技术有限公司 | Multi-mode frequency-dividing apparatus and method for expanding frequency-dividing range of multi-mode frequency divider |
-
2008
- 2008-11-25 CN CN 200820124137 patent/CN201332394Y/en not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101409555B (en) * | 2008-11-25 | 2011-01-19 | 北京朗波芯微技术有限公司 | Multi-mode frequency-dividing apparatus and method for expanding frequency-dividing range of multi-mode frequency divider |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101599763B (en) | Timing error detection device and method thereof | |
| CN101419483B (en) | Clock generator based on phase-locked loop and clock generating method | |
| CN101409555B (en) | Multi-mode frequency-dividing apparatus and method for expanding frequency-dividing range of multi-mode frequency divider | |
| CN207720116U (en) | A kind of digital delay phase-locked loop of quick lock in | |
| CN103840830A (en) | Time-to-digit converter and digital phase-locked loop | |
| CN103312319B (en) | Be applied to the spurious reduction phase frequency detector circuit in integer-N PLL | |
| CN104579320B (en) | Clock delay method, apparatus, delay phase-locked loop and digital dock administrative unit | |
| CN102158221B (en) | Phase-locked loop and fast lockign apparatus thereof | |
| CN101371439A (en) | Phase comparison circuit and PLL synthesizer using the same | |
| CN104753499A (en) | Duty ratio calibrating circuit | |
| CN101588177A (en) | Digital locking indictor, phase lock loop frequency synthesizer and wireless transceiver | |
| CN101667830B (en) | Phase-locked loop frequency synthesizer | |
| CN105634443A (en) | Clock generating device and fractional frequency divider thereof | |
| CN101465645A (en) | Decimals/integer frequency divider | |
| CN101527564B (en) | Fractional-neuronal frequency divider and method thereof | |
| US9602115B1 (en) | Method and apparatus for multi-rate clock generation | |
| CN201332394Y (en) | Multimode frequency division device | |
| CN100417024C (en) | Lock phase loop of low stable error and its correcting circuif | |
| CN113037251A (en) | Clock management device, clock frequency division module and system on chip | |
| CN101309082B (en) | Phase shifting multi-mode frequency dividing method based on clock frequency control and frequency divider | |
| CN214045599U (en) | N-time pulse width expansion circuit applied to phase-locked loop and phase-locked loop thereof | |
| CN113114237B (en) | Loop system capable of realizing rapid frequency locking | |
| CN213906646U (en) | N-fold pulse width expansion circuit and pulse width expanded phase-locked loop system | |
| CN103780257B (en) | ring oscillator circuit | |
| CN1099763C (en) | Frequency synthesizer |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| AV01 | Patent right actively abandoned |
Granted publication date: 20091021 Effective date of abandoning: 20081125 |