CN201312285Y - D-type audio power amplifier - Google Patents
D-type audio power amplifier Download PDFInfo
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- CN201312285Y CN201312285Y CN 200820122402 CN200820122402U CN201312285Y CN 201312285 Y CN201312285 Y CN 201312285Y CN 200820122402 CN200820122402 CN 200820122402 CN 200820122402 U CN200820122402 U CN 200820122402U CN 201312285 Y CN201312285 Y CN 201312285Y
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/30—Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters
- H03F1/305—Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters in case of switching on or off of a power supply
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Abstract
The utility model provides a D-type audio power amplifier which comprises a preamplifier, an integrator, a first comparator, a second comparator, a switching transistor group, a first output end and a second output end, and also comprises a first pull-down circuit connected between the first output end and power earthing, a second pull-down circuit connected between the second output end and the power earthing, and a time-sequence control circuit, wherein the time-sequence control circuit controls the preamplifier, the integrator, the first comparator, the second comparator, the first pull-down circuit and the second pull-down circuit to eliminate noise generated by switching the D-type audio power amplifier. The utility model controls the D-type audio power amplifier by the time-sequence control circuit, can avoid the defects brought by using a capacitor to inhibit CLICK-POP noise in the prior art and saves the chip area.
Description
Technical field
The utility model relates to electronic equipment manufacturing technology field, particularly a kind of D genus audio power amplifier.
Background technology
Along with the continuous development of electronic technology, people require more and more higher to the acoustic characteristic of portable type electronic products such as mobile phone, MP3.Because the D genus audio power amplifier can provide under the situation of low distortion up near 90% efficient, so it has obtained using widely in portable type electronic products such as mobile phone, MP3.The principle of this D genus audio power amplifier is: by the audio signal of input is compared with carrier signal; Produce the pulse width modulated waveform (PWM waveform) that includes input audio signal information then; Drive loud speaker by power switch pipe again, audio signal is reduced by loud speaker; Perhaps after output, the audio signal reduction is driven later loud speaker again by filter.
But when the D class audio amplifier enters switching on and shutting down; the D class audio amplifier produces switch/switching noise (CLICK_POP noise) through regular meeting; yet the user of portable type electronic products such as mobile phone, MP3 or personal digital assistant does not wish to hear that these disturb people's noise, therefore must remove the CLICK_POP noise that produces when switching on and shutting down.As shown in Figure 1, be D genus audio power amplifier structural representation in the prior art, this D genus audio power amplifier comprises preamplifier 101, integrator 102 and first comparator 103 and second comparator 104 that links to each other successively, and resistance R 1-R8, capacitor C 1-C2 and H bridge power switch transistor group 105 (Q5-Q8), its annexation is as shown in Figure 1.Below will simply introduce the various piece in the D class audio amplifier, wherein, preamplifier comprises fully differential operational amplifier, input resistance R1 and R2, feedback resistance R3 and R4, be used for the audio signal of output is amplified, integrator, first comparator 103 and second comparator 104 etc. of itself and back are complementary; Integrator 102 is used for integral processing is done in the output of preamplifier 101 and feedback signal, and it can be made of differential amplifier and integrating capacitor C1 and C2 and input resistance R5 and R6 and integrating resistor R7 and R8; First comparator 103 and second comparator 104, can be PWM (Plus Width Modulator, pulse-width modulator) comparator is used for and will be compared with triangular wave by the audio signal of integrator input, thereby produces the pulse width modulated waveform that has comprised the input audio-frequency information; H bridge power switch transistor Q5-Qg is by comparator drives, and generation can drive the pulse width modulated waveform of loud speaker.
At present, the technology that suppresses the CLICK_POP noise of D genus audio power amplifier in the prior art mainly is by a bigger electric capacity, there is certain delay the time that D genus audio power amplifier chip internal module is started working with respect to the time of electric power starting, when chip is closed, make the voltage of output slowly be changed to fixed level by pull down resistor more then, thereby reach the purpose that suppresses the CLICK_POP noise.As shown in Figure 2, for being used for suppressing the circuit structure diagram of D genus audio power amplifier CLICK_POP noise in the prior art.When supply voltage VDD opens, begin capacitor C 301 is charged by control circuit supply voltage VDD; When the voltage on the capacitor C 301 surpassed another input VREF of comparator, the output level of comparator will be undergone mutation, and makes chip begin to carry out work; When power-off, the voltage signal of output just makes it slowly change to a fixed level by pull down resistor R301 and R302.Just make chip in the moment of supply voltage opening and closing by capacitor C 301 and pull down resistor R301 and R302 like this, do not have very big current/voltage at output and change, thereby reached the purpose that suppresses the CLICK_POP noise.
From the explanation of above-mentioned solution as seen, the major defect that is used to suppress the circuit of CLICK_POP noise in the prior art is:
1, in the prior art because be to realize by a big electric capacity is charged time of delay,, then can waste very much chip area, the utilance of chip be reduced, and can cause the increase of chip power-consumption if electric capacity is arranged on chip internal.
If 2 electric capacity are arranged on chip exterior, then externally under the situation of power supply one direct power supply, the voltage on the electric capacity can surpass another input VREF of comparator all the time, if therefore powered-down not, and only open or close chip, just can't suppress the CLICK_POP noise effectively.
The utility model content
During the purpose of this utility model is intended to solve the problems of the technologies described above at least one particularly solves and relies on electric capacity to suppress the technical problem that the caused chip area of CLICK_POP noise increases, can't effectively suppress the CLICK_POP noise in the prior art.
For this reason, the utility model proposes a kind of D genus audio power amplifier, comprise: preamplifier, integrator, first comparator, second comparator, the switching transistor group, first output and second output, also comprise first pull-down circuit that is connected between described first output and the power supply ground, be connected second pull-down circuit between described second output and the power supply ground, and sequential control circuit, described sequential control circuit is controlled described preamplifier, described integrator, described first comparator, described second comparator, described first pull-down circuit and described second pull-down circuit are to eliminate the switch/switching noise of described D genus audio power amplifier.
The utility model is controlled the D genus audio power amplifier by sequential control circuit, not only can avoid prior art to use electric capacity to suppress the shortcoming that the CLICK_POP noise brings, saved chip area, and the time that can very accurate control need postpone, output signal is slowly changed, extraordinary effect is arranged for suppressing D genus audio power amplifier CLICK_POP noise.
Aspect that the utility model is additional and advantage part in the following description provide, and part will become obviously from the following description, or recognize by practice of the present utility model.
Description of drawings
Above-mentioned and/or additional aspect of the utility model and advantage are from obviously and easily understanding becoming the description of embodiment below in conjunction with accompanying drawing, wherein:
Fig. 1 is a D genus audio power amplifier structural representation in the prior art;
Fig. 2 is the circuit structure diagram that suppresses CLICK_POP noise in the D genus audio power amplifier in the prior art;
Fig. 3 is the structure chart of an embodiment D of the utility model genus audio power amplifier;
Sequential chart when Fig. 4 closes for an embodiment D of the utility model genus audio power amplifier chip;
Sequential chart when Fig. 5 is the unlatching of an embodiment D of the utility model genus audio power amplifier chip;
Fig. 6 is the structure chart of another embodiment D genus audio power amplifier of the present utility model.
Embodiment
Describe embodiment of the present utility model below in detail, the example of described embodiment is shown in the drawings, and wherein identical from start to finish or similar label is represented identical or similar elements or the element with identical or similar functions.Below by the embodiment that is described with reference to the drawings is exemplary, only is used to explain the utility model, and can not be interpreted as restriction of the present utility model.
The utility model mainly is by the timing control signal of sequential control circuit the state of D genus audio power amplifier to be controlled, make this D genus audio power amplifier when opening and closing, can avoid big voltage or current impulse to produce, thereby avoided shortcoming of the prior art, not only saved chip area, and the time that can very accurate control need postpone, output signal is slowly changed.Therefore the utility model has extraordinary effect for suppressing D genus audio power amplifier CLICK_POP noise.
As an embodiment of the present utility model, as shown in Figure 3, be the structure chart of an embodiment D of the utility model genus audio power amplifier.As can be seen from the figure, preamplifier 101, integrator 102, first comparator 103 and second comparator 104 in the clock signal control D genus audio power amplifier that produces by sequential control circuit, and first pull-down circuit 106 and second pull-down circuit 107 that link to each other respectively with the first output VO+ and the second output VO-.Particularly, in this embodiment, the output state of first clock signal of sequential control circuit control preamplifier 101 and integrator 102; The on off state of second clock signal control preamplifier 101, integrator 102; The 3rd clock signal is controlled first comparator 103, second comparator 104 and first pull-down circuit 106 and second pull-down circuit 107.By sequential control circuit in the utility model to preamplifier 101, integrator 102, first comparator 103, second comparator 104, and the control of first pull-down circuit 106 and second pull-down circuit 107, make this D genus audio power amplifier when opening and closing, avoid occurring bigger voltage or current impulse, thereby can suppress D genus audio power amplifier CLICK_POP noise effectively.
Need to prove; the utility model mainly is the above-mentioned D genus audio power amplifier structure that the utility model proposes; in said structure; sequential control circuit can produce ordered pair preamplifier 101 when multiple; integrator 102; first comparator 103; second comparator 104; and first pull-down circuit 106 and second pull-down circuit 107 control; first clock signal of above-mentioned its generation; second clock signal and the 3rd clock signal only are preferred embodiment of the present utility model; can change based on this scheme those of ordinary skills and multiple clock signal structure; for example at quantity or the above-mentioned clock signal and the preamplifier 101 of clock signal; integrator 102; first comparator 103; second comparator 104; and make the variation that does not break away from the main thought of the utility model on the annexation of first pull-down circuit 106 and second pull-down circuit 107 etc.; these similar variations all should be considered as being equal to replacement to of the present utility model, should be the utility model protection range and contain.
In a specific embodiment, the utility model proposes above-mentioned clock signal control preamplifier 101, integrator 102, first comparator, 103/ second comparator 104, and the control mode of first pull-down circuit 106 and second pull-down circuit 107.In Fig. 3, also include with preamplifier 101 in feedback resistance R3 and R4 first switching circuit and second switch circuit in parallel, first switching circuit is MOS switching tube Q1 in the figure, the second switch circuit is MOS switching tube Q2, but need to prove that above-mentioned MOS switching tube only is a kind of specific implementation of the present utility model, any active or passive device that can play on-off action also can be applicable in the utility model.Also have with integrator 102 in feedback capacity C1 and C2 the 3rd switching circuit (MOS switching tube Q3) and the 4th switching circuit (MOS switching tube Q4) in parallel, the switch of above-mentioned first clock signal by control first switching circuit, second switch circuit, the 3rd switching circuit and the 4th switching circuit is to control the output state of preamplifier 101 and integrator 102.After for example first clock signal is opened above-mentioned first switching circuit, second switch circuit, the 3rd switching circuit and the 4th switching circuit, can be with above-mentioned feedback resistance R3, R4 and feedback capacity C1, C2 short circuit, thereby make the output of preamplifier 101 and integrator 102 be stabilized on the common mode electrical level, will to form duty ratio be 50% square wave when this common mode electrical level and triangular wave are compared, thereby make the output of chip not have sound.
Wherein, for of the control of second clock signal, be to realize by the first enable signal end PD1 in control preamplifier 101 and the integrator 102 and the second enable signal end PD2 to preamplifier 101 and integrator 102 on off states.Be specially second clock signal and link to each other with the described second enable signal end PD2, when second clock signal is closed preamplifier 101 and integrator 102 during for high potential with the first enable signal end PD1.Certainly it will be appreciated by those skilled in the art that, also can close preamplifier 101 and integrator 102 during for electronegative potential at second clock signal.
For the 3rd clock signal, not only need to control the on off state of first comparator 103 and second comparator 104, also need to control the on off state of first pull-down circuit 106 and second pull-down circuit 107.Concrete implementation is that the 3rd clock signal links to each other with the 4th enable signal end PD4 with the 3rd enable signal end PD3 of first comparator 103 and second comparator 104, to control the on off state of first comparator 103 and second comparator 104.As an embodiment of the present utility model, first pull-down circuit 106 comprises the first pull down resistor R9 and the 5th switching circuit, second pull-down circuit 107 comprises the second pull down resistor R10 and the 6th switching circuit, wherein, the 5th switching circuit is MOS switching tube Q5 in the figure, the 6th switching circuit is MOS switching tube Q6, and the 3rd clock signal control MOS switching tube Q5 and MOS switching tube Q6 are to control the on off state of first pull-down circuit 106 and second pull-down circuit 107.
For clearer understanding can be arranged the said structure that the utility model proposes, below the order of first clock signal, second clock signal and the 3rd clock signal that will propose with embodiment of the utility model is that example is simply introduced the running of said structure.
When D class audio frequency power device chip is closed, its sequential chart as shown in Figure 4, postpone T1 the flip-flop transition of the flip-flop transition of second clock signal and the 3rd clock signal than first clock signal, wherein, T1 realizes by the delay circuit that resistance and electric capacity are formed.In this embodiment, the upset of second clock signal is for to overturn to high potential from electronegative potential, it will be apparent to those skilled in the art that from high potential also can realize the purpose of this utility model to the electronegative potential upset, and other circuit are made corresponding change and got final product certainly.As can be seen from Figure 4, when chip is closed, first clock signal of sequential control circuit output at first becomes high level by low level, thereby can make MOS switching tube Q1, Q2, Q3, the Q4 conducting, the output of preamplifier 101 and integrator 102 is stabilized on the common mode electrical level, and this common mode electrical level and triangular wave are compared and just formed duty ratio is 50% square wave, thereby makes the not output sound of chip.
Second clock signal and the 3rd clock signal postpone to overturn behind the T1 then, can close preamplifier 101 simultaneously like this, integrator 102, comparator 103 and 104, and while conducting MOS switching tube Q9 and Q10.Because the conducting of MOS switching tube, output VO+ and VO-will be pulled down to a fixed level by pull down resistor R9 and R10 respectively.In addition since signal from comparator 103,104 to VO+ and VO-have the delay of certain hour, therefore the output level after comparator 103 and 104 is closed is transferred to before VO+ and the VO-, and the output level of VO+ and VO-has been pulled down to fixed level by pull down resistor.From foregoing description as can be seen in the process that whole D class audio frequency power device chip is closed, the voltage and current of output does not have to take place very big sudden change, thereby also just can not produce very big CLICK_POP noise, thereby reach the purpose that in closing chip processes, suppresses the CLICK_POP noise.
When D class audio frequency power device chip is opened, its sequential chart as shown in Figure 5, the flip-flop transition of first clock signal is than postponing flip-flop transition of second clock signal T2, the flip-flop transition of the 3rd clock signal is than postponing flip-flop transition of first clock signal T3.When chip was opened, second clock signal of being exported by sequential control circuit at first became low level by high level, thereby made preamplifier 101 and integrator 102 beginning operate as normal.But because this moment, first clock signal still was a high level, i.e. MOS switching tube Q1, Q2, Q3, the whole conductings of Q4 are so preamplifier 101 and integrator 102 are output as a common mode electrical level.This moment, the 3rd clock signal also still was a high level, so the output of VO+ and VO-still is a fixed level, audio signal is not output still.
Then, through the T2 of delay all the time of certain hour, first clock signal begins to become low level by high level, thereby makes MOS switching tube Q1, Q2, and Q3, Q4 all turn-offs, and make that preamplifier 101 and integrator 102 can output audio signals this moment.But because this moment, the 3rd clock signal still was a high level, the output of output VO+ and VO-still is fixed level like this, does not promptly also have audio signal output.At last, through T3 time of delay, the 3rd clock signal becomes low level from high level, thereby makes comparator 103 and 104 beginning operate as normal, and MOS switching tube Q9 and Q10 are closed.This moment, VO+ and VO-began the PWM ripple that output packet contains audio-frequency information.Because the time delay for some time that the output time of audio signal is opened than chip, and modular circuit wherein divides sequencing to start working, and makes it have one section to wait for the stable time.So, do not have very big voltage and current sudden change at output VO+ and VO-, thereby just can not produce very big CLICK_POP noise yet.
Need to prove the sequential chart shown in above-mentioned Fig. 4 and Fig. 5 only for preferred implementation of the present utility model, be in order better to understand the utility model, and should not become for restriction of the present utility model.
As another embodiment of the present utility model, as shown in Figure 6, be the structure chart of another embodiment D genus audio power amplifier of the utility model.The first above-mentioned as can be seen from this figure switching circuit, second switch circuit, the 3rd switching circuit and the 4th switching circuit also can be formed by transmission gate (Q401-Q404), but also need increase inverter 401, by the first clock signal control transmission door Q401-Q404 after first clock signal and the negate to the first clock signal negate.
The utility model is controlled the D genus audio power amplifier by sequential control circuit, not only can avoid prior art to use electric capacity to suppress the shortcoming that the CLICK_POP noise brings, and has saved chip area; And the time that can very accurate control need postpone, output signal is slowly changed, for suppressing D genus audio power amplifier CLICK_POP noise extraordinary effect is arranged.
Although illustrated and described embodiment of the present utility model, for the ordinary skill in the art, be appreciated that under the situation that does not break away from principle of the present utility model and spirit and can carry out multiple variation, modification, replacement and modification that scope of the present utility model is by claims and be equal to and limit to these embodiment.
Claims (10)
1, a kind of D genus audio power amplifier comprises: preamplifier, integrator, first comparator, second comparator, switching transistor group, first output and second output, it is characterized in that, and also comprise:
First pull-down circuit, described first pull-down circuit are connected between described first output and the power supply ground;
Second pull-down circuit, described second pull-down circuit is connected between described second output and the power supply ground, and
Sequential control circuit, described sequential control circuit are controlled described preamplifier, described integrator, described first comparator, described second comparator, described first pull-down circuit and described second pull-down circuit to eliminate the switch/switching noise of described D genus audio power amplifier.
2, D genus audio power amplifier according to claim 1, it is characterized in that, described sequential control circuit links to each other with described integrator with described preamplifier, and send first clock signal of described preamplifier of control and described integrator output state to described preamplifier and described integrator, and second clock signal of the on off state of transmission described preamplifier of control and described integrator, described sequential control circuit also with described first comparator, described second comparator, described first pull-down circuit links to each other with described second pull-down circuit, and sends the 3rd clock signal of its on off state of control.
3, as D genus audio power amplifier as described in the claim 2, it is characterized in that, postpone T1 the flip-flop transition of first clock signal that described second clock signal that described sequential control circuit sends and the flip-flop transition of described the 3rd clock signal send than described sequential control circuit when power-off.
4, as D genus audio power amplifier as described in claim 2 or 3, it is characterized in that, postpone T2 the flip-flop transition of second clock signal that send than described sequential control circuit the flip-flop transition of first clock signal that described sequential control circuit sends when electric power starting, postpone T3 the flip-flop transition of first clock signal that send than described sequential control circuit the flip-flop transition of the 3rd clock signal that described sequential control circuit sends when electric power starting.
5, as D genus audio power amplifier as described in the claim 2, it is characterized in that, also comprise:
First switching circuit and second switch circuit, described first switching circuit and second switch circuit are in parallel with feedback resistance in the described preamplifier; With
The 3rd switching circuit and the 4th switching circuit, described the 3rd switching circuit and the 4th switching circuit are in parallel with feedback capacity in the described integrator, and described first clock signal is controlled the output state of described preamplifier and described integrator by the switch of controlling described first switching circuit, described second switch circuit, described the 3rd switching circuit and described the 4th switching circuit.
6, as D genus audio power amplifier as described in the claim 2, it is characterized in that, described preamplifier comprises the first enable signal end, described integrator comprises the second enable signal end, described second clock signal links to each other with the described second enable signal end with the described first enable signal end, to control the on off state of described preamplifier and described integrator.
7, as D genus audio power amplifier as described in the claim 2, it is characterized in that, described first comparator and described second comparator comprise the 3rd enable signal end and the 4th enable signal end respectively, described the 3rd clock signal links to each other with described the 4th enable signal end with described the 3rd enable signal end, to control the on off state of described first comparator and described second comparator.
8, as D genus audio power amplifier as described in the claim 7, it is characterized in that, described first pull-down circuit comprises first pull down resistor and the 5th switching circuit, described second pull-down circuit comprises second pull down resistor and the 6th switching circuit, and described the 3rd clock signal is controlled described the 5th switching circuit and described the 6th switching circuit to control the on off state of described first pull-down circuit and described second pull-down circuit.
9, as D genus audio power amplifier as described in the claim 8, it is characterized in that described the 5th switching circuit and described the 6th switching circuit are the MOS switching tube.
10, as D genus audio power amplifier as described in the claim 5, it is characterized in that, also comprise inverter to the described first clock signal negate, described first switching circuit, described second switch circuit, described the 3rd switching circuit and described the 4th switching circuit are transmission gate, control described first switching circuit, described second switch circuit, described the 3rd switching circuit and described the 4th switching circuit by first clock signal after described first clock signal and the negate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200820122402 CN201312285Y (en) | 2008-09-02 | 2008-09-02 | D-type audio power amplifier |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200820122402 CN201312285Y (en) | 2008-09-02 | 2008-09-02 | D-type audio power amplifier |
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| CN201312285Y true CN201312285Y (en) | 2009-09-16 |
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| CN 200820122402 Expired - Fee Related CN201312285Y (en) | 2008-09-02 | 2008-09-02 | D-type audio power amplifier |
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Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101826845A (en) * | 2010-04-22 | 2010-09-08 | 成都成电硅海科技股份有限公司 | Voltage control delay circuit-based class D power amplifier |
| CN104467704A (en) * | 2013-11-25 | 2015-03-25 | 松翰科技股份有限公司 | Audio amplifier, electronic device using same and transient noise suppression method |
| CN106059513A (en) * | 2016-05-30 | 2016-10-26 | 矽力杰半导体技术(杭州)有限公司 | DC detection protection circuit and D type amplifier applying same |
| CN106059507A (en) * | 2016-05-30 | 2016-10-26 | 矽力杰半导体技术(杭州)有限公司 | D type amplifier and method for suppressing noise of D type amplifier |
| CN106160681A (en) * | 2015-03-30 | 2016-11-23 | 中航（重庆）微电子有限公司 | A kind of automatic biasing CMOS difference amplifier |
| CN107889024A (en) * | 2017-11-21 | 2018-04-06 | 深圳市沃特沃德股份有限公司 | Voicefrequency circuit and vehicle control syetem |
| CN108462472A (en) * | 2017-02-21 | 2018-08-28 | 株式会社东芝 | D grades of amplifiers |
| CN109120269A (en) * | 2018-08-07 | 2019-01-01 | 上海艾为电子技术股份有限公司 | A kind of digital analog converter |
-
2008
- 2008-09-02 CN CN 200820122402 patent/CN201312285Y/en not_active Expired - Fee Related
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101826845A (en) * | 2010-04-22 | 2010-09-08 | 成都成电硅海科技股份有限公司 | Voltage control delay circuit-based class D power amplifier |
| CN104467704A (en) * | 2013-11-25 | 2015-03-25 | 松翰科技股份有限公司 | Audio amplifier, electronic device using same and transient noise suppression method |
| CN106160681A (en) * | 2015-03-30 | 2016-11-23 | 中航（重庆）微电子有限公司 | A kind of automatic biasing CMOS difference amplifier |
| CN106059513A (en) * | 2016-05-30 | 2016-10-26 | 矽力杰半导体技术(杭州)有限公司 | DC detection protection circuit and D type amplifier applying same |
| CN106059507A (en) * | 2016-05-30 | 2016-10-26 | 矽力杰半导体技术(杭州)有限公司 | D type amplifier and method for suppressing noise of D type amplifier |
| CN106059513B (en) * | 2016-05-30 | 2018-11-23 | 上海芃矽半导体技术有限公司 | Direct current detection protects circuit and the class-D amplifier using it |
| CN106059507B (en) * | 2016-05-30 | 2019-03-01 | 上海芃矽半导体技术有限公司 | Class-D amplifier and the method for inhibiting class-D amplifier noise |
| CN108462472A (en) * | 2017-02-21 | 2018-08-28 | 株式会社东芝 | D grades of amplifiers |
| CN107889024A (en) * | 2017-11-21 | 2018-04-06 | 深圳市沃特沃德股份有限公司 | Voicefrequency circuit and vehicle control syetem |
| CN109120269A (en) * | 2018-08-07 | 2019-01-01 | 上海艾为电子技术股份有限公司 | A kind of digital analog converter |
| CN109120269B (en) * | 2018-08-07 | 2024-02-27 | 上海艾为电子技术股份有限公司 | Digital-analog converter |
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| EE01 | Entry into force of recordation of patent licensing contract |
Assignee: Ningbo BYD Semiconductor Co., Ltd. Assignor: Biyadi Co., Ltd. Contract record no.: 2010440020106 Denomination of utility model: Class D audio power amplifier with anti-saturation distortion circuit Granted publication date: 20090916 License type: Exclusive License Record date: 20100708 |
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| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20090916 Termination date: 20150902 |
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