CN201282142Y - Plastic packaging body flat seal type novel semiconductor packaging structure - Google Patents
Plastic packaging body flat seal type novel semiconductor packaging structure Download PDFInfo
- Publication number
- CN201282142Y CN201282142Y CNU2008200388017U CN200820038801U CN201282142Y CN 201282142 Y CN201282142 Y CN 201282142Y CN U2008200388017 U CNU2008200388017 U CN U2008200388017U CN 200820038801 U CN200820038801 U CN 200820038801U CN 201282142 Y CN201282142 Y CN 201282142Y
- Authority
- CN
- China
- Prior art keywords
- function pin
- bearing base
- chip
- chip bearing
- plastic
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
The utility model relates to a plastic-sealed body flat seal type novel semi-conductor encapsulation structure, which is mainly used for the four-side footless flat patch type encapsulation of a semi-conductor. The encapsulation structure comprises a function pin (3) and a chip bearing base (4). The structure is characterized in that either the function pin (3) or the chip bearing base (4) adopts a single block structure; metal layers (2) are plated on the front sides and the back sides of the function pin (3) and the chip bearing base (4); a passive component (5), such as a resistor , a capacitor or an inductor, is planted into the function pin (3) plated with the metal layers; a chip (7) is planted into the chip bearing base (4) plated with the metal layers; a metal wire (6) is arranged between the chip (7) and the function pin (3); the plastic-sealed body are coated on the function pin (3), the chip bearing base (4), the passive component (5), the chip (7) and the metal wire (6); and the metal layers (2) on the back sides of the function pin (3) and the chip bearing base (4) and the back side of the plastic-sealed body (1) are in the same horizontal plane. The material cost of the encapsulation structure provided by the utility model is relatively low.
Description
(1) technical field
The utility model relates to a kind of semiconductor package, and being mainly used in semi-conductive four sides does not have the flat SMD encapsulation of pin.Belong to the semiconductor packaging field.
(2) background technology
Traditional four sides does not have that the flat SMD encapsulation of pin adopts be at the good whole piece framework of penetration etching basic enterprising luggage sheet, routing, method for packaging semiconductor such as seal.This semiconductor packages of carrying out on the good whole piece frame foundation of penetration etching mainly has the following disadvantages: because framework is the penetration etching, increased material cost.
(3) summary of the invention
The purpose of this utility model is to overcome above-mentioned deficiency, and the flat envelope formula of the lower plastic-sealed body of a kind of material cost novel semi-conductor encapsulating structure is provided.
The purpose of this utility model is achieved in that the flat envelope formula of a kind of plastic-sealed body novel semi-conductor encapsulating structure, comprise function pin and chip bearing base, described function pin and chip bearing base are independent one by one block structure, described function pin and chip bearing base are just, back of the body two sides all is coated with metal level, on the described function pin that is coated with metal level, implant passive device, described passive device is a resistance, electric capacity or inductance, on the described chip bearing base that is coated with metal level, implant chip is arranged, between described chip and function pin, break metal wire, at described function pin, the chip bearing base, passive device, chip and metal wire are sealed plastic-sealed body outward, and the metal level of described function pin and chip bearing base back surface and the described plastic-sealed body back side are on the same horizontal plane.
The utility model semiconductor package is compared with the semiconductor packages components and parts that traditional employing penetration framework is made, have following advantage: function pin of the present utility model and chip bearing base adopt the mode that is pre-formed independent one by one block structure, greatly improved the utilance of metal material, the generation of waste material when having reduced the general frame moulding, and then reduced material cost.
(4) description of drawings
Fig. 1 is the flat envelope formula of a utility model plastic-sealed body novel semi-conductor encapsulating structure schematic diagram.
Among the figure: plastic-sealed body 1, metal level 2, function pin 3, chip bearing base 4, passive device 5, metal wire 6, chip 7.
(5) embodiment
Referring to Fig. 1, the flat envelope formula of a kind of plastic-sealed body novel semi-conductor encapsulating structure that the utility model relates to, comprise function pin 3 and chip bearing base 4, described function pin 3 and chip bearing base 4 are independent one by one block structure, described function pin 3 and chip bearing base 4 are just, back of the body two sides all is coated with metal level 2, on the described function pin 3 that is coated with metal level, implant passive device 5, described passive device 5 is a resistance, electric capacity or inductance, on the described chip bearing base 4 that is coated with metal level, implant chip 7 is arranged, between described chip 7 and function pin 3, break metal wire 6, at described function pin 3, chip bearing base 4, passive device 5, seal plastic-sealed body 1 outside chip 7 and the metal wire 6, and the metal level 2 at the described function pin 3 and chip bearing base 4 back sides is on the same horizontal plane with described plastic-sealed body 1 back side.
Claims (1)
1, the flat envelope formula of a kind of plastic-sealed body novel semi-conductor encapsulating structure, comprise function pin (3) and chip bearing base (4), it is characterized in that described function pin (3) and chip bearing base (4) are independent one by one block structure, described function pin (3) and chip bearing base (4) are just, back of the body two sides all is coated with metal level (2), go up implantation passive device (5) at the described function pin (3) that is coated with metal level, described passive device (5) is a resistance, electric capacity or inductance, go up implantation at the described chip bearing base (4) that is coated with metal level chip (7) is arranged, between described chip (7) and function pin (3), break metal wire (6), at described function pin (3), chip bearing base (4), passive device (5), chip (7) and metal wire (6) are outer seals plastic-sealed body (1), and the metal level (2) at the described function pin (3) and chip bearing base (4) back side and described plastic-sealed body (1) back side are on the same horizontal plane.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNU2008200388017U CN201282142Y (en) | 2008-07-30 | 2008-07-30 | Plastic packaging body flat seal type novel semiconductor packaging structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNU2008200388017U CN201282142Y (en) | 2008-07-30 | 2008-07-30 | Plastic packaging body flat seal type novel semiconductor packaging structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN201282142Y true CN201282142Y (en) | 2009-07-29 |
Family
ID=40929010
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNU2008200388017U Expired - Fee Related CN201282142Y (en) | 2008-07-30 | 2008-07-30 | Plastic packaging body flat seal type novel semiconductor packaging structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN201282142Y (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2022134439A1 (en) * | 2020-12-24 | 2022-06-30 | 江苏长电科技股份有限公司 | Packaging structure having inductive device, and manufacturing method therefor |
-
2008
- 2008-07-30 CN CNU2008200388017U patent/CN201282142Y/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2022134439A1 (en) * | 2020-12-24 | 2022-06-30 | 江苏长电科技股份有限公司 | Packaging structure having inductive device, and manufacturing method therefor |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20090729 Termination date: 20120730 |