CN201196089Y - Communication circuit used for down-hole instrument - Google Patents
Communication circuit used for down-hole instrument Download PDFInfo
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- CN201196089Y CN201196089Y CNU2008201081839U CN200820108183U CN201196089Y CN 201196089 Y CN201196089 Y CN 201196089Y CN U2008201081839 U CNU2008201081839 U CN U2008201081839U CN 200820108183 U CN200820108183 U CN 200820108183U CN 201196089 Y CN201196089 Y CN 201196089Y
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Abstract
The utility model discloses a communication circuit for underground instruments, wherein one end of the communication circuit is connected with an oil well logging system via a EDIB bus and the another end is connected with a data acquisition processing system of the underground instrument via a duplex serial port, the communication circuit is composed a filed programmable gate array chip, a central processing unit, a data memory, a program memory, a reset circuit, a clock generation logic circuit and a data channel, the field programmable gate array chip is connected with the EDIB bus via the data channel and is connected with the central processing unit and the duplex serial port, the data memory, the program memory and the reset circuit are connected with the central processing unit, and the clock generation logic circuit is connected with the central processing unit and the field programmable gate array chip. The utility model provides a suitable communication circuit for direct application in underground instruments of oil well logging systems (ELIS).
Description
Technical field
The utility model relates to a kind of communicating circuit, specifically, relates to a kind of communicating circuit that is applied to the downhole instrument of logging system (ELIS).
Background technology
The communicating circuit of wireline logging instrument is usually based on certain downhole toolbus structure; the logging system (ELIS) of CNOOC's service technology center development has proposed a kind of communication standard of downhole instrument in the prior art; for downhole instrument normally is articulated in the ELIS system, need the communication interface and the control circuit of a kind of special use of design.But, but there are a lot of problems in existing Reference Design in device performance and design, can't be applied directly on the ELIS system bus structure.
In sum, directly not can be applicable to the communicating circuit of the downhole instrument of ELIS system in the prior art; But and the technical grade field programmable gate array (FPGA) that has all used simple reset circuit and poor-performing of Reference Design in the prior art, in the overall performance performance, open defect is arranged, applied environment is restricted.
The utility model content
Technical problem to be solved in the utility model provides a kind of communicating circuit that is used for downhole instrument, does not have a kind of suitable communicating circuit can directly apply to problem in the downhole instrument of logging system (ELIS) in the prior art to solve.
In order to solve the problems of the technologies described above, the utility model provides a kind of communicating circuit that is used for downhole instrument, one end of this communicating circuit is connected with the logging system on ground by the EDIB bus, and the other end is connected with the data acquisition processing system of downhole instrument by duplexing serial ports; Described communicating circuit is made up of field programmable gate array chip, CPU, data storage, program storage, reset circuit, clock occurrence logic circuit and data channel;
Wherein, described field programmable gate array chip is connected with the EDIB bus by described data channel, also is connected with described duplexing serial ports with described CPU respectively; Described data storage, program storage and reset circuit link to each other with CPU respectively, and described clock occurrence logic circuit links to each other respectively at described CPU, field programmable gate array chip.
Further, wherein, described field programmable gate array chip is non-volatile programming, and be applicable to hot environment, the chip that can keep the stability of a system, it is connected with the EDIB bus by described data channel, also is connected with described duplexing serial ports with described CPU respectively.
Described CPU is the 80C186XL chip, and it is connected with described field programmable gate array chip, data storage, program storage, reset circuit and clock occurrence logic circuit respectively.
Described data storage, for the memory capacity of being made up of 2 HM628128 chips is the data storage of 256KB byte, it is the CMOS static data memory with high speed, low-power consumption and single 5V power supply, it is connected with described CPU;
Described program storage, for the memory capacity of being made up of 2 27C256 chips is the program storage of 64KB byte, it is connected with described CPU.
Described reset circuit, the special-purpose μ P that serves as reasons reset and manage the reset circuit that the MAX705 chip is formed, and it is connected with described CPU.
Described data channel is the CMD passage, its respectively with the logging system on described ground by the EDIB bus, and described field programmable gate array chip is connected.
Described duplexing serial ports is full duplex bi-directional synchronization communication serial ports, and it is connected with described field programmable gate array chip.
Further, wherein, described field programmable gate array chip comprises by Manchester code coding decoder, peripheral control logic circuit, the two-way asynchronous communication serial ports of full duplex, data converting circuit, address decoder and Clock dividers and forming; Wherein, described Manchester code coding decoder is used for effective coding/decoding is carried out in the instruction that logging system and described CPU from described ground receive and send.
Technique effect of the present utility model is:
1, adopts the FPGA+MCU structure, reasonably solve the functional requirement of communicating circuit;
2, in downhole instrument, adopt the grade flashFPGA of army of ACTEL first, improved the high-temperature behavior and the job stability of circuit;
3, adopt professional reset circuit design, can realize the slow electrification reset of downhole instrument, help prolonging service life of structure;
4, excellent according to the circuit overall performance that Electro Magnetic Compatibility requires and reliability requirement the designs performance of strictness.
Description of drawings
Fig. 1 is the communicating circuit structural principle block diagram that is applied to the downhole instrument of logging system (ELIS) described in the utility model;
Fig. 2 is the communicating circuit concrete structure block diagram that is applied to the downhole instrument of logging system (ELIS) described in the utility model.
The specific embodiment
The utility model provides a kind of communicating circuit that is used for downhole instrument, does not have a kind of suitable communicating circuit can directly apply to problem in the downhole instrument of logging system (ELIS) in the prior art to solve.Below the specific embodiment is described in detail, but not as to qualification of the present utility model.
In logging system (ELIS), all downhole instruments all are in passive in check status, that is to say that all working state of downhole instrument is determined by ground system.Logging system is controlled all downhole instruments according to certain time sequence by a series of instructions.Different downhole instruments is distinguished with the instrument address, and the address of every kind of downhole instrument all is unique, and every kind of instrument is according to the own specific specific instruction set of address response.
As shown in Figure 1, be applied to the communicating circuit structural principle block diagram of the downhole instrument of logging system (ELIS) for the utility model;
Wherein, an end of communicating circuit is connected with the logging system (ELIS) 109 on ground by the EDIB bus, and the other end is connected with the data acquisition processing system 110 of downhole instrument by duplexing serial ports 108; This communicating circuit is made up of fpga chip 101, CPU (CPU) 102, data storage 103, program storage 104, reset circuit 105, clock occurrence logic circuit 106 and data channel 107;
Wherein, fpga chip one end is connected with the logging system (ELIS) on ground through the EDIB bus by data channel, and the fpga chip other end is connected with duplexing serial ports with CPU respectively; Data storage, program storage and reset circuit link to each other with CPU respectively, and described clock occurrence logic circuit links to each other respectively at CPU, fpga chip.
As shown in Figure 2, be the communicating circuit concrete structure block diagram of the downhole instrument that is applied to logging system (ELIS);
Wherein, fpga chip has been selected the APA600PQ208M army grade chip of ACTEL company for use, and this chip is taked non-volatile programming based on the Flash structure, goes for hot environment, can keep the stability of a system;
CPU selects for use is 80C186XL chip in INTEL Corp.'s 8086 series, and its clock is produced by the 24MHz external crystal-controlled oscillation, through being 12MHz behind the 80C186XL chip internal clock circuit frequency division;
Data storage is made up of 2 HM628128 chips, and memory capacity is 256KBbyte, and it is the CMOS static RAM (SRAM), has the characteristics of high speed, low-power consumption and single 5V power supply.
Program storage is made up of 2 27C256 chips, and it is UV EPROM, can repeatedly programme by programmer, and its non-volatile data content can be used ultraviolet erasing, and its memory capacity is 64KBbyte.
Reset circuit mainly is made up of the special-purpose μ P management MAX705 chip that resets, and it has electrification reset and WATCHDOG (house dog) function.
Main design comprises in the fpga chip here: the peripheral control logic circuit of 80C186XL chip; The two-way asynchronous communication serial ports of the full duplex of communicating by letter with the ELIS ground control system; And Manchester (Manchester code) coding decoder, this coding decoder and HD6408 and HD6409 chip compatibility; Also comprise: data converting circuit, address decoder and Clock dividers, this fpga chip links to each other with the 1M full duplex bi-directional synchronization communication serial ports that dsp board is communicated by letter; This fpga chip also links to each other with clock occurrence logic circuit and other control logic circuit.
ELIS (logging system) will instruct through the EDIB bus and send to fpga chip on the Communication Control plate by the CMD passage, Manchester (Manchester code) coding is adopted in this instruction on fpga chip, 10G CPU Control Unit instructs decoding to the received instruction of carrying local instrument address, the form and the implication of instruction must have clear and definite agreement in command protocols, communicating circuit at first can will read in fpga chip through the instruction of coding, there is Manchester (Manchester code) coding decoder fpga chip inside, instruction is effectively decoded and instruction is effectively discerned, when fpga chip determine instruction decoded finish and effectively after can produce and interrupt to CPU notice CPU reading command.
After the CPU reading command in the communicating circuit, can carry out operation response by instruction system according to a preconcerted arrangement, each circuit is correctly worked under the control well, for downhole instrument, instruction mainly comprises communication test, instrument setting, the control that resets, data acquisition, data transmission etc.
Communication test command request communicating circuit sends one group of number determining, and communication is normal between plane system and the communicating circuit definitely.
It is that the downhole instrument each several part is carried out various settings that instrument is provided with instruction, these settings are undertaken by 1M full duplex bi-directional synchronization communication serial ports, this 1M full duplex bi-directional synchronization communication serial ports is integrated in fpga chip inside, CPU sent out parameter is set goes here and there and change, and in conjunction with the 1M serial clock, frame synchronization forms other parts that standard SPI serial ports is connected to downhole instrument, and instrument parameter is provided with.
The control instruction that resets is the reset instruction of downhole instrument of ground system, after communicating circuit receives reset instruction, can send reset instruction to other each circuit of instrument on the one hand, can control the watchdog circuit chip on the other hand CPU and fpga chip are resetted.
In the downhole instrument instruction system, wherein most important instruction is that data acquisition (ACQUIRE) and data send (SEND) these two instructions.
After 10G CPU Control Unit receives the ACQUIRE instruction, at first can send serial command to data acquisition processing system by 1M full duplex bi-directional synchronization communication serial ports, log-on data is gathered and is handled, after the data acquisition process plate is handled data, can data be reached CPU board by 1M full duplex bi-directional synchronization communication serial ports, fpga chip is gone here and there to the data that receive and is changed, and by interrupt mode data is read into CPU then.
When receiving data transmission order, fpga chip is at first read into fpga chip internal RAM (data storage) with the data that collect from CPU, after all data run through, the inner Manchester coding decoder of fpga chip can be weaved into each data the Manchester sign indicating number of standard and be uploaded to the control system on ground, waits for that then instruction arrives next time.
The communicating circuit of wireline logging instrument of the present utility model is the key that connects downhole instrument and ground system, has played the important function of " forming a connecting link " between logging system (ELIS) the Ground Control treatment system of CNOOC's service autonomous research and development in field and downhole instrument.This communicating circuit is usually based on certain downhole toolbus structure; the ELIS (logging system) of CNOOC's clothes technique center development has proposed a kind of communication standard of downhole instrument; adopted Manchester code that data are encoded; according to transmitting, communicating circuit of the present utility model normally is articulated in downhole instrument in the ELIS system by the total demand pairs of EDIB.
By top described, technique effect of the present utility model is:
1, adopts the FPGA+MCU structure, reasonably solve the functional requirement of communicating circuit;
2, in downhole instrument, adopt the grade flashFPGA of army of ACTEL first, improved the high-temperature behavior and the job stability of circuit;
3, adopt professional reset circuit design, can realize the slow electrification reset of downhole instrument, help prolonging service life of structure;
4, excellent according to the circuit overall performance that Electro Magnetic Compatibility requires and reliability requirement the designs performance of strictness.
Certainly; the utility model also can have other various embodiments; under the situation that does not deviate from the utility model spirit and essence thereof; those of ordinary skill in the art can make various corresponding changes and distortion according to the utility model, but these corresponding changes and distortion all should belong to the protection domain of the appended claim of the utility model.
Claims (8)
1. a communicating circuit that is used for downhole instrument is characterized in that, an end of described communicating circuit is connected with the logging system on ground by the EDIB bus, and the other end is connected with the data acquisition processing system of downhole instrument by duplexing serial ports; Described communicating circuit is made up of field programmable gate array chip, CPU, data storage, program storage, reset circuit, clock occurrence logic circuit and data channel;
Wherein, described field programmable gate array chip is connected with the EDIB bus by described data channel, also is connected with described duplexing serial ports with described CPU respectively; Described data storage, program storage and reset circuit link to each other with CPU respectively, and described clock occurrence logic circuit links to each other respectively at described CPU, field programmable gate array chip.
2. communicating circuit as claimed in claim 1, it is characterized in that, described field programmable gate array chip is non-volatile programming, and be applicable to hot environment, the chip that can keep the stability of a system, it is connected with the EDIB bus by described data channel, also is connected with described duplexing serial ports with described CPU respectively.
3. communicating circuit as claimed in claim 1, it is characterized in that, described CPU is the 80C186XL chip, and it is connected with described field programmable gate array chip, data storage, program storage, reset circuit and clock occurrence logic circuit respectively.
4. communicating circuit as claimed in claim 1, it is characterized in that, described data storage, for the memory capacity of being made up of 2 HM628128 chips is the data storage of 256KB byte, it is the CMOS static data memory with high speed, low-power consumption and single 5V power supply, and it is connected with described CPU;
Described program storage, for the memory capacity of being made up of 2 27C256 chips is the program storage of 64KB byte, it is connected with described CPU.
5. communicating circuit as claimed in claim 1 is characterized in that, described reset circuit, the special-purpose μ P that serves as reasons reset and manage the reset circuit that the MAX705 chip is formed, and it is connected with described CPU.
6. communicating circuit as claimed in claim 1 is characterized in that, described data channel is the CMD passage, its respectively with the logging system on described ground by the EDIB bus, and described field programmable gate array chip is connected.
7. communicating circuit as claimed in claim 1 is characterized in that, described duplexing serial ports is full duplex bi-directional synchronization communication serial ports, and it is connected with described field programmable gate array chip.
8. communicating circuit as claimed in claim 2, it is characterized in that, described field programmable gate array chip comprises by Manchester code coding decoder, peripheral control logic circuit, the two-way asynchronous communication serial ports of full duplex, data converting circuit, address decoder and Clock dividers and forming; Wherein, described Manchester code coding decoder is used for effective coding/decoding is carried out in the instruction that logging system and described CPU from described ground receive and send.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNU2008201081839U CN201196089Y (en) | 2008-05-26 | 2008-05-26 | Communication circuit used for down-hole instrument |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNU2008201081839U CN201196089Y (en) | 2008-05-26 | 2008-05-26 | Communication circuit used for down-hole instrument |
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| CN201196089Y true CN201196089Y (en) | 2009-02-18 |
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| CNU2008201081839U Expired - Fee Related CN201196089Y (en) | 2008-05-26 | 2008-05-26 | Communication circuit used for down-hole instrument |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104615566A (en) * | 2015-03-05 | 2015-05-13 | 中国海洋石油总公司 | Monitoring data conversion device and method of nuclear magnetic resonance logger |
| CN109254198A (en) * | 2018-10-08 | 2019-01-22 | 许昌许继软件技术有限公司 | The synchronous data sampling system and data acquisition device of arrester |
| CN110058612A (en) * | 2018-01-19 | 2019-07-26 | 通用电气航空系统有限责任公司 | Isomery processing in unmanned carrier |
| CN112181881A (en) * | 2020-09-16 | 2021-01-05 | 中国海洋石油集团有限公司 | EDIB-USB communication adapter and communication system |
-
2008
- 2008-05-26 CN CNU2008201081839U patent/CN201196089Y/en not_active Expired - Fee Related
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104615566A (en) * | 2015-03-05 | 2015-05-13 | 中国海洋石油总公司 | Monitoring data conversion device and method of nuclear magnetic resonance logger |
| CN110058612A (en) * | 2018-01-19 | 2019-07-26 | 通用电气航空系统有限责任公司 | Isomery processing in unmanned carrier |
| US11604462B2 (en) | 2018-01-19 | 2023-03-14 | Ge Aviation Systems Llc | Heterogeneous processing in unmanned vehicles |
| CN109254198A (en) * | 2018-10-08 | 2019-01-22 | 许昌许继软件技术有限公司 | The synchronous data sampling system and data acquisition device of arrester |
| CN112181881A (en) * | 2020-09-16 | 2021-01-05 | 中国海洋石油集团有限公司 | EDIB-USB communication adapter and communication system |
| CN112181881B (en) * | 2020-09-16 | 2022-06-14 | 中国海洋石油集团有限公司 | EDIB-USB communication adapter and communication system |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20090218 Termination date: 20160526 |
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| CF01 | Termination of patent right due to non-payment of annual fee |