CN201191885Y - Video processing apparatus for camera - Google Patents

Abstract

The utility model discloses a cam video process device based on a DSP+FPGA structure, which comprises a digital process chip (DSP), a field programmable gate array (FPGA) and a subsidiary circuit. A data line, an address line and a control line are arranged between the digital process chip (DSP) and the field programmable gate array (FPGA). The DSP+FPGA structure has the advantages of flexible structure, stronger commonality and is fit for modular design, further improving the algorism efficiency. Simultaneously, the development period is shorter and the system is easy to maintain and dispatch, thereby the cam video process device is fit for real time signal process and improves the property of the cam.

Description

The camera video processing unit

Technical field

The utility model relates to the camera video image processing system, particularly a kind of camera video processing unit based on the DSP+FPGA structure.

Background technology

Along with security product market is more and more higher to the performance requirement of camera product, when conventional art is done more profound and more profound, use the Wavelet image Processing Algorithm and handle the device of camera video signal also in development, wavelet analysis is the new branch of science that in recent years develops rapidly, can be from the requirement of motion adaptive video signal analysis, thus can focus on any details of signal. and the software of present many wavelet algorithms is realized very ripe; Use the Wavelet image Processing Algorithm simultaneously and handle the device of camera video signal also in development, development along with digital signal processor (DSP) and Field Programmable Gate Array (FPGA), adopt the digital hardware system of DSP+FPGA to demonstrate its superiority, can be together the advantages of the two, take into account speed and flexibility, and the circuit structure that hardware unit adopts has determined its performance quality.

Summary of the invention

The purpose of this utility model is exactly at present situation, a kind of camera video processing unit based on the DSP+FPGA structure is provided, the utility model is to be achieved through the following technical solutions: a kind of camera video processing unit, comprise digital signal processing chip, field programmable gate array and auxiliary circuit composition, auxiliary circuit comprises synchronous dynamic random access memory, fifo device, A/D circuit, flash memory; It is characterized in that, also comprise a data wire 3, an address wire 4 and a control line 5 between digital signal processing chip and the field programmable gate array; Data wire 3 two ends connect the DATE port of digital processing chip and the F1 port of field programmable gate array respectively; Address wire 4 two ends connect the DR port of digital processing chip and the F2 port of field programmable gate array respectively; Control line 5 two ends connect the CON port of digital processing chip and the F3 port of field programmable gate array respectively.

DSP and FPGA carry RAM, be used to deposit needed data of processing procedure and intermediate object program, the configuration data of storage DSP executive program and FPGA among the Flash ROM, FIFO device then are used for the certain operations that realizes that signal processing is commonly used, as delay line, sequential storage etc.

DSP+FPGA structure biggest advantage is that structure is flexible, and stronger versatility is arranged, and is suitable for modularized design, thereby can improve efficiency of algorithm; Its construction cycle of while is shorter, and the easy maintenance and expansion of system are fit to real time signal processing; So this programme just is based on the DSP+FPGA structure and designs the camera video processing unit.

The purpose of Digital Image Processing is exactly that the image after the digitlization is carried out some computing or processing, with the quality that improves image or reach the desired expected results of people.Because image is a 2D signal, therefore, can obtain better treatment effect based on DSP+FPGA structure camera video processing unit, thereby improve the performance of camera.

Description of drawings

Fig. 1 is a camera video processing unit structural representation and as Figure of abstract.

Embodiment

The camera video processing unit is made up of DSP digital processing chip 1 and FPGA field programmable gate array 2 and auxiliary circuit, and auxiliary circuit comprises SDRAM synchronous DRAM, FIFO fifo device, A/D circuit, flash memory (FLASHROM); Also comprise a data wire 3, an address wire 4 and a control line 5 between DSP digital processing chip 1 and the FPGA field programmable gate array 2; Data wire 3 two ends connect the DATE port of DSP digital processing chip 1 and the F1 port of field programmable gate array 2 respectively; Address wire 4 two ends connect the DR port of DSP digital processing chip 1 and the F2 port of FPGA field programmable gate array 2 respectively; Control line 5 two ends connect the CON port of DSP digital processing chip 1 and the F3 port of FPGA field programmable gate array 2 respectively.

The auxiliary core circuit of peripheral circuit carries out work; DSP and FPGA respectively carry RAM, are used to deposit needed data of processing procedure and intermediate object program; The configuration data of storage DSP executive program and FPGA among the FLASH ROM.The FIFO device then is used for realizing the certain operations that signal processing is commonly used, as delay line, sequential storage etc.

The design of memory will consider at first whether speed, type, the capacity of memory can satisfy that computing requires and sexual valence.Such as what; Expand external memory storage in the system, SDRAM is used for that the buffer memory to view data can be set to the SDRAM memory block that four address spaces link to each other at most with the sdram controller of PCI33 compatibility in the algorithm calculating process, the size of each memory block can be 16～128MB, each memory block can separate configurations, and needn't consider continuously the size and the position of memory block with contiguous block, this makes kernel all to regard all SDRAM as single and continuous physical address space.

Mould/number conversion part: the high-speed a/d transfer pair collects signal digitalized after, analog picture signal is converted to data image signal, deposit in the video memory; A/D converter using AD9042, its highest sample frequency can reach 40MHz, and precision is 12, and input reference signal is ± 2V; FPGA field programmable gate array 2 systems adopt the fpga chip of the SpartanII series of Xilinx company, realize the function of FIFO and expansion serial ports with FPGA.Sequencing control is realized that by on-site programmable gate array FPGA the major function of its realization has: the address decoding and the control that produce the DSP visit; Produce the required control signal of DMA port access DSP; Produce the reset signal of DSP; Produce the conversion and control sequential of A/D converter, comprise SCLK (serial clock) and CONV (conversion and control); Produce the received frame synchronizing signal of serial ports.System uses FPCA can reduce the quantity of peripheral chip, and can revise design more easily, for the expansion of system later on provides the space.

Claims (1)

1, a kind of camera video processing unit comprises digital signal processing chip (1), field programmable gate array (2) and auxiliary circuit composition, and auxiliary circuit comprises synchronous dynamic random access memory, fifo device, A/D circuit, flash memory; It is characterized in that, also comprise a data wire (3), an address wire (4) and a control line (5) between digital signal processing chip (1) and the field programmable gate array (2); Data wire (3) two ends connect the DATE port of digital processing chip (1) and the F1 port of field programmable gate array (2) respectively; Address wire (4) two ends connect the DR port of digital processing chip (1) and the F2 port of field programmable gate array (2) respectively; Control line (5) two ends connect the CON port of digital processing chip (1) and the F3 port of field programmable gate array (2) respectively.