CN104023202B - HD video processing system - Google Patents
HD video processing system Download PDFInfo
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- CN104023202B CN104023202B CN201410100057.9A CN201410100057A CN104023202B CN 104023202 B CN104023202 B CN 104023202B CN 201410100057 A CN201410100057 A CN 201410100057A CN 104023202 B CN104023202 B CN 104023202B
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Abstract
The present invention relates to a kind of framework of HD video processing unit, including HD video processing unit, Image Acquisition peripheral hardware, liquid crystal display, ARM microprocessor, SDRAM memory, the AXI system bus interfaces being connected with the image capture interface of Image Acquisition peripheral hardware, with liquid crystal display display interface and respectively with ARM microprocessor and SDRAM memory；The HD video processing unit includes video acquisition module, deblocking filtering module, DMA control modules, system control module, video adjustment control module and high definition display module.The present invention according to the demand of different user with a chip for that can select different parts to use, it can be very good the function of meeting most of user, so as to which a chip solves the functional requirement of a large number of users by reasonable disposition, from cost, the design cost of many electronic products will be substantially reduced, so that design obtains the competitive advantage of bigger, there is wide application value.
Description
Technical field
The present invention relates to the framework of HD video processing unit, belongs to the technical field that HD video is handled.
Background technology
With the construction of the heavy constructions such as the development of video and image relevant industries and safe city, intelligence easily regards
Frequency image processing techniques receives more and more attention.Video image processing technology is derived from computer vision technique, and video figure
The gatherer process of picture is the basis of computer vision technique.Pass through the video image gathered to video camera or image acquiring sensor
Sequence is analyzed, and the target positioning in special scenes, target identification, target following etc. are operated with reaching, and basic herein
The behavior of upper understanding and description target.
The research of video image processing technology is increasingly mature, video image processing system gradually to intelligent, high Qinghua and
Networking direction is developed.High clear video image can include a large amount of useful image informations, this is also just Computer Vision skill
Processing basis has been established in development of the art to abstract semantics direction.But HD video needs to handle mass data, this results in soft
The processing speed of part system is difficult to meet the requirement of system design, so as to reduce the real-time of HD video processing.
The development advanced by leaps and bounds with market to the demand of high definition product, HD video treatment technology.It is many public
Department is all combined with HD video treatment technology with asic technology, is proposed the solution of oneself one after another, it is excellent to devise more moneys
Elegant HD video process chip.In following several years, the development trend of HD video process chip includes：Chip power-consumption is more
It is low, chip integration higher, the video processnig algorithms of the intellectual analysis of semantic abstraction layer and more high coding efficiency.
The content of the invention
In view of the deficiencies of the prior art, the present invention provides the framework of HD video processing unit.High definition of the present invention
The framework of video processing unit can realize the collection, processing and display function of HD video.
Technical scheme is as follows：
A kind of framework of HD video processing unit, including HD video processing unit, Image Acquisition peripheral hardware, liquid crystal display
Device, ARM microprocessor, SDRAM memory, with the image capture interface of Image Acquisition peripheral hardware, with liquid crystal display display interface,
And the AXI system bus interfaces being connected respectively with ARM microprocessor and SDRAM memory；
The HD video processing unit includes video acquisition module, deblocking filtering module, DMA control modules, system
Control module, video adjustment control module and high definition display module；
Described image collection peripheral hardware is connected with the video acquisition module inside HD video processing unit, completes high-definition data
Acquisition tasks；
The liquid crystal display is connected with the HD video display module of HD video processing unit, completes HD video
Display task；
The ARM microprocessor is connected by AXI bus interface with system control module, and effect is that the control to system is posted
Storage is written and read, and controls the task and parameter of the framework；
The SDRAM memory is the chip external memory of video data, and one side DMA control modules will by AXI interfaces
The video data write-in SDRAM memory that processing is completed, another aspect DMA control modules read SDRAM by AXI interfaces and store
Pending video data in module；
The task of the DMA control modules is realized between the framework internal module and inside the framework and framework
Video data is directly accessed between external SDRAM memory；The DMA control modules can at most be configured 16 passages, often
One passage corresponds to different data transfers.Channel parameters storage unit stores the required parameter of data transfer, address fortune
Calculate the address that unit reads the channel parameters value calculating data access of channel parameters storage unit.Channel control unit passes through address
Algorithm unit and the parameter of channel parameters storage unit generation, control fifo controller, reading video data is simultaneously stored in piece
In FIFO.AXI master controllers are connected with AXI system bus interfaces, realize between DMA control modules and outside SDRM memories
Data exchange；
The video acquisition module includes acquisition interface control unit and video type converting unit, the acquisition interface control
Unit processed reads the video data that Image Acquisition peripheral hardware exports by the control to interface signal；The data of the collection regarding
Frequency type conversion unit carries out YUV and RGB color degree space, video sampling, the processing of video data mapping；Handle the number completed
According to being stored in by DMA control modules in SDRAM memory；
The deblocking filtering module includes filtering flow control unit, filtering storage control unit and filtering algorithm and realizes
Unit, the process that the filtering flow control unit control entirely filters, the control signal control filtering algorithm of generation realize list
Member completes specific filter task；Filtering storage control unit reads data from filter memory and is sent to filtering algorithm realization list
Member, and filtering algorithm realize cell processing complete data writing filtering memory in；The DMA control modules are to removing square
The video data that filter module writes video data to be filtered and reading process is completed；
The system control module includes interrupt control register and task control register；The interrupt control register
The interrupting information of control system, task control register complete the enabled and configuration of corresponding task；Register can be connect by AXI
Mouth is by ARM microprocessor Read-write Catrol.
The video adjustment control module completes scaling and the rotation of video image frame；The DMA control modules will be waited to locate
Reason video data is put into input FIFO, and scaling algorithm unit reads the data of input FIFO into row interpolation or sampling processing, will
Handling result write-in output FIFO, DMA control modules read the video data of output FIFO；The flow control unit control is whole
A task realizes process；The algorithm parameter FIFO storage scaling required processing parameters of algorithm unit；Video rotation includes rotation
Turn storage control unit, rotation FIFO and rotation control unit；Storage unit control rotation FIFO is rotated, completes video data
Access；Rotation control unit completes the rotational tasks to rotating storage control unit data streams read；
The HD video display module includes simultaneous display unit, asynchronous display unit, display adapter and interface
Sequential converter unit；The simultaneous display unit supports the simultaneous display of real-time video；The asynchronous display is supported to real-time
Property asynchronous display of less demanding；The either synchronously or asynchronously display unit receives the display video data of the DMA control modules,
By either synchronously or asynchronously handling, video data is sent to display adapter and completes video data frame line synchronous sequence with specifically connecing
The timing conversion of mouth；Arbitration response, data transfer and sequential control are carried out between the interface sequence converter unit and adapter
The interface conversion of system, will show that video data is sent to exterior liquid crystal display and is shown.
The beneficial effects of the invention are as follows：
1st, the present invention is the design object based on a large-scale SOC, by designing, verifying, the design such as comprehensive and domain
Flow, it is final to carry out flow volume production.First, HD video processing unit is realized in a manner of devices at full hardware, wherein realizing numerous normal
Software algorithm.Theoretical research to these algorithms there is important reference to anticipate the hardware realization of other algorithms with innovation
Justice.Second, the system target is HD video, it is necessary to carry out respective handling, the access band to system data to huge data
Width has very high requirement.Research to system storage architecture is advantageously used in other big data chips.3rd, system control
Complicated, simple register cannot store the required parameter of all system operations, so introducing parameter storage storage
Required parameter during algorithm performs, and can access at any time, substantially increase the operational efficiency of system.4th, number
According to caching be used as piece memory storage unit, between different submodules the synchronization of clock played great function, pass through assembly line, shape
The technology such as state machine and ping-pong operation realizes the function of chip design well.
2nd, the design focal point of video processing unit considers storage, framework composition, bus, arbitration scheme, calculation in the present invention
Hardware realization of method etc..The pre-treatment of video and processing procedure are parts necessary to all processing system for video,
As video monitoring system must be used as element using the collection of video and display.ASIC design method is the work(to be realized
It can be integrated on a small chip, whole system possesses the insufficient performance advantage of Software for Design, low energy consumption advantage, low complexity
Degree, advantage etc., consider also there is traditional software design method from many aspects such as the stability of whole system and design price
Unlike advantage., can be with for that according to the demand of different user different part can be selected to use with a chip
Meet the function of most of user well, so that a chip solves the functional requirement of a large number of users by reasonable disposition,
From cost, it will the design cost of many electronic products is substantially reduced, so that design obtains the competitive advantage of bigger,
With wide application value.
Brief description of the drawings
Fig. 1 is the system block diagram of HD video processing unit framework.
Embodiment
The present invention is described in detail with reference to embodiment and Figure of description, but not limited to this.
Embodiment,
A kind of framework of HD video processing unit, including HD video processing unit, Image Acquisition peripheral hardware, liquid crystal display
Device, ARM microprocessor, SDRAM memory, with the image capture interface of Image Acquisition peripheral hardware, with liquid crystal display display interface,
And the AXI system bus interfaces being connected respectively with ARM microprocessor and SDRAM memory；
The HD video processing unit includes video acquisition module, deblocking filtering module, DMA control modules, system
Control module, video adjustment control module and high definition display module；
Described image collection peripheral hardware is connected with the video acquisition module inside HD video processing unit, completes high-definition data
Acquisition tasks；
The liquid crystal display is connected with the HD video display module of HD video processing unit, completes HD video
Display task；
The ARM microprocessor is connected by AXI bus interface with system control module, and effect is that the control to system is posted
Storage is written and read, and controls the task and parameter of the framework；
The SDRAM memory is the chip external memory of video data, and one side DMA control modules will by AXI interfaces
The video data write-in SDRAM memory that processing is completed, another aspect DMA control modules read SDRAM by AXI interfaces and store
Pending video data in module；
The task of the DMA control modules is realized between the framework internal module and inside the framework and framework
Video data is directly accessed between external SDRAM memory；The DMA control modules can at most be configured 16 passages, often
One passage corresponds to different data transfers.Channel parameters storage unit stores the required parameter of data transfer, address fortune
Calculate the address that unit reads the channel parameters value calculating data access of channel parameters storage unit.Channel control unit passes through address
Algorithm unit and the parameter of channel parameters storage unit generation, control fifo controller, reading video data is simultaneously stored in piece
In FIFO.AXI master controllers are connected with AXI system bus interfaces, realize between DMA control modules and outside SDRM memories
Data exchange；
The video acquisition module includes acquisition interface control unit and video type converting unit, the acquisition interface control
Unit processed reads the video data that Image Acquisition peripheral hardware exports by the control to interface signal；The data of the collection regarding
Frequency type conversion unit carries out YUV and RGB color degree space, video sampling, the processing of video data mapping；Handle the number completed
According to being stored in by DMA control modules in SDRAM memory；
The deblocking filtering module includes filtering flow control unit, filtering storage control unit and filtering algorithm and realizes
Unit, the process that the filtering flow control unit control entirely filters, the control signal control filtering algorithm of generation realize list
Member completes specific filter task；Filtering storage control unit reads data from filter memory and is sent to filtering algorithm realization list
Member, and filtering algorithm realize cell processing complete data writing filtering memory in；The DMA control modules are to removing square
The video data that filter module writes video data to be filtered and reading process is completed；
The system control module includes interrupt control register and task control register；The interrupt control register
The interrupting information of control system, task control register complete the enabled and configuration of corresponding task；Register can be connect by AXI
Mouth is by ARM microprocessor Read-write Catrol.
The video adjustment control module completes scaling and the rotation of video image frame；The DMA control modules will be waited to locate
Reason video data is put into input FIFO, and scaling algorithm unit reads the data of input FIFO into row interpolation or sampling processing, will
Handling result write-in output FIFO, DMA control modules read the video data of output FIFO；The flow control unit control is whole
A task realizes process；The algorithm parameter FIFO storage scaling required processing parameters of algorithm unit；Video rotation includes rotation
Turn storage control unit, rotation FIFO and rotation control unit；Storage unit control rotation FIFO is rotated, completes video data
Access；Rotation control unit completes the rotational tasks to rotating storage control unit data streams read；
The HD video display module includes simultaneous display unit, asynchronous display unit, display adapter and interface
Sequential converter unit；The simultaneous display unit supports the simultaneous display of real-time video；The asynchronous display is supported to real-time
Property asynchronous display of less demanding；The either synchronously or asynchronously display unit receives the display video data of the DMA control modules,
By either synchronously or asynchronously handling, video data is sent to display adapter and completes video data frame line synchronous sequence with specifically connecing
The timing conversion of mouth；Arbitration response, data transfer and sequential control are carried out between the interface sequence converter unit and adapter
The interface conversion of system, will show that video data is sent to exterior liquid crystal display and is shown.
Claims (1)
- A kind of 1. HD video processing system, it is characterised in that the HD video processing system include HD video processing unit, Image Acquisition peripheral hardware, liquid crystal display, ARM microprocessor, SDRAM memory, with the image capture interface of Image Acquisition peripheral hardware, The AXI system bus interfaces being connected with liquid crystal display display interface and respectively with ARM microprocessor and SDRAM memory；The HD video processing unit includes video acquisition module, deblocking filtering module, DMA control modules, system control Module, video adjustment control module and high definition display module；Described image collection peripheral hardware is connected with the video acquisition module inside HD video processing unit, completes adopting for high-definition data Set task；The liquid crystal display is connected with the HD video display module of HD video processing unit, completes the display of HD video Task；The ARM microprocessor is connected by AXI bus interface with system control module, and effect is the control register to system It is written and read, controls the task and parameter of the system；The SDRAM memory is the chip external memory of video data, and one side DMA control modules will be handled by AXI interfaces The video data write-in SDRAM memory of completion, another aspect DMA control modules read SDRAM memory modules by AXI interfaces Interior pending video data；The task of the DMA control modules is to realize between the internal system module and the internal system and its exterior Video data is directly accessed between SDRAM memory；The video acquisition module includes acquisition interface control unit and video type converting unit, and the acquisition interface control is single Member reads the video data that Image Acquisition peripheral hardware exports by the control to interface signal；The data of the collection are in video class Type converting unit carries out YUV and RGB color degree space, video sampling, the processing of video data mapping；The data completed are handled, are led to DMA control modules are crossed to be stored in SDRAM memory；The deblocking filtering module includes filtering flow control unit, filtering storage control unit and filtering algorithm and realizes list Member, the process that the filtering flow control unit control entirely filters, the control signal control filtering algorithm of generation realize unit Complete specific filter task；Filtering storage control unit reads data from filter memory and is sent to filtering algorithm realization list Member, and filtering algorithm realize cell processing complete data writing filtering memory in；The DMA control modules are to removing square The video data that filter module writes video data to be filtered and reading process is completed；The system control module includes interrupt control register and task control register；The interrupt control register control The interrupting information of system, task control register complete the enabled and configuration of corresponding task；The video adjustment control module completes scaling and the rotation of video image frame；The DMA control modules are regarded pending For frequency according to being put into input FIFO, scaling algorithm unit reads the data of input FIFO into row interpolation or sampling processing, will handle As a result write-in output FIFO, DMA control modules read the video data of output FIFO；The flow control unit control is whole to appoint Process is realized in business；The algorithm parameter FIFO storage scaling required processing parameters of algorithm unit；Video rotation includes rotation and deposits Store up control unit, rotation FIFO and rotation control unit；Storage unit control rotation FIFO is rotated, completes depositing for video data Take；Rotation control unit completes the rotational tasks to rotating storage control unit data streams read；The HD video display module includes simultaneous display unit, asynchronous display unit, display adapter and interface sequence Converter unit；The simultaneous display unit supports the simultaneous display of real-time video；The asynchronous display is supported will to real-time Seek not high asynchronous display；The either synchronously or asynchronously display unit receives the display video data of the DMA control modules, passes through Either synchronously or asynchronously handle, video data is sent to display adapter completes video data frame line synchronous sequence and physical interface Timing conversion；Carry out arbitration response between the interface sequence converter unit and adapter, data transfer and timing control Interface conversion, will show that video data is sent to exterior liquid crystal display and is shown.
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| CN201410100057.9A CN104023202B (en) | 2014-03-18 | 2014-03-18 | HD video processing system |
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| CN104023202B true CN104023202B (en) | 2018-04-27 |
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| CN109194847A (en) * | 2018-09-12 | 2019-01-11 | 深圳市风扇屏技术有限公司 | A kind of integrated chip for holographic fan screen |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6067098A (en) * | 1994-11-16 | 2000-05-23 | Interactive Silicon, Inc. | Video/graphics controller which performs pointer-based display list video refresh operation |
| CN1716312A (en) * | 2004-05-20 | 2006-01-04 | 英特尔公司 | Hierarchical processor architecture for video processing |
| CN101383968A (en) * | 2008-09-27 | 2009-03-11 | 北京创毅视讯科技有限公司 | Video decoder, video decoding method and mobile multimedia terminal chip |
| CN202210851U (en) * | 2011-02-12 | 2012-05-02 | 北京华夏电通科技股份有限公司 | Control device for standard definition and high-definition audio and video coding and decoding |
| CN105430334A (en) * | 2015-11-19 | 2016-03-23 | 青岛中科软件股份有限公司 | Video image acquisition and processing system based on DSP (Digital Signal Processor) and FPGA (Field Programmable Gate Array) |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020196853A1 (en) * | 1997-06-04 | 2002-12-26 | Jie Liang | Reduced resolution video decompression |
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2014
- 2014-03-18 CN CN201410100057.9A patent/CN104023202B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6067098A (en) * | 1994-11-16 | 2000-05-23 | Interactive Silicon, Inc. | Video/graphics controller which performs pointer-based display list video refresh operation |
| CN1716312A (en) * | 2004-05-20 | 2006-01-04 | 英特尔公司 | Hierarchical processor architecture for video processing |
| CN101383968A (en) * | 2008-09-27 | 2009-03-11 | 北京创毅视讯科技有限公司 | Video decoder, video decoding method and mobile multimedia terminal chip |
| CN202210851U (en) * | 2011-02-12 | 2012-05-02 | 北京华夏电通科技股份有限公司 | Control device for standard definition and high-definition audio and video coding and decoding |
| CN105430334A (en) * | 2015-11-19 | 2016-03-23 | 青岛中科软件股份有限公司 | Video image acquisition and processing system based on DSP (Digital Signal Processor) and FPGA (Field Programmable Gate Array) |
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