CN201181291Y - Distributed multicenter ultrasonic inspection system - Google Patents
Distributed multicenter ultrasonic inspection system Download PDFInfo
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- CN201181291Y CN201181291Y CNU2008200117871U CN200820011787U CN201181291Y CN 201181291 Y CN201181291 Y CN 201181291Y CN U2008200117871 U CNU2008200117871 U CN U2008200117871U CN 200820011787 U CN200820011787 U CN 200820011787U CN 201181291 Y CN201181291 Y CN 201181291Y
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Abstract
The utility model relates to an apparatus for ultrasonic detecting metal products such as steel pipes and steep plates, in particular to a distributive multi-channel ultrasonic flaw detection system. The system consists of a plurality of ultrasonic modules, each ultrasonic module is connected with 2 to 64 ultrasonic probes and is connected with an upper computer through an Ethernet exchanger, and the upper computer is respectively connected with a display, a printer and an alarm device. A location and marking module is connected with one of the ultrasonic probes and with an external location and marking device. Compared with the prior similar products, the distributive multi-channel ultrasonic flaw detection system has the advantages of high flaw detection speed, accurate flaw determination, high field interference resistance, more than one hundred channels, modularized function, free combination, convenient connection and reliable function, and can achieve continuous operation and real-time detection in 365 days.
Description
Technical field
The utility model relates to and metallic articles such as steel pipe, steel plate is carried out ultrasonic detection instrument, particularly a kind of distributed multi-channel ultrasonic flaw.
Background technology
Utilizing ultrasound wave to detect a flaw is a kind of flaw detection means of present Non-Destructive Testing field widespread usage.Metallic article such as steel pipe, steel plate can form a lot of defectives in manufacture process, as crackle, bubble etc.Have a lot of inherent vice human eyes to distinguish to come out, need detect with physical method, ultrasound examination is a very important detection means, and it utilizes characteristics such as ultrasound wave velocity of propagation in metal is fast, detects the judgement defective by analyzing reflection echo.At present, domestic ultrasonic detection instrument has a lot, but on-the-spot ultra-sonic equipment mostly is analog, form by discrete component and small scale integration, volume is big, weight is big, power consumption is big, the problem that carrying out flaw detection speed is low etc. is not well solved, and brings very big inconvenience to the user.
Summary of the invention
For overcoming the above problems, the purpose of this utility model provide a kind of differentiation defective accurately and reliably, the inspection speed height, the distributed multi-channel ultrasonic flaw-inspecting system that volume is little, in light weight, power consumption is little.This system has realized the robotization of ultrasonic detection equipment and miniaturization, the digitizing of instrument for high-speed, the high precision that adapts to modern industry Non-Destructive Testing is proposed, high resolution, high reliability and on-the-spot requirement such as easy to use.
For achieving the above object, the utility model adopts following technical scheme:
Distributed multi-channel ultrasonic flaw-inspecting system, comprise display, host computer, warning device, printer, Ethernet switch, ultrasonic probe, location spray mark module, outside location nameplate spraying device, this system is made up of a plurality of ultrasonic module, each ultrasonic module connects 2-64 ultrasonic probe, each ultrasonic module is connected with host computer by Ethernet switch again, and host computer is connected with display, printer, warning device respectively again; Location spray mark module is connected with one of them ultrasonic probe, and location spray mark module connects outside location nameplate spraying device.
Described ultrasonic module is by the ultrasound emission receiving element, echo amplifying unit able to programme, the A/D sampling unit, the real-time processing unit of FPGA, the FPGA communication processing unit, spray mark and the long interface unit of survey, Ethernet interface is formed, the ultrasound emission receiving element connects echo amplifying unit able to programme, echo amplifying unit able to programme connects the A/D sampling unit, the A/D sampling unit connects the real-time processing unit of FPGA, the real-time processing unit of FPGA connects the FPGA communication processing unit, spray mark and the long interface unit of survey, the real-time processing unit of FPGA also connects the ultrasound emission receiving element, echo amplifying unit able to programme, the FPGA communication processing unit connects Ethernet interface.
The course of work of the present utility model is:
Each ultrasonic module is that field programmable gate array is the control core with two FPGA (Field Programmable Gate Array), wherein the real-time processing unit of the FPGA of lower floor produces trigger pulse is given each passage by transmitter module ultrasonic probe, deliver to AD conversion unit (A/D sampling unit) after by ultrasonic receiving element module the echoed signal of each passage ultrasonic probe being amplified by echo amplifying unit able to programme, the digital signal of conversion is delivered to the real-time processing unit of the FPGA of lower floor, and is equipped with special-purpose lower floor's FPGA software of differentiating defective and realizes that UT (Ultrasonic Testing) detects.Upper strata FPGA communication processing unit mainly transmits the various parameters and the Wave data of the real-time processing unit of the FPGA of lower floor, transmit various parameters and Wave data mutually by Ethernet and host computer again, host computer transmits parameter also according to the Wave data that transmits by 100,000,000 nets and upper strata FPGA communication processing unit, show various waveforms, hinder data, have the warning of wound also can print simultaneously and hinder the result.
The utility model is to adopt 90nm technology CYCLONEII Series FPGA chip (manufacturing process is with the P4 processor) to form embedded system, utilization SOPC (System OnProgrammable Chip abbreviates programmable system on chip as) control and treatment when putting into effect.Simulation, the integrated unified ultrasonic module that constitutes of digital circuit, whole system has only three kinds of circuit-board cards, and full surface mount elements welding is changed easy to maintenance.The powerful chip of integrated employing substitutes multiple element, and computing machine does not have card plugging structure, and the optimization of hardware tie point reduces, and splicing ear adopts latch-up structure, and is simple in structure, intermediate link is few, failure rate is low.Network distribution Open architecture is not subjected to the computer card restricted number.When system broke down, hardware such as audible alarm, host computer can select the various products for civilian use to substitute.(can substitute with notebook computer) as host computer.Based on the above, the problem in the actual as previously mentioned carrying out flaw detection can be well solved.
The utility model is compared with existing like product, have that carrying out flaw detection speed is fast, to differentiate defective accurate, on-the-spot antijamming capability is strong, under the situation of port number as many as passages up to a hundred, realize function modoularization, but independent assortment, line are easy, the characteristics of reliable in function, can realize running without interruption in on-the-spot 365 days, detect in real time.
Description of drawings
Fig. 1 is one-piece construction figure of the present utility model;
Fig. 2 is the frame circuit diagram of the utility model ultrasonic module;
Fig. 3 is a ultrasound emission receiving element theory diagram of the present utility model;
Fig. 4 is an echo of the present utility model amplifying unit theory diagram able to programme;
Fig. 5 is an A/D sampling unit theory diagram of the present utility model;
Fig. 6 is the real-time processing unit theory diagram of FPGA of the present utility model;
Fig. 7 is a FPGA communication processing unit theory diagram of the present utility model;
Fig. 8 is spray mark of the present utility model and surveys long interface unit theory diagram.
Embodiment
Describe the technical solution of the utility model in detail below in conjunction with accompanying drawing
See Fig. 1, distributed multi-channel ultrasonic flaw-inspecting system, comprise display 111, host computer 110, warning device 112, printer 113, Ethernet switch 109, ultrasonic module 106, ultrasonic module 107, ultrasonic module 108, ultrasonic probe 102, ultrasonic probe 103, ultrasonic probe 104, location spray mark module 105, outside location nameplate spraying device 101, this system is made up of a plurality of ultrasonic module, each ultrasonic module connects 2-64 ultrasonic probe, each ultrasonic module is connected with host computer by Ethernet switch again, host computer more respectively with display, printer, warning device is connected; Location spray mark module is connected with one of them ultrasonic probe, and location spray mark module connects outside location nameplate spraying device.
See Fig. 2, described ultrasonic module is by ultrasound emission receiving element 1, echo amplifying unit 2 able to programme, 100MhHzA/D sampling unit 3, the real-time processing unit 4 of FPGA, FPGA communication processing unit 5, spray mark and the long interface unit 7 of survey, 100M Ethernet interface 6 is formed, ultrasound emission receiving element 1 connects echo amplifying unit 2 able to programme, echo amplifying unit able to programme connects 100MhHz A/D sampling unit 3,100MhHz A/D sampling unit 3 connects the real-time processing unit 4 of FPGA, the real-time processing unit 4 of FPGA connects FPGA communication processing unit 5, spray mark and the long interface unit 7 of survey, the real-time processing unit 4 of FPGA also connects ultrasound emission receiving element 1, echo amplifying unit 2 able to programme, FPGA communication processing unit 5 connect Ethernet and connect 6 mouthfuls.
Display 111 adopts the liquid crystal widescreen display, meets the ergonomics requirement.
Warning device 112 is selected the audio amplifier integrated with display for use, can simulate the flaw detection of different frequency auditory tone cues, coupling warning, but the voice prompt alarm content.
Printer 113 is selected laser printer for use, can get the result of detection of every steel pipe at any time.
Host computer 110 is selected brand name computer or server for use, and no card plugging structure reduces failure rate.Host computer external connection keyboard mouse, display, printer can be realized man-machine conversation, the function of alarm, testing result printout, and software Vcc++ language compilation operates under the WIN98/WIN2000/WINXP operating system.
Ethernet switch 109 connects a plurality of ultrasonic module communications, guarantees individual module 100Mbit communication speed.(10Mbit speed can realize that video transmits)
Ultrasonic module 106 is controlled the emission of ultrasonic trigger pulse, receives and handles ultrasound echo signal, declares and after wound is discerned data is passed through Ethernet interface, delivers to Ethernet switch 109, and then sends host computer to.Can expand to 32 (each module can connect 2-64 probe) according to system requirements.
Location spray mark module: controlled by No. 1 ultrasonic module, output spray mark alerting signal, received code device pulse signal, the falling signal of having popped one's head in are used for defect location.
Outside location nameplate spraying device: spray gun, external probes play the speed feedback pulse signal of falling signal, motor.These signals are delivered to the spray mark and are surveyed long locating module by spray mark and the long interface of survey.
The utility model is core control with the ultrasonic module, is described in detail its course of work below again:
The multichannel radiating circuit of ultrasound emission receiving element 1 sends the high electric field pulse of excitation ultrasound ripple probe, the electric signal that returns by acoustic-electric energy conversion reception ultrasonic probe is an echoed signal, behind the multipath reception circuit through ultrasound emission receiving element 1 inside, by converting the echoed signal of one tunnel timesharing output behind the analog switch to by sequential square wave control switching.
Echo amplifying unit 2 able to programme is echoed signals that ultrasound emission receiving element 1 is produced, real-time control by the real-time processing unit 4 of FPGA, through echo amplifying unit 2 waveform amplification able to programme, amplification range is-10～90dB, produces the waveform of different amplification quantity able to programme.
The waveform signal that 100Mhz A/D sampling unit 3 is produced echo amplifying unit 2 able to programme through after the differential amplification, changes into analog waveform through A/D converter the Wave data of digital signal again.The Wave data of the digital signal that 100Mhz A/D sampling unit 3 is produced is connected to the real-time processing unit 4 of FPGA.
The real-time processing unit 4 of FPGA is by FPGA software, gather the digital signal waveform of 100Mhz A/D sampling unit 3 in real time, and deliver to the respective memory locations of different passages, the real time discriminating defective, control the parameters such as amplification quantity of each passage in real time, the real-time analysis deal with data, thus it is fast to reach carrying out flaw detection speed, differentiates defective work characteristics accurately.The real-time processing unit 4 of FPGA is by control spray mark and survey the position that long interface unit 7 obtains current defective, and makes marks by the spray mark on corresponding position.The real-time processing unit 4 of FPGA passes to FPGA communication processing unit 5 to the defective locations of the Wave data of each passage, each passage and other parameters.
FPGA communication processing unit 5 is delivered to 100M Ethernet interface 6. to the defective locations of the Wave data of each passage, each passage and other parameters
100M Ethernet interface 6 is passages of the data of FPGA communication processing unit 5 being delivered to Ethernet switch by Ethernet interface.
See Fig. 3, the ultrasound emission receiving element is made up of transponder pulse change-over circuit, pulsed drive, transmitter unit, receiving element, echo high resistant conversion output circuit.
The transponder pulse change-over circuit is the pulse signal of the 3.3V of the real-time processing unit output of FPGA to be connected to eight select an analog switch input end.
Pulsed drive is eight to select the pulse signal of eight output terminal 5V of an analog switch, through special driving chip 7667, converts the trigger pulse of 12V to.
Transmitter unit is hyperacoustic signal source, the pulse signal that is produced by pulsed drive can trigger the high speed high voltage switch pipe, the high speed high voltage switch pipe has 400～500 volts of voltage inputs, when its conducting, to be stored in electric energy on the high-voltage capacitance through the ultrasonic probe rapid discharge, thereby swash the most nearly 8 ultrasonic probes of strive forward, produce ultrasound wave.The conducting of high speed high voltage switch pipe is controlled by trigger end, triggers moment to be the ultrasonic emitting starting point, is the starting point of single channel sequential.
Receiving element is meant the echoed signal of 8 ultrasonic probes, through impedance matching, by the circuit of two diode pair input signal amplitude limits.
Echo high resistant conversion output circuit has with a high resistant and amplifies and the chip 4141 of switch function, the circuit that a plurality of discrete components before having replaced are formed, and enlargement factor generally about 2 times, is exported by the different echoes of popping one's head in of sequential control.
See Fig. 4, echo amplifying unit 2 one total level Four able to programme are amplified, wherein first three grade amplification is subjected to programmable control circuit control, just these three grades of amplifications and programmable control circuit are formed the programme-controlled gain unit, gain margin-10dB is to 90dB, the chip of these three grades of amplification usefulness is AD603 of ANALOG DEVICE company, it is the novel amplifier of a kind of low noise, Control of Voltage gain, its transmission bandwidth is up to 90MHz, and gain reaches as high as 51dB, minimum reaching-11dB.That use in the programmable control circuit is MAX530, and it is the low-power consumption 12 bit parallel DAC that MAXI company releases, and by the real-time processing unit control of FPGA MAX530, realizes gain-adjusted.The fourth stage amplifies the AD 810 that adopts ANALOG DEVICE company, and it is the operational amplifier of low-power consumption, amplifies twice by it.After the fourth stage amplifies output, carry out frequency-selecting by frequency selection network control, frequency-selecting is: low channel and hf channel.Through after the frequency-selecting, pass through follow circuit again after, output waveform.
See Fig. 5,100MhHzA/D sampling unit 3 is that the waveform of amplification able to programme is delivered to differential amplifier circuit, what use in the differential amplifier circuit is high-performance high speed 320MHz differential amplifier, adopt the XFCB bipolar technology, realize the conversion of single-ended-to-difference amplifier, differential signal amplifies and driving thereby simplify, and can adjust the common mode output voltage, outside adjustment gain and low harmonic distortion.A/D converter selects for use the AD9214 of AD company to finish mould/number conversion, and output signal is sent into the real-time processing unit of FPGA.AD9214 is the ADC chip of a 10bit, and the highest sampling rate is 105Msps.The highest input data rate can reach 100Msps.Adopt this chip, the broadband signal that system will receive is sampled with higher speed with regard to realizing, reduces sampling rate to greatest extent and reduces the signal-to-noise ratio degradation that is caused.
See Fig. 6, the key control unit that the real-time processing unit 4 of FPGA is native systems.It is controlled by on-site programmable gate array FPGA (field programmable gate array) realization.FPGA is the highest a kind of of integrated level in the special IC (ASIC).Kernel control chip adopts EP2C8Q208C8, and it is the up-to-date main flow CycloneII chip of ALTERA company, has the interface of enriching and peripheral hardware 90nm, and 8,256Les is equivalent to 200,000 scales, and ASCI and ASSP are cheap relatively has an advantage able to programme.
The crystal oscillator control circuit is that the external crystal-controlled oscillation output of 100M inputs to FPGA inside by FPGA clock input pin, forms the fundamental clock of FPGA.
Initiatively the series arrangement circuit adopts active arrangement chip EPCS1, come the boot configuration operation, under the FPGA active mode, initiatively export control and synchronizing signal (comprising configurable clock generator) by target FPGA, give the configuring chip of Altera special use, after configuring chip receives order, just configuration data is issued FPGA, finish layoutprocedure.
The JTAG configuration circuit be by under the jtag interface in the program of FPGA, and carry out on-line debugging.
Data after the A/D conversion are delivered in the FPGA, gather in real time by the program of FPGA, and carry out data analysis according to the data of gathering and handle.
The dual port RAM data are the ties of getting in touch between real-time processing unit of FPGA and the FPGA communication processing unit, carry out data transmission by it.
Logic control signal output is by the programmed control in the FPGA, the synchronizing signal of output and channel switching signal, totally four signal A0, A1, EN1 and EN2.
Trigger pulse output also is by the programmed control in the FPGA, gives the emission start pulse signal that receiving element provides.
The location output of spray mark output survey length is by the programmed control in the FPGA, and the mark signal is sprayed in output accordingly when hindering, and FPGA reads the outside X and the rate signal of Y direction in real time simultaneously, and a falling signal of external probes.
See Fig. 7, FPGA communication processing unit 5 is the communications that realize host computer and the real-time processing unit of FPGA.It is controlled by on-site programmable gate array FPGA (field programmable gate array) realization.Kernel control chip adopts EP1C12Q240C8N, and it also is the up-to-date mainstream chip of ALTERA company.
The crystal oscillator control circuit is that the external crystal-controlled oscillation output of 40M inputs to FPGA inside by FPGA clock input pin, forms the fundamental clock of FPGA.
Initiatively the series arrangement circuit adopts active arrangement chip EPCS1, come the boot configuration operation, under the FPGA active mode, initiatively export control and synchronizing signal (comprising configurable clock generator) by target FPGA, give the configuring chip of Altera special use, after configuring chip receives order, just configuration data is issued FPGA, finish layoutprocedure.
The JTAG configuration circuit be by under the jtag interface in the program of FPGA, and carry out on-line debugging.
Data storage cell is made up of FLASH chip and SDRAM chip, and the FLASH chip adopts AM29LV160,2M byte.The SDRAM chip adopts the K4S641632F of Samsung, and capacity is 8M, and program run district and buffer zone are provided.
The dual port RAM data are the ties of getting in touch between FPGA communication processing unit and the real-time processing unit of FPGA, carry out data transmission by it.Thereby the data of host computer are passed to the real-time processing unit of FPGA, simultaneously the data of the real-time processing unit of FPGA are passed to host computer.
Network control circuit LAN91C111 Ethernet chip, the Ethernet speed of support 10M and 100M.Support 8,16 and 32 s' bus.
Network interface is connected to Ethernet switch, handles the communication of FPGA communication processing unit and host computer.
See Fig. 8, it is by the programmed control in the FPGA that the output of long location is surveyed in the output of spray mark, and the corresponding spray mark of output signal when hindering through spray mark driving circuit, forms the 220V alternating voltage and delivers to outside nameplate spraying device by spray tag splice mouth.Simultaneously outside probe rises and falls and the rate signal of X and Y direction, through optical coupling isolation circuit, behind the plastic drive circuit, going here and there out circuit through incorporating into, read the outside X and the rate signal of Y direction by the real-time processing unit control of FPGA, and a falling signal of external probes.Incorporate wherein that to go here and there out circuit be that 3 74HCT165 chipsets are linked to be into, control, read current location and the probe state that rises and falls by the software of the real-time processing unit of FPGA.
Claims (2)
1, distributed multi-channel ultrasonic flaw-inspecting system, comprise display, host computer, warning device, printer, Ethernet switch, ultrasonic probe, location spray mark module, outside location nameplate spraying device, it is characterized in that, this system is made up of a plurality of ultrasonic module, each ultrasonic module connects 2-64 ultrasonic probe, each ultrasonic module is connected with host computer by Ethernet switch again, and host computer is connected with display, printer, warning device respectively again; Location spray mark module is connected with one of them ultrasonic probe, and location spray mark module connects outside location nameplate spraying device.
2, distributed multi-channel ultrasonic flaw-inspecting system according to claim 1, it is characterized in that, described ultrasonic module is by the ultrasound emission receiving element, echo amplifying unit able to programme, the A/D sampling unit, the real-time processing unit of FPGA, the FPGA communication processing unit, spray mark and the long interface unit of survey, Ethernet interface is formed, the ultrasound emission receiving element connects echo amplifying unit able to programme, echo amplifying unit able to programme connects the A/D sampling unit, the A/D sampling unit connects the real-time processing unit of FPGA, the real-time processing unit of FPGA connects the FPGA communication processing unit, spray mark and the long interface unit of survey, the real-time processing unit of FPGA also connects the ultrasound emission receiving element, echo amplifying unit able to programme, the FPGA communication processing unit connects Ethernet interface.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNU2008200117871U CN201181291Y (en) | 2008-03-28 | 2008-03-28 | Distributed multicenter ultrasonic inspection system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNU2008200117871U CN201181291Y (en) | 2008-03-28 | 2008-03-28 | Distributed multicenter ultrasonic inspection system |
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| CN201181291Y true CN201181291Y (en) | 2009-01-14 |
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| Application Number | Title | Priority Date | Filing Date |
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| CNU2008200117871U Expired - Fee Related CN201181291Y (en) | 2008-03-28 | 2008-03-28 | Distributed multicenter ultrasonic inspection system |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101545888B (en) * | 2008-03-28 | 2011-05-11 | 鞍山长风无损检测设备有限公司 | Distributed multi-channel ultrasonic flaw-inspecting system |
| CN108956761A (en) * | 2017-05-23 | 2018-12-07 | 浙江工商职业技术学院 | Steel plate all standing ultrasonic detection device and method |
-
2008
- 2008-03-28 CN CNU2008200117871U patent/CN201181291Y/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101545888B (en) * | 2008-03-28 | 2011-05-11 | 鞍山长风无损检测设备有限公司 | Distributed multi-channel ultrasonic flaw-inspecting system |
| CN108956761A (en) * | 2017-05-23 | 2018-12-07 | 浙江工商职业技术学院 | Steel plate all standing ultrasonic detection device and method |
| CN108956761B (en) * | 2017-05-23 | 2020-12-25 | 浙江工商职业技术学院 | Steel plate full-coverage ultrasonic detection device and method |
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| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20090114 Termination date: 20120328 |