CN201163404Y

CN201163404Y - Communication interface based on FPGA

Info

Publication number: CN201163404Y
Application number: CNU2008200190275U
Authority: CN
Inventors: 杨�嘉; 刘勇; 李磊; 项红强; 王伟
Original assignee: Qingdao Hisense Electronics Co Ltd
Current assignee: Hisense Electric Co Ltd; Qingdao Hisense Electronics Co Ltd
Priority date: 2008-03-14
Filing date: 2008-03-14
Publication date: 2008-12-10
Anticipated expiration: 2018-03-14

Abstract

The utility model discloses a communication interface based on an FPGA, which comprises a socket and a plug matched with the socket, wherein, one is arranged on an FPGA board, and the other is arranged on a processor mainboard. The communication interface is characterized in that: the communication interface comprises a transmission bus signal, a control signal, a data signal and a functional pin of a power supply, and the pin is respectively and correspondingly connected with the FPGA and a corresponding functional circuit in a processor. The utility model provides an interface suitable for communication between the FPGA and the processor; by defining the content and electrical characteristics of the interface, the effective communication between the FPGA and a TV signal processor is realized, and the working efficiency of the design and development of the processor is improved.

Description

Communication interface based on FPGA

Technical field

The utility model relates to a kind of communication interface, specifically, relates to the interface that communicates between a kind of FPGA and the processor, belongs to technical field of television sets.

Background technology

FPGA is the abbreviation of English Field Programmable Gate Array, i.e. field programmable gate array, and it is the product that further develops on the basis of programming devices such as PAL, GAL, PLD.FPGA inside comprises programmed logical module, output load module and three parts of interconnector, and the user can reconfigure the logic module and the I/O module of FPGA inside, realizing user's logic, thereby also is used to the simulation to CPU.The user is placed in the Flash chip of FPGA the programming data of FPGA, is loaded among the FPGA by powering on, and it is carried out initialization.Also can be online to its programming, realize system's on-line reorganization.FPGA had both solved the deficiency of custom circuit, had overcome the limited shortcoming of original programming device gate circuit number again, had obtained using widely in integrated circuit fields.

In the production run of televisor, design, debugging and software Development and the debugging work of its inner signal processing main chip of using are one of vital operations, and the performance of the software of signal processing main chip and configuration thereof directly influences the performance of whole televisor.So, developing high-performance, high-quality chip, need constantly to carry out debugging and verification on stream, and FPGA can finish the artificial debugging process of master chip performance well.But, because interface and the existing television signal processor interface of FPGA can not directly mate, limit communication speed and communication quality between FPGA and the processor, reduced the efficient of processor debugging and checking, thereby limited the efficient of whole development.

For these reasons, how designing a kind of interface that can realize efficient communication between FPGA and the processor, so that utilize FPGA to carry out the development of television system, is technical problem underlying to be solved in the utility model.

The utility model content

The utility model provides a kind of communication interface based on FPGA in order to solve the technical matters that television signal processor interface and FPGA interface can not directly mate in the prior art, and described interface is applicable to the intercommunication mutually between FPGA and the processor; By the content and the electrical specification of defining interface, realized the efficient communication between FPGA and television signal processor, can utilize FPGA to carry out the development of television system.

For solving the problems of the technologies described above, the utility model is achieved by the following technical solutions:

A kind of communication interface based on FPGA, comprise socket and supporting with it plug, one is installed on the FPGA plate, another is installed on the processor main board, it is characterized in that, described communication interface includes the function pin of transfer bus signal, control signal, data-signal and power supply, described pin respectively with the corresponding connection of corresponding function circuit in FPGA and the processor.

Wherein, the function pin of described transfer bus signal comprises a pair of bus clock pin SCL and a pair of bus data pin SDA, and described bus adopts I ²The C bus; I ²The C bus realizes the transmission of data between FPGA and the processor by SCL pin and SDA pin.

Further, the function pin of described transmission of control signals comprise a pair ofly read to enable to control pin, a pair of writing enables to control pin, a pair of address latch signal control pin and a pair of chip selection signal control pin; Described processor send control signal corresponding by described control tube human hair combing waste, and FPGA is controlled.

Further, the function pin of described transmission of data signals is a pair of 8 bit data bus pins, and the needed partial data information of FPGA plate transfers in the storer of FPGA by described 8 bit data bus pins.

And in described interface, the function pin of transmission power supply comprises the pin and a pair of ground pin of a pair of transmission 5V power supply at least.Wherein, for solving interference problem, described grounding function pin is four pairs, guarantees that each function pin to the transmission unlike signal all has at least a pair of ground pin corresponding with it.

Except that the above-mentioned functions pin, described interface also comprises at least one pair of reserved pin, and the user can be according to the actual functional capability needs, and by described reserved pin, the pin function of docking port is expanded.

Again further, described interface is the socket or the plug of double 40 pins; FPGA and processor be the socket by corresponding plug or socket and described interface or plug is corresponding is connected respectively; Wherein, the contact pin of described plug adopts gilding to make, and is good to guarantee contact, and then improves the reliability of signal transmission between FPGA and the processor.

Preferably, in the utility model, described processor is microcontroller MCU.

Compared with prior art, advantage of the present utility model and good effect are: by the communication interface between FPGA and the processor is carried out the definition of content and electrical specification, realized the efficient communication of FPGA and processor.When the signal processing main chip of using in televisor was not made with the final physical form as yet, the code programming that chip is part or all of made the partial function of its emulation chip in FPGA, to carry out software Development work.Adopt aforesaid way not only the whole process that chip development is made to system's complete machine can be divided with the form of module, each several part can walk abreast as soon as possible and carry out, but also the correctness of proofing chip design has in time improved work efficiency greatly.

Description of drawings

Fig. 1 utilizes the utility model interface to realize the system architecture diagram of FPGA emulation board and MCU debugging board communications;

Fig. 2 is the pin layout of double 40 pin interfaces among Fig. 1.

Embodiment

Below in conjunction with accompanying drawing embodiment of the present utility model is described in detail.

When the signal processing main chip of using in televisor is not made with the final physical form as yet, need constantly to the program in the chip debug, modification and perfect.Can utilize the logic module and the I/O module of the abundant inside of FPGA, the partial function that the emulation master chip will be realized by chip being debugged program code programming part or all of in the plate in the FPGA emulation board.By such mode, both the process of chip development can be divided into a plurality of modules, each module can concurrent development, has improved work efficiency greatly; Simultaneously, by the artificial debugging of FPGA, can proofing chip the correctness of design, further improved the efficient of designing and developing.Guarantee carrying out smoothly of above-mentioned development, require to keep efficiently between FPGA and the master chip, communicate by letter smoothly, to increase work efficiency.

Embodiment one, referring to shown in Figure 1.Among the figure, FPGA emulation board 1 communicates by interface 3 with MCU debugging plate 2.Consist predominantly of a Programmable Logic Device 14 in the FPGA emulation board 1, the user can reconfigure logical circuit, with the logic function that needing to realize.Also comprise the SDRAM12 and the peripheral circuits such as FLASH13 and power circuit 11 that are used for storing data information in the FPGA emulation board.MCU parallel port debugging plate 2 comprises microprocessor MCU22, FLASH21 and I ²Peripheral circuits such as C bus interface 24, Remote Control Interface 23 and keystroke interface 25.

The interface 3 that above-mentioned realization FPGA emulation board 1 is communicated by letter with MCU debugging plate 2 adopts the topological design of double 40 pins, and its each function pin is debugged the corresponding connection of function corresponding circuit in the plate 2 with FPGA emulation board 1 and MCU respectively.Each pin is defined as follows shown in the table 1:

Table 1

From above-mentioned table 1, can clearly be seen that: the function pin that has defined transfer bus signal, control signal, data-signal and power supply in the described communication interface.Wherein, pin one 8,23 and pin one 9,22 are respectively the SDA and the SCL pin of a pair of transfer bus signal, I ²The C bus realizes that by SDA and SCL pin FPGA emulation board and MCU debug the data transmission between the plate.

In the pin of above-mentioned communication interface transmission of control signals, pin 9 and 32 is a pair of MCU chip selection signal CS pin, and MCU sends chip selection signal by the CS pin, and the fpga chip of need selecting communicates.Pin one 0 and 31 is a MCU address latch signal ALE pin, and MCU drives address lock car device latch address signal by the ALE pin.Pin one 1 and 30 enables the WR pin for MCU writes, and MCU sends write signal by the WR pin, and the data message among the MCU is written in the FPGA emulation board of choosing.Pin one 2 and 29 is for MCU reads to enable the RD pin, and MCU sends read signal by the RD pin, and the data message in the FPGA emulation board is read in the MCU debugging plate.

When televisor carries out the OSD debugging, be loaded in the FPGA emulation board for conveniently debugging resource, in the card extender interface, also defined the function pin of 8 pairs 8 transmission of data signals, be respectively pin one to 8 and pin 33 to 40.

The pin that also comprises a pair of transmission 5V power supply in the described interface, i.e. pin two 0 and 21 in the table.In addition, for solving interference problem, ground pin has defined four pairs, be respectively pin one 4 and 27, pin one 5 and 26, pin one 6 and 25 and pin one 7 and 24, guarantee that each function pin to the transmission unlike signal all has at least a pair of ground pin corresponding with it, shielding when being used to connect up avoids interference.

Except that the above-mentioned functions pin, described card extender interface also comprises a pair of reserved pin RES, i.e. pin one 3 and 28.This wouldn't define reserved pin, and the card extender interface can be according to the needs of actual functional capability, and RES defines to reserved pin, the expansion of Convenient interface pin function.

Above-mentioned card extender interface can be the socket of double 40 pins, and the FPGA emulation board is connected with described interface socket is corresponding by corresponding plug respectively with MCU debugging plate.Wherein, the contact pin of described plug adopts gilding to make, and is good to guarantee contact, and then improves the reliability of signal transmission between FPGA plate and the mainboard.

Certainly, the card extender interface also can adopt the plug of double 40 pins, and the FPGA emulation board is connected with described interface plug is corresponding by corresponding socket respectively with MCU debugging plate.

Described interface can be arranged on separately on the pcb board, is made into independent interface card extender; Also can be set directly on the FPGA plate, like this can be so that FPGA plate and card extender structure are compact more, and reduced hardware cost.

Fig. 2 is the pin layout of the described double card extender interface of Fig. 1, and the concrete definition of its each pin is with reference to table 1.

Certainly; the above only is a kind of preferred implementation of the present utility model; should be understood that; for those skilled in the art; under the prerequisite that does not break away from the utility model principle; can also make some improvements and modifications, these improvements and modifications also should be considered as protection domain of the present utility model.

Claims

1, a kind of communication interface based on FPGA, comprise socket and supporting with it plug, one is installed on the FPGA plate, another is installed on the processor main board, it is characterized in that, described communication interface includes the function pin of transfer bus signal, control signal, data-signal and power supply, described pin respectively with the corresponding connection of corresponding function circuit in FPGA and the processor.

2, the communication interface based on FPGA according to claim 1 is characterized in that, the function pin of described transfer bus signal comprises a pair of bus clock pin and a pair of bus data pin.

3, the communication interface based on FPGA according to claim 2 is characterized in that, described bus is I ²The C bus.

4, the communication interface based on FPGA according to claim 1, it is characterized in that, the function pin of described transmission of control signals comprise a pair ofly read to enable to control pin, a pair of writing enables to control pin, a pair of address latch signal control pin and a pair of chip selection signal control pin; Described processor send control signal corresponding by described control tube human hair combing waste, and FPGA is controlled.

5, the communication interface based on FPGA according to claim 1, it is characterized in that, the function pin of described transmission of data signals is a pair of 8 bit data bus pins, and the needed partial data information of FPGA transfers in the storer of FPGA by described data bus pin.

6, the communication interface based on FPGA according to claim 1 is characterized in that, the function pin of described transmission power supply comprises the pin and a pair of ground pin of a pair of transmission 5V power supply at least.

7, the communication interface based on FPGA according to claim 6 is characterized in that, described grounding function pin is four pairs.

8, according to each described communication interface based on FPGA in the claim 1 to 6, it is characterized in that described interface also comprises at least one pair of reserved pin, described interface is by the pin function of described reserved pin expansion interface.

9, the communication interface based on FPGA according to claim 8 is characterized in that, described interface is the socket or the plug of double 40 pins; FPGA and processor be the socket by corresponding plug or socket and described interface or plug is corresponding is connected respectively; Wherein, the contact pin of described plug adopts gilding to make.

10, the communication interface based on FPGA according to claim 1 is characterized in that, described processor is microcontroller MCU.