CN201159889Y - Switch type multi-BIOS selection circuit - Google Patents

Switch type multi-BIOS selection circuit Download PDF

Info

Publication number
CN201159889Y
CN201159889Y CNU2008200925676U CN200820092567U CN201159889Y CN 201159889 Y CN201159889 Y CN 201159889Y CN U2008200925676 U CNU2008200925676 U CN U2008200925676U CN 200820092567 U CN200820092567 U CN 200820092567U CN 201159889 Y CN201159889 Y CN 201159889Y
Authority
CN
China
Prior art keywords
bios
circuit
chip
pin
write
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CNU2008200925676U
Other languages
Chinese (zh)
Inventor
区展鹏
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TAIHUI ELECTRONICS (SHENZHEN) CO Ltd
Original Assignee
TAIHUI ELECTRONICS (SHENZHEN) CO Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by TAIHUI ELECTRONICS (SHENZHEN) CO Ltd filed Critical TAIHUI ELECTRONICS (SHENZHEN) CO Ltd
Priority to CNU2008200925676U priority Critical patent/CN201159889Y/en
Application granted granted Critical
Publication of CN201159889Y publication Critical patent/CN201159889Y/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Landscapes

  • Stored Programmes (AREA)

Abstract

The utility model discloses a switch type multi-BIOS selecting circuit, which comprises a BIOS readable and unwritable chip U55 and at least one BIOS read-write chip U54, the BIOS readable and unwritable chip U55 and the BIOS read-write chip U54 are connected with a BIOS selecting and locking circuit, and the BIOS selecting and locking circuit is connected with a mainboard input control signal RESET through a BIOS switching circuit. Compared with the prior art, the selecting circuit can realize the switching between two BIOS chips and complete the data restoration by only pressing a RESET key when a computer fails in exceeding frequency, thereby greatly facilitating the frequency exceeding for users.

Description

The many BIOS of switching regulator select circuit
Technical field:
The utility model relates to the computer display card application technology, and the many BIOS of particularly a kind of switching regulator select circuit.
Background technology:
Fast development along with computer technology, the user is also more and more higher to the requirement of computer hardware, especially some game players have higher requirement to video card, often satisfy the demand by the video card overclocking, overclocking is improper then may to cause the video card instability, the flower machine, even can't normal boot-strap, thereby the performance of video card can't better be brought into play.
For this reason, some manufacturers are integrated two BIOS chips on video card, to satisfy user's overclocking requirement, yet these two BIOS chips can refresh, in case data is lost, to cause the computing machine can't operate as normal, and need be by manually stirring selector switch when between the two, switching, it is very inconvenient to operate.
Summary of the invention:
For this reason, the purpose of this utility model is to provide the many BIOS of a kind of switching regulator to select circuit, this circuit comprises a BIOS storage chip and at least one read-write BIOS chip, can select circuit to select by BIOS between the two, has improved the job stability of video card greatly.
For achieving the above object, the utility model is mainly by the following technical solutions:
The many BIOS of a kind of switching regulator select circuit, comprising that BIOS is readable can not write chip U55 and the read-write chip U54 of at least one BIOS, the readable chip U55 that can not write of described BIOS selects lock-in circuit to be connected with read-write chip U54 of BIOS and BIOS, and described BIOS selects lock-in circuit to be connected with mainboard input control signal RESET by the BIOS commutation circuit.
Wherein said BIOS selects lock-in circuit to comprise chip U113 and J6, readable 5 pin, 2 pin and 6 pin that can not write chip U55 and the read-write chip U54 of BIOS of described BIOS are connected with 14 pin of chip U113 by GPU-GPIO, 1 pin of described U55 is connected with 5 pin of U113, and 1 pin of described U54 is connected with 4 pin of U113.
Wherein said J6 is connected with the BIOS commutation circuit, and described BIOS commutation circuit comprises AND circuit U114A, U114B and gate circuit U115A, U115B, U116A, U116B, and is connected with mainboard input control signal RESET by this commutation circuit.
The utility model is provided with on the computer video card that BIOS is readable can not to write chip and the read-write chip of at least one BIOS, thereby make the user unstable at video card overclocking failure or video card and under the situation that causes to start shooting, can be by carrying out the switching between the BIOS chip between the computer RESET button, realization recovers the data of read-write BIOS chip, and the whole operation process is simple and convenient.
Description of drawings:
Fig. 1 is the utility model circuit theory diagrams.
Embodiment:
For setting forth the purpose of this utility model and technique effect, the utility model is described in further details below in conjunction with circuit diagram and specific embodiment.
See also shown in Figure 1, the utility model is that example describes with two BIOS storage FLASH chips, this programme circuit mainly selects the commutation circuit between lock-in circuit, two BIOS to form by two BIOS storage FLASH chips and BIOS, wherein to be that BIOS is readable can not write the FLASH chip to U55, U54 is the read-write FLASH chip of BIOS, these two chips are mainly used in data on file, and described U55 selects lock-in circuit to be connected with U54 by GPU-GPIO and BIOS.
Described BIOS selection lock-in circuit mainly includes and comprises chip U113 and J6, its chips U113 is used for the BIOS selection and locks, readable 5 pin, 2 pin and 6 pin that can not write chip U55 and the read-write chip U54 of BIOS of described BIOS are connected with 14 pin of chip U113 by GPU-GPIO, 1 pin of described U55 is connected with 5 pin of U113, and 1 pin of described U54 is connected with 4 pin of U113.15 of the pins of chip U113 are connected with commutation circuit between two BIOS by chip J6.
Commutation circuit between wherein said two BIOS mainly includes gate circuit U114A, U114B and gate circuit U115A, U115B, U116A, U116B, and is connected with mainboard input control signal RESET by this commutation circuit.Can realize two switchings between the BIOS by above chip.
Below in conjunction with circuit principle of work of the present utility model is described.
When the user needs overclocking, can brush the read-write FLASH chip of BIOS U54, owing to select and add the 3rd of lock core chip U113,13,14 pin are low level, the 4th pin is a high level, thereby U54Enable, but when in a single day U54 goes wrong, in the time of can not starting shooting, then can reduce by the following method: after start, press the Reset key on the cabinet in the 15S, this Reset key is connected with the BIOS commutation circuit by mainboard, the the 2nd and the 10th pin of U115 is a high level in the BIOS commutation circuit at this moment, because 14 of U115,15 pin and 6, have Delay (RC discharge circuit) on 7 pin, thereby triggering U116 makes its 5th pin go out a high level, make 1 of U114,2 pin are high level, its the 3rd pin output high level, trigger U116 and make its 8th pin output low level, by 5 of J6,6 pin trigger the 15th pin of U113, thereby making its 5th pin is high level, make U55 selected, BIOS Flash just can realize switching, just can reduce BIOS after DOS or the system by entering, be failure to actuate owing to the RC discharge circuit when upgrading BIOS, the 5th of J6,6 pin quite open circuit, U113 can only export high level by the 4th pin, so the BIOS of reduction meeting covers the BIOS of overclocking failure before automatically, makes the trouble and worry that has no of overclocking change.
More than select circuit to be described in detail to the many BIOS of a kind of switching regulator provided by the utility model, used specific case herein principle of the present utility model and embodiment are set forth, the explanation of above embodiment just is used for helping to understand method of the present utility model and core concept thereof; Simultaneously, for one of ordinary skill in the art, according to thought of the present utility model, the part that all can change in specific embodiments and applications, in sum, this description should not be construed as restriction of the present utility model.

Claims (3)

1, the many BIOS of a kind of switching regulator select circuit, it is characterized in that: comprising that BIOS is readable can not write chip U55 and the read-write chip U54 of at least one BIOS, the readable chip U55 that can not write of described BIOS selects lock-in circuit to be connected with read-write chip U54 of BIOS and BIOS, and described BIOS selects lock-in circuit to be connected with mainboard input control signal RESET by the BIOS commutation circuit.
2, the many BIOS of switching regulator according to claim 1 select circuit, it is characterized in that: described BIOS selects lock-in circuit to comprise chip U113 and J6, readable 5 pin, 2 pin and 6 pin that can not write chip U55 and the read-write chip U54 of BIOS of described BIOS are connected with 14 pin of chip U113 by GPU-GPIO, 1 pin of described U55 is connected with 5 pin of U113, and 1 pin of described U54 is connected with 4 pin of U113.
3, the many BIOS of switching regulator according to claim 2 select circuit, it is characterized in that: described J6 is connected with the BIOS commutation circuit, described BIOS commutation circuit comprises AND circuit U114A, U114B and gate circuit U115A, U115B, U116A, U116B, and is connected with mainboard input control signal RESET by this commutation circuit.
CNU2008200925676U 2008-03-13 2008-03-13 Switch type multi-BIOS selection circuit Expired - Fee Related CN201159889Y (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CNU2008200925676U CN201159889Y (en) 2008-03-13 2008-03-13 Switch type multi-BIOS selection circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CNU2008200925676U CN201159889Y (en) 2008-03-13 2008-03-13 Switch type multi-BIOS selection circuit

Publications (1)

Publication Number Publication Date
CN201159889Y true CN201159889Y (en) 2008-12-03

Family

ID=40110474

Family Applications (1)

Application Number Title Priority Date Filing Date
CNU2008200925676U Expired - Fee Related CN201159889Y (en) 2008-03-13 2008-03-13 Switch type multi-BIOS selection circuit

Country Status (1)

Country Link
CN (1) CN201159889Y (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103530177A (en) * 2013-08-14 2014-01-22 南通腾启电子商务有限公司 Computer device provided with multiple BIOSs
TWI448880B (en) * 2012-04-02 2014-08-11 Hon Hai Prec Ind Co Ltd Power-on selecting circuit
CN105867568A (en) * 2015-01-19 2016-08-17 龙芯中科技术有限公司 Circuit realizing switching among different chips, and computer equipment
CN109144757A (en) * 2017-06-28 2019-01-04 环达电脑(上海)有限公司 Mainboard with firmware defencive function

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI448880B (en) * 2012-04-02 2014-08-11 Hon Hai Prec Ind Co Ltd Power-on selecting circuit
CN103530177A (en) * 2013-08-14 2014-01-22 南通腾启电子商务有限公司 Computer device provided with multiple BIOSs
CN105867568A (en) * 2015-01-19 2016-08-17 龙芯中科技术有限公司 Circuit realizing switching among different chips, and computer equipment
CN105867568B (en) * 2015-01-19 2019-03-05 龙芯中科技术有限公司 A kind of circuit and computer equipment for realizing different chip chamber switchings
CN109144757A (en) * 2017-06-28 2019-01-04 环达电脑(上海)有限公司 Mainboard with firmware defencive function

Similar Documents

Publication Publication Date Title
CN201041656Y (en) CMOS cleaning circuit
CN103279203B (en) Key reuse method and multifunctional key
CN201159889Y (en) Switch type multi-BIOS selection circuit
CN108090006A (en) A kind of method of one key switching PCIE Switch operating modes
CN102200916A (en) Electronic equipment, configurable member and method for storing configuration information of configurable member
US7062585B2 (en) Memory card for integrating the USB interface and an adaptor for the memory card
US8230206B2 (en) Bios parameter erasing method and apparatus applied to computer system
CN100374974C (en) Method for implementing USB port screening control
CN101645016A (en) System for switching BIOS set values
CN104063133A (en) Method and system of one-key switchover of interfaces
CN2735426Y (en) Real-time clock feed circuit capable of clearing CMOS settings
EP3012829A1 (en) Display circuit of switchable external display ports
CN212723999U (en) BIOS and BMC serial port information capturing system based on server uninterrupted power supply
CN201352461Y (en) Flash memory burning device
CN101359298A (en) Method for removing internal memory with BIOS and computer system thereof
CN102854417A (en) Master test board and testing method thereof
CN101387966A (en) Computer equipment with BIOS selection function
CN210295083U (en) Display board card USB peripheral hardware connecting system
CN1336593A (en) Secret related computer
US20080191014A1 (en) Multifunctional card reader
CN220983880U (en) Multi-program single-port burning circuit and device
CN105516495A (en) Method for quickly starting camera and mobile terminal
CN110633002A (en) Processing circuit and power management method thereof
CN108693976A (en) Transcripter
CN104935752A (en) Method and device for starting mobile terminal, and mobile terminal

Legal Events

Date Code Title Description
C14 Grant of patent or utility model
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20081203

Termination date: 20140313