CN103530177A

CN103530177A - Computer device provided with multiple BIOSs

Info

Publication number: CN103530177A
Application number: CN201310352127.5A
Authority: CN
Inventors: 陈玉康
Original assignee: NANTONG TENGQI E-COMMERCE Co Ltd
Current assignee: NANTONG TENGQI E-COMMERCE Co Ltd
Priority date: 2013-08-14
Filing date: 2013-08-14
Publication date: 2014-01-22

Abstract

The invention relates to a computer device, in particular to a computer device provided with multiple BIOSs. The corresponding BIOSs can be used according to needs so that the danger that the computer device crashes when the BIOSs are wrong can be avoided. The computer device provided with the multiple BIOSs is mainly provided, an internal storage is provided with the multiple BIOSs, the needed BIOSs are selected for use through a selection device, and the shortcoming that a traditional computer only using a single BIOS cannot be operated when the only BIOS goes wrong is overcome.

Description

The computer equipment with a plurality of basic input systems

Technical field

The present invention is about a kind of computer equipment, particularly relevant for a kind of computer equipment with a plurality of basic input systems (BI0s), can use as required corresponding BI0S, to avoid that the danger that computer equipment crashes occurs because lying prone 0S mistake.

Background technology

In general computer system, no matter be notebook or desk-top computer, the BI0S device using all adopts the design of flash memory (flash memory).Yet it only has single BI0S data.The BI0S data necessary base program that is computer system when start, if during flash memory access failure, can be because normal access BI0S data and cause computer system to move.

Under this situation, because computer system cannot normally be used because of BI0S content false, or even in the state in crashing, user cannot directly be modified to correct content from computer system by BI0S data.If now will make the computer system can normal running, computing machine must be taken apart, and again by correct BI0S data by burning program again burned flash memory, or basic setting value when flash memory is discharged to recover to dispatch from the factory.In any case, be all the quite work of trouble of part for the user, show that current conventional art haves much room for improvement.

No. 5964873, invent in (Choi et.a1) people's such as artificial Qiao Yi United States Patent (USP), a kind of renewal is provided---the method for ROM (read-only memory) Basic Input or Output System (BIOS) (ROM BI0S), and in the artificial United States Patent (USP) of breathing out Mo Dengren (Harmer et.a1) of No. 5835760, invention, described one method and the device of BI0S to main frame is provided.Yet above-mentioned known technology does not all disclose relevant for the computer equipment with a plurality of BI0S.

Summary of the invention

In view of this, fundamental purpose of the present invention is to provide a kind of computer equipment with a plurality of basic input systems, its internal storage has a plurality of BI0S, and can be by a selecting arrangement and the required BI0S of choice for use, with the shortcoming of avoiding only using the traditional computer of single BI0S cannot operate because problem occurs only BI0S.

For achieving the above object, a kind of computer equipment with a plurality of basic input systems of the present invention, is applicable to as required and switches and use a plurality of BI0S, comprising: a selecting arrangement, for providing, corresponding to one of described BI0S, select signal; One memory storage, is coupled to described selecting arrangement, for storing described BI0S data, and exports corresponding BI0S data according to described selection signal; And a CPU (central processing unit), be coupled to described memory storage, for receiving exported BI0S data, for computer equipment, use.

In addition, according in computer equipment of the present invention, if memory storage of the present invention has 4 groups of BI0S, described selecting arrangement comprises: the first Sheffer stroke gate, controls signal to described memory storage for receiving the first input signal and the second input signal and exporting first; The second Sheffer stroke gate, for receiving described the first input signal, described the second input signal and the 3rd input signal and exporting the first comparison signal; The 3rd Sheffer stroke gate, for receiving described the second input signal, described the 3rd input signal and the 4th input signal and exporting the second comparison signal; With door, for receiving described the first comparison signal and the second comparison signal, and export one second and control signal to described memory storage.

By the structure of described selecting arrangement, can provide four group selection signals to select its corresponding BI0S data and to export it according to the signal of input.Accompanying drawing explanation

Fig. 1 relates to the circuit block diagram of a preferred embodiment of the present invention

Fig. 2 is the outside drawing of display chip AT49F008, and describes its each pin bit number and function

Fig. 3 is the circuit structure diagram of display input device

Fig. 4 shows according to selecting arrangement 11 its input signal I0-I3 shown in Fig. 3, with the truth table of the control signal relation of exporting

Embodiment

For further illustrating described object of the present invention, design feature and effect, below with reference to accompanying drawing, ground the present invention is described in detail.

Consult Fig. 1, Fig. 1 relates to the circuit block diagram of a preferred embodiment of the present invention.According to the embodiment of the present invention, be to provide a kind of computer equipment with a plurality of basic input systems, its inner memory storage 12 has a plurality of BI0S, and can be by a selecting arrangement 11 and the required BI0S of choice for use.It is below the structural relation of describing respectively its each parts.

Selecting arrangement 11, for providing the selection signal corresponding to required BI0S according to action need.In the present embodiment, selecting arrangement 11 is the structure configurations that adopt as shown in Figure 3.The structure of selecting arrangement 11 comprises the first Sheffer stroke gate 31, for receiving the first input signal I0 and the second input signal I1, exports the first control signal CTRLl8 to memory storage 12; The second Sheffer stroke gate 32, for receiving described the first input signal I0, the second input signal I1, and the 3rd input signal I2, and export the first comparison signal; The 3rd Sheffer stroke gate 33, for receiving the second input signal I1,, the 3rd input signal I2: and the 4th input signal I3 export the second comparison signal; With door 34, for receiving described the first comparison signal and the second comparison signal, and export the second control signal CTRLl9 to memory storage 12.In the present embodiment, I0-I3, control by the switch (361-364) shown in Fig. 3, controlled respectively, use the outputting level that changes the first control signal CTRLl8 and the second control signal CTRLl9.

Memory storage 12, is coupled to described selecting arrangement 11, for storing described BI0S, and exports corresponding BI0S data according to described selection signal.In this embodiment, memory storage 12 is a flash memory (flash memory), and meanwhile, the present embodiment is that to take memory storage 12 be example as storing the flash memory of 4 groups of BI0S data, its chip number is AT49F008 or AT49F8192, at this, is to take AT49F008 as example.Consult Fig. 2, Fig. 2 is the outside drawing of display chip AT49F008, and describes its each pin bit number and function.Wherein pin position 22 is chip enable signal (CE) (Chip Enable), and pin position 24 is output enable signal (0E) (0utput Enable), and pin position 9 is for writing enable signal (WE) (Write Enable).Pin position 13 and pin position 37 receive respectively the signal of CTRLl8 and CTRLl9, and according to the signal of its input, determine the BI0S of output, finally by being exported by SDO-SD7.

In Fig. 4, show according to selecting arrangement 11 its input signal I0-I3 shown in Fig. 3, with the truth table of the control signal relation of exporting.As shown in the figure, by controlling I0-I3, can make control signal (CTRLl8, CTRLl9) be (0,0), (0,1), (1,0), the form such as (1,1), and these four kinds of forms are to correspond respectively to four kinds of BI0S that are stored in memory storage 12.Memory storage 12 is selected BI0S corresponding to output according to received control signal (CTRLl8, CTRLl9) by SDO-SD7.

CPU (central processing unit) 13 is to be coupled to memory storage 12 by data bus, the BI0S data of exporting for receiving/storing device 12 is used for CPU (central processing unit) (CPU) or other computer equipment, at this, CPU (central processing unit) 13 can be led to by data bus and other peripherals equally.

User, when this computer equipment of operation, if while finding computing machine flash memory access BI0S data failure or the content false of BI0S, can cause the situation of computer system deadlock conventionally.In conventional art, user must take complicated action can make flash memory normal access BI0S data or BI0S content modification that this is made a mistake is correct content, can make computer equipment normal running.

Yet, according to the computer equipment of the embodiment of the present invention, because it has a plurality of BI0S, therefore when one of them BI0S makes a mistake, now only need computer equipment shutdown, and the switch in manual switchover selecting arrangement 11 is to change the control signal of output (CTRLl8, CTRLl9), and memory storage 12 can be exported other BI0S data according to received control signal, so that computer equipment is able to normal running.

Certainly, those of ordinary skill in the art will be appreciated that, above embodiment is only for the present invention is described, and be not used as limitation of the invention, as long as within the scope of connotation of the present invention, the variation of the above embodiment, modification all will be dropped in the scope of the claims in the present invention book.

Claims

1. a computer equipment with a plurality of basic input systems, be applicable to switch and use a plurality of Basic Input or Output System (BIOS)s as required, it is characterized in that, comprising: a selecting arrangement (11), for the selection signal corresponding to each Basic Input or Output System (BIOS) is provided; One memory storage (12), is coupled to selecting arrangement (11), for storing a plurality of Basic Input or Output System (BIOS)s, and exports corresponding Basic Input or Output System (BIOS) according to described selection signal; One CPU (central processing unit) (13), is coupled to described memory storage (12), for receiving exported Basic Input or Output System (BIOS), for computer equipment, uses.

2. a kind of computer equipment with a plurality of basic input systems as claimed in claim 1, is characterized in that: described memory storage (12) stores four Basic Input or Output System (BIOS) data.

3. a kind of computer equipment with a plurality of basic input systems as claimed in claim 2, it is characterized in that, described selecting arrangement (11) comprising: the first Sheffer stroke gate (31), be used for receiving the first input signal and the second input signal, and export first and control signal to described memory storage (12); The second Sheffer stroke gate (32), for receiving described the first input signal, described the second input signal and the 3rd input signal and exporting the first comparison signal; The 3rd Sheffer stroke gate (33), for receiving described the second input signal, described the 3rd input signal and the 4th input signal and exporting the second comparison signal; With door (34), for receiving described the first comparison signal and the second comparison signal, and export one second and control signal to described memory storage (12).

4. a kind of computer equipment with a plurality of basic input systems as claimed in claim 3, is characterized in that: the first input signal that described selecting arrangement (11) receives, the second input signal, the 3rd input signal, the 4th input signal are controlled by a switch.

5. a kind of computer equipment with a plurality of basic input systems as claimed in claim 3, it is characterized in that: described memory storage (12) has two input ends, for receiving respectively described the first control signal and the second control signal to obtain described selection signal.

6. a kind of computer equipment with a plurality of basic input systems as claimed in claim 1, is characterized in that: described memory storage (12) is flash memory AT49F008.

7. a kind of computer equipment with a plurality of basic input systems as claimed in claim 1, is characterized in that: the Basic Input or Output System (BIOS) data that described memory storage (12) is exported is to be sent to described CPU (central processing unit) (13) by a data bus.

8. a kind of computer equipment with a plurality of basic input systems as claimed in claim 7, is characterized in that: described data bus is to be coupled to other peripherals.