CN201118603Y - Pseudo satellite baseband signal generator - Google Patents
Pseudo satellite baseband signal generator Download PDFInfo
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- CN201118603Y CN201118603Y CNU200720076280XU CN200720076280U CN201118603Y CN 201118603 Y CN201118603 Y CN 201118603Y CN U200720076280X U CNU200720076280X U CN U200720076280XU CN 200720076280 U CN200720076280 U CN 200720076280U CN 201118603 Y CN201118603 Y CN 201118603Y
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Abstract
Disclosed is a signal sending device, relating to the electronic technical field, in particular to a pseudo-satellite baseband signal generator used for producing and controlling the medium-frequency signals similar to the pseudo-satellite signals in the GPS satellite signal format, and used for simulating satellite signals and realizing the application such as pseudo-satellite positioning. The signal sensing device comprises a field programmable gate array (FPGA) and medium-frequency signal module and four independent integrated pseudo-satellite signal channels; the core of the entire system is integrated in a field programmable gate array (FPGA) chip; the soft core and the four pseudo-satellite peripheries form the baseband signal generator. The utility model mainly solves the technical problems about how to integrate the entire system core into a field programmable gate array (FPGA) chip. The utility model has the advantages that the format and the content of the output signals of the device are united with the GPS signals; the reliability and the controllability are improved; and the signal sending device is characterized by low cost, high precision, flexible control and convenient operation.
Description
Technical field
The utility model relates to the apparatus for transmitting signal of electronic technology field, outstanding a kind of modern means of science and technology of utilizing of purport, be used for the intermediate-freuqncy signal that generation and control are similar to the pseudo satellite, pseudolite signal of GPS (Global Position System) GPS (Global Positiong System) satellite-signal form, be used for the device of multinomial application such as satellite-signal simulation and realization pseudo satellite, pseudolite location.
Background technology
Pseudo satellite, pseudolite is as the term suggests be a Satellite Simulation device, and its major function is an analog satellite, here is the simulating GPS satellite, emission and the living satellite navigation signals of gps signal form.The appearance of pseudo satellite, pseudolite is evening, GPS System in USA build as yet finish before, just use pseudo satellite, pseudolite to carry out the analogue test of GPS.In recent years, there are many researchs at pseudo satellite, pseudolite countries in the world, and all there are ripe pseudo satellite, pseudolite group network system in Korea S and Finland.Also there are many researchs to pseudo satellite, pseudolite in China, and great majority are to use 1～2 pseudo satellite, pseudolite to realize that the zone of satellite navigation system strengthens.
And the realization of domestic pseudo satellite, pseudolite body does not have ripe product, uses the product of external one or two companies of the general dependence on import of pseudo satellite, pseudolite both at home and abroad.
Summary of the invention
In order to overcome above-mentioned weak point, main purpose of the present utility model aims to provide a kind of by baseband signal generation and control logic circuit mechanism, finish the realization and the controlling organization of false satellite baseband signal, the generation of pseudo satellite, pseudolite signal can be the handled easily person controlled on computers flexibly, the false satellite baseband signal maker of parameters can be moved again.
The technical problems to be solved in the utility model is: mainly solve how the whole system core is integrated in problem in an on-site programmable gate array FPGA (the Field Programmable GateArray) chip; Solve the digital circuit how to realize specific logical function realizes that the CA sign indicating number generates, the carrier wave output problem of navigation message output and Direct Digital Frequency Synthesizers DDS (DirectDigital Synthesis), solve the order of the host computer of how will decode and according to relevant technologies problems such as the complicated controlled function of this order realization.
The technical scheme that its technical problem that solves the utility model adopts is: this device is made up of parts such as programmable gate array, bus, interface, antenna, logical circuit, inverter, register, memory, timer manager, delay controller, digital frequency synthesizer, interruption logging device and D/A converters, and this device comprises at least:
On-site programmable gate array FPGA, serial line interface, boundary scan interface, memory chip, the input of 75M crystal oscillator clock, the high steady clock input of 20.46M, digital-to-analogue conversion and intermediate-freuqncy signal module, and integrated four tunnel pseudo satellite, pseudolite signalling channel independently, the digital circuit of logic function and embedded soft nuclear are formed an embedded SOC (system on a chip), the whole system core is integrated in the on-site programmable gate array FPGA chip, and soft nuclear and four road pseudo satellite, pseudolite peripheral hardwares are combined as a baseband signal maker together; Wherein:
The input of one on-site programmable gate array FPGA module is connected with the output of 75M crystal oscillator clock input and the high steady clock input module of 20.46M respectively, the output of on-site programmable gate array FPGA module respectively with D/A converter module in the input of digital-to-analogue conversion A, digital-to-analogue conversion B, digital-to-analogue conversion C and digital-to-analogue conversion D walk abreast mutually and be connected;
The output of digital-to-analogue conversion A, digital-to-analogue conversion B, digital-to-analogue conversion C and digital-to-analogue conversion D respectively with the intermediate-freuqncy signal module in parallel mutually connection of input of intermediate-freuqncy signal A, intermediate-freuqncy signal B, intermediate-freuqncy signal C intermediate-freuqncy signal D;
One serial line interface is connected with the corresponding port of on-site programmable gate array FPGA module by reception, the transmit port of chip;
One border scan interface is connected by the corresponding port of interface with the on-site programmable gate array FPGA module;
The input/output terminal of one memory chip interconnects with the I/O of on-site programmable gate array FPGA module respectively by bus;
One on-site programmable gate array FPGA module mainly is made up of the soft nuclear of microblaze flush bonding processor, pseudo satellite, pseudolite core logic circuit, digital dock manager A, digital dock manager B, interrupt control unit, serial ports control module and Memory Controller Hub, and the clock signal of the digital dock manager DCM (Digital ClockManager) of this on-site programmable gate array FPGA internal resource is directly delivered to the corresponding port of the soft core module of microblaze flush bonding processor; The logical signal of pseudo satellite, pseudolite core logic circuit is delivered to each corresponding port of the soft core module of microblaze flush bonding processor respectively;
The output signal of one digital dock manager A is delivered to the input of the soft nuclear of microblaze flush bonding processor, and 75M crystal oscillator clock input signal is delivered to the input of digital dock manager A;
The output signal of one digital dock manager B is delivered to the clock in the pseudo satellite, pseudolite core logic circuit and the input of pseudo satellite, pseudolite administration module, and the high steady clock input signal of 20.46M is delivered to the input of digital dock manager B;
The interrupt signal of one interrupt control unit output is delivered to the input of the soft nuclear of microblaze flush bonding processor, the output interrupt signal 0 of serial ports control module is delivered to the input of interrupt control unit, and the output interrupt signal 1 of clock in the pseudo satellite, pseudolite core logic circuit and pseudo satellite, pseudolite administration module is delivered to the input of interrupt control unit;
The input/output terminal of one serial ports control module is connected with the corresponding port of serial interface module, reception is from the control command of host computer, can send interrupt signal 0 after receiving order, the output transmission of serial ports control module sends signal, and the I/O of serial ports control module is connected with the corresponding port of the soft core module of microblaze flush bonding processor respectively by peripheral bus on the sheet;
The input/output terminal of one Memory Controller Hub is connected by the corresponding port of local bus memory with the soft nuclear of microblaze flush bonding processor.
Be provided with pseudo satellite, pseudolite peripheral hardware and clock and pseudo satellite, pseudolite administration module in the pseudo satellite, pseudolite core logic circuit of described false satellite baseband signal maker, the input/output terminal of this pseudo satellite, pseudolite core logic circuit is connected with the corresponding port of the soft core module of microblaze flush bonding processor respectively by peripheral bus on the sheet; The output of pseudo satellite, pseudolite core logic circuit interconnects by the input of peripheral bus on the sheet and analog-digital chip, wherein:
One pseudo satellite, pseudolite peripheral hardware respectively by four the tunnel independently pseudo satellite, pseudolite peripheral hardware A, pseudo satellite, pseudolite peripheral hardware B, pseudo satellite, pseudolite peripheral hardware C and pseudo satellite, pseudolite peripheral hardware D form, the output of this pseudo satellite, pseudolite peripheral hardware interconnects by the input of peripheral bus on the sheet and analog-digital chip;
The pseudo noise code clock of one clock and pseudo satellite, pseudolite administration module output, navigation message clock and digital frequency synthesizer clock clock signal are delivered to four tunnel each input of pseudo satellite, pseudolite peripheral hardware A, pseudo satellite, pseudolite peripheral hardware B, pseudo satellite, pseudolite peripheral hardware C and pseudo satellite, pseudolite peripheral hardware D independently respectively; The resetting and start on the global semaphore end that two control signals are delivered to four tunnel independence pseudo satellite, pseudolite peripheral hardwares respectively of clock and pseudo satellite, pseudolite administration module output.
The pseudo satellite, pseudolite peripheral hardware of described false satellite baseband signal maker is provided with four tunnel independence pseudo satellite, pseudolite structures that different base address form, the pseudo satellite, pseudolite peripheral hardware of each road independence pseudo satellite, pseudolite structure comprises at least: the CA sign indicating number is selected maker, navigation message shift unit, digital frequency synthesizer carrier wave maker, CA sign indicating number mask register and navigation message register, wherein:
The input that the CA sign indicating number is selected maker interconnects with the output of CA sign indicating number mask register and pseudo noise code clock signal respectively; The input of navigation message shift unit interconnects with the output of navigation message register and navigation message clock signal respectively; The input of digital frequency synthesizer carrier wave maker and the output of digital frequency synthesizer clock signal interconnect; CA sign indicating number mask register should be different offset addresss with the navigation message register pair;
The CA sign indicating number selects global semaphore connecting line and the start-up control signal end between maker and the digital frequency synthesizer carrier wave maker to interconnect; The CA sign indicating number selects the global semaphore connecting line and the reseting controling signal end of maker, navigation message shift unit and digital frequency synthesizer carrier wave maker to interconnect;
With after computing module is connected, the input with the binary phase shift keying modulation module is connected the output that the CA sign indicating number is selected maker and navigation message shift unit again via mould two; The output of digital frequency synthesizer carrier wave maker is connected with the input of binary phase shift keying modulation module; The clock signal one tunnel of binary phase shift keying modulation module is a digital-to-analogue conversion clock 0, export via inverter on another road, be digital-to- analogue conversion clock 1,12 figure place mould translation data of two-way clock signal and the output of binary phase shift keying modulation module export the respective input of analog-digital chip respectively to;
The interrupt request singal of one navigation message shift unit output is delivered to the input of clock and pseudo satellite, pseudolite administration module.
The clock of described false satellite baseband signal maker and pseudo satellite, pseudolite administration module are provided with four pseudo satellite, pseudolite peripheral hardware clock control logic modules, respectively corresponding four pseudo satellite, pseudolite peripheral hardwares, each pseudo satellite, pseudolite peripheral hardware clock control logic are provided with one group of time-delay control register and amount of delay register, carrier frequency delay controller and each frequency divider; Described clock and pseudo satellite, pseudolite administration module comprise three road signals at least:
The first via is provided with and starts and the command register module, startup and command register are imported read-write by the soft nuclear of microblaze flush bonding processor by peripheral bus on the sheet, start different according to the command word that writes with the output signal of command register, send out the signal that starts and reset respectively, this startup and the signal that resets are connected respectively to the global semaphore connecting line of four pseudo satellite, pseudolite peripheral hardwares;
The second the tunnel is provided with pseudo satellite, pseudolite peripheral hardware clock control logic module;
Third Road is provided with interruption logging device module, and this module is collected the interruption input signal of four pseudo satellite, pseudolites respectively, and interrupt request singal is delivered to the input of interruption logging device, and after collection was neat, the output signal of this interruption logging device was an interrupt signal 1.
Each pseudo satellite, pseudolite peripheral hardware clock control logic module of described false satellite baseband signal maker is provided with pseudo satellite, pseudolite peripheral hardware A time-delay control register, pseudo satellite, pseudolite peripheral hardware A amount of delay register, carrier frequency delay controller, 80 frequency divisions and 20460 frequency division modules at least, wherein:
The output signal of one group of pseudo satellite, pseudolite peripheral hardware A time-delay control register and pseudo satellite, pseudolite peripheral hardware A amount of delay register is delivered to the input of carrier frequency delay controller respectively, and the input signal of the high steady clock of 81.84M is delivered to the input of carrier frequency delay controller; The output signal of carrier frequency delay controller passes out the required digital frequency synthesizer clock of pseudo satellite, pseudolite peripheral hardware, navigation message clock and three kinds of clock signals of pseudo noise code clock along separate routes by the counter frequency division of 80 frequency divisions and 20460 frequency division modules respectively.
The beneficial effects of the utility model are: this device has been realized a kind of low cost, degree of precision, control false satellite baseband signal maker flexible, easy to use; Its output signal is except carrier wave is the 10.23M intermediate frequency, and form, content and gps signal are consistent; With the gps carrier frequency of output signal up-conversion to 1575.42M, can by antenna launch and gps signal in full accord; The whole system core is integrated in the fpga chip, has saved the pseudo satellite, pseudolite spending of hardware, and development time and expense have improved reliability and controllability, is fit to very much the research of pseudo satellite, pseudolite indoor positioning and as the signal source of satellite navigation technical research; Has the simple and direct advantage such as effectively of convenient, flexible, control.
Description of drawings
Below in conjunction with drawings and Examples the utility model is further specified.
Accompanying drawing 2 is the primary structure schematic diagram of the utility model field programmable gate array core;
Accompanying drawing 3 is the utility model pseudo satellite, pseudolite peripheral module structural representation;
Accompanying drawing 4 is the utility model clock and pseudo satellite, pseudolite administration module structural representation;
Label declaration in the accompanying drawing:
The 1-on-site programmable gate array FPGA; 14-clock and pseudo satellite, pseudolite administration module;
The 2-serial line interface; 141-resets;
The 3-boundary scan interface; 142-starts;
The 4-memory chip; 143-pseudo noise code clock;
The input of 5-75M crystal oscillator clock; 144-navigation message clock;
6-20.46M high steady clock input; 145-digital frequency synthesizer clock;
The 7-digital-to-analogue conversion; The 146-interrupt request singal;
71-digital-to-analogue conversion A; 1401-starts and command register;
72-digital-to-analogue conversion B; The 1402-pseudo satellite, pseudolite peripheral hardware A control register of delaying time;
73-digital-to-analogue conversion C; 1403-pseudo satellite, pseudolite peripheral hardware A amount of delay register;
74-digital-to-analogue conversion D; 1404-interruption logging device;
The 8-intermediate-freuqncy signal; 1405-carrier frequency delay controller;
81-intermediate-freuqncy signal A; The 1406-80 frequency division;
82-intermediate-freuqncy signal B; The 1407-20460 frequency division;
83-intermediate-freuqncy signal C 15-digital dock manager A;
84-intermediate-freuqncy signal D; 16-digital dock manager B;
The soft nuclear of 11-microblaze flush bonding processor; The 17-interrupt control unit;
Peripheral bus on the 12-sheet; 18-serial ports control module;
13-pseudo satellite, pseudolite peripheral hardware; The 19-local bus memory;
131-pseudo satellite, pseudolite peripheral hardware A; The 20-Memory Controller Hub;
132-pseudo satellite, pseudolite peripheral hardware B; 30-pseudo satellite, pseudolite core logic circuit;
133-pseudo satellite, pseudolite peripheral hardware C; 140-pseudo satellite, pseudolite peripheral hardware clock control logic;
134-pseudo satellite, pseudolite peripheral hardware D;
The 1301-CA sign indicating number is selected maker;
1302-navigation message shift unit;
1303-digital frequency synthesizer carrier wave maker;
1304-mould two Hes;
The 1305-inverter;
The modulation of 1306-binary phase shift keying;
1307-CA sign indicating number mask register;
1308-navigation message register;
Embodiment
See also shown in the accompanying drawing 1,2,3,4, the utility model is made up of parts such as programmable gate array, bus, interface, antenna, logical circuit, inverter, register, memory, timer manager, delay controller, digital frequency synthesizer, interruption logging device and D/A converters, and this device comprises at least:
On-site programmable gate array FPGA 1, serial line interface 2, boundary scan interface 3, memory chip 4,75M crystal oscillator clock input 5, the high steady clock input 6 of 20.46M, digital-to-analogue conversion 7 and intermediate-freuqncy signal 8 modules, and integrated four tunnel pseudo satellite, pseudolite signalling channel independently, the digital circuit of logic function and embedded soft nuclear are formed an embedded SOC (system on a chip), the whole system core is integrated in on-site programmable gate array FPGA 1 chip, and soft nuclear and four road pseudo satellite, pseudolite peripheral hardwares are combined as a baseband signal maker together; Wherein:
The input of one on-site programmable gate array FPGA, 1 module is connected with the output that 75M crystal oscillator clock input 5 and the high steady clock of 20.46M are imported 6 modules respectively, the output of on-site programmable gate array FPGA 1 module respectively with digital-to-analogue conversion 7 modules in parallel mutually connection of input of digital-to-analogue conversion A71, digital-to-analogue conversion B72, digital-to-analogue conversion C73 and digital-to-analogue conversion D74;
The output of digital-to-analogue conversion A71, digital-to-analogue conversion B72, digital-to-analogue conversion C73 and digital-to-analogue conversion D74 respectively with intermediate-freuqncy signal 8 modules in parallel mutually connection of input of intermediate-freuqncy signal A81, intermediate-freuqncy signal B82, intermediate-freuqncy signal C83 intermediate-freuqncy signal D84;
One serial line interface 2 is connected with the corresponding port of on-site programmable gate array FPGA 1 module by reception, the transmit port of chip;
One border scan interface 3 is connected by the corresponding port of interface with on-site programmable gate array FPGA 1 module;
The input/output terminal of one memory chip 4 interconnects with the I/O of on-site programmable gate array FPGA 1 module respectively by bus;
One on-site programmable gate array FPGA, 1 module mainly is made up of the soft nuclear 11 of microblaze flush bonding processor, pseudo satellite, pseudolite core logic circuit 30, digital dock manager A15, digital dock manager B16, interrupt control unit 17, serial ports control module 18 and Memory Controller Hub 20, and the clock signal of the digital dock manager DCM of this on-site programmable gate array FPGA 1 internal resource is directly delivered to the corresponding port of soft nuclear 11 modules of microblaze flush bonding processor; The logical signal of pseudo satellite, pseudolite core logic circuit 30 is delivered to each corresponding port of soft nuclear 11 modules of microblaze flush bonding processor respectively;
The output signal of one digital dock manager A15 is delivered to the input of the soft nuclear 11 of microblaze flush bonding processor, and 75M crystal oscillator clock is imported the input that 5 signals are delivered to digital dock manager A15;
The output signal of one digital dock manager B16 is delivered to the clock in the pseudo satellite, pseudolite core logic circuit 30 and the input of pseudo satellite, pseudolite administration module 14, and 20.46M is high, and steady clock is imported the input that 6 signals are delivered to digital dock manager B16;
The interrupt signal of one interrupt control unit, 17 outputs is delivered to the input of the soft nuclear 11 of microblaze flush bonding processor, the output interrupt signal 0 of serial ports control module 18 is delivered to the input of interrupt control unit 17, and the output interrupt signal 1 of clock in the pseudo satellite, pseudolite core logic circuit 30 and pseudo satellite, pseudolite administration module 14 is delivered to the input of interrupt control unit 17;
The input/output terminal of one serial ports control module 18 is connected with the corresponding port of serial line interface 2 modules, reception is from the control command of host computer, can send interrupt signal 0 after receiving order, the output transmission of serial ports control module 18 sends signal, and the I/O of serial ports control module 18 is connected with the corresponding port of soft nuclear 11 modules of microblaze flush bonding processor respectively by peripheral bus on the sheet 12;
The input/output terminal of one Memory Controller Hub 20 is connected by the corresponding port of local bus memory 19 with the soft nuclear 11 of microblaze flush bonding processor.
Be provided with pseudo satellite, pseudolite peripheral hardware 13 and clock and pseudo satellite, pseudolite administration module 14 in the pseudo satellite, pseudolite core logic circuit 30 of described false satellite baseband signal maker, the input/output terminal of this pseudo satellite, pseudolite core logic circuit 30 is connected with the corresponding port of soft nuclear 11 modules of microblaze flush bonding processor respectively by peripheral bus on the sheet 12; The output of pseudo satellite, pseudolite core logic circuit 30 interconnects by the input of peripheral bus on the sheet 12 with analog-digital chip, wherein:
One pseudo satellite, pseudolite peripheral hardware 13 respectively by four the tunnel independently pseudo satellite, pseudolite peripheral hardware A131, pseudo satellite, pseudolite peripheral hardware B132, pseudo satellite, pseudolite peripheral hardware C133 and pseudo satellite, pseudolite peripheral hardware D134 form, the output of this pseudo satellite, pseudolite peripheral hardware 13 interconnects by peripheral bus on the sheet 12 input with analog-digital chip;
The pseudo noise code clock 143 of one clock and pseudo satellite, pseudolite administration module 14 outputs, navigation message clock 144 and digital frequency synthesizer clock 145 clock signals are delivered to four tunnel each input of pseudo satellite, pseudolite peripheral hardware A131, pseudo satellite, pseudolite peripheral hardware B132, pseudo satellite, pseudolite peripheral hardware C133 and pseudo satellite, pseudolite peripheral hardware D134 independently respectively; Clock and pseudo satellite, pseudolite administration module 14 outputs reset 141 and start 142 two control signals and be delivered to respectively on the global semaphore end of four tunnel independence pseudo satellite, pseudolite peripheral hardwares 13.
The pseudo satellite, pseudolite peripheral hardware 13 of described false satellite baseband signal maker is provided with four tunnel independence pseudo satellite, pseudolite structures that different base address form, the pseudo satellite, pseudolite peripheral hardware 13 of each road independence pseudo satellite, pseudolite structure comprises at least: the CA sign indicating number is selected maker 1301, navigation message shift unit 1302, digital frequency synthesizer carrier wave maker 1303, CA sign indicating number mask register 1307 and navigation message register 1308, wherein:
The input that the CA sign indicating number is selected maker 1301 interconnects with the output of CA sign indicating number mask register 1307 and pseudo noise code clock 143 signals respectively; The input of navigation message shift unit 1302 interconnects with the output of navigation message register 1308 and navigation message clock 144 signals respectively; The output of the input of digital frequency synthesizer carrier wave maker 1303 and digital frequency synthesizer clock 145 signals interconnects; CA sign indicating number mask register 1307 corresponds to different offset addresss with navigation message register 1308;
The CA sign indicating number selects the global semaphore connecting line between maker 1301 and the digital frequency synthesizer carrier wave maker 1303 to interconnect with startup 142 control signal ends; The CA sign indicating number selects the global semaphore connecting line of maker 1301, navigation message shift unit 1302 and digital frequency synthesizer carrier wave maker 1303 and the 141 control signal ends that reset to interconnect;
The output that the CA sign indicating number is selected maker 1301 and navigation message shift unit 1302, is connected with the input that binary phase shift keying is modulated 1306 modules with after 1304 computing modules are connected via mould two again; The output of digital frequency synthesizer carrier wave maker 1303 is connected with the input that binary phase shift keying is modulated 1306 modules; The clock signal one tunnel that binary phase shift keying is modulated 1306 modules is a digital-to-analogue conversion clock 0, another road is via inverter 1305 outputs, be digital-to-analogue conversion clock 1, the 12 figure place mould translation data that two-way clock signal and binary phase shift keying are modulated 1306 modules output export the respective input of analog-digital chip respectively to;
The interrupt request singal 146 of one navigation message shift unit, 1302 outputs is delivered to the input of clock and pseudo satellite, pseudolite administration module 14.
The clock of described false satellite baseband signal maker and pseudo satellite, pseudolite administration module 14 are provided with four pseudo satellite, pseudolite peripheral hardware clock control logic 140 modules, respectively corresponding four pseudo satellite, pseudolite peripheral hardwares 13, each pseudo satellite, pseudolite peripheral hardware clock control logic 140 are provided with one group of time-delay control register and amount of delay register, carrier frequency delay controller and each frequency divider; Described clock and pseudo satellite, pseudolite administration module 14 comprise three road signals at least:
The first via is provided with and starts and command register 1401 modules, startup and command register 1401 are imported read-writes by the soft nuclear 11 of microblaze flush bonding processor by peripheral bus on the sheet 12, start different according to the command word that writes with the output signal of command register 1401, send out respectively and start 1 42 and 141 the signal that resets, this startups 142 and 141 the signal of resetting are connected respectively to the global semaphore connecting line of four pseudo satellite, pseudolite peripheral hardwares 13;
The second the tunnel is provided with pseudo satellite, pseudolite peripheral hardware clock control logic 140 modules;
Third Road is provided with interruption logging device 1404 modules, this module is collected the interruption input signal of four pseudo satellite, pseudolites respectively, interrupt request singal 146 is delivered to the input of interruption logging device 1404, and after collection was neat, the output signal of this interruption logging device 1404 was an interrupt signal 1.
Each pseudo satellite, pseudolite peripheral hardware clock control logic 140 module of described false satellite baseband signal maker are provided with pseudo satellite, pseudolite peripheral hardware A time-delay control register 1402, pseudo satellite, pseudolite peripheral hardware A amount of delay register 1403, carrier frequency delay controller 1405,80 frequency divisions 1406 and 20460 frequency divisions, 1407 modules at least, wherein:
The output signal of one group of pseudo satellite, pseudolite peripheral hardware A time-delay control register 1402 and pseudo satellite, pseudolite peripheral hardware A amount of delay register 1403 is delivered to the input of carrier frequency delay controller 1405 respectively, and the input signal of the high steady clock of 81.84M is delivered to the input of carrier frequency delay controller 1405; The output signal of the carrier frequency delay controller 1405 counter frequency division by 80 frequency divisions 1406 and 20460 frequency divisions, 1407 modules respectively passes out pseudo satellite, pseudolite peripheral hardware 13 required digital frequency synthesizer clock 145, navigation message clock 144 and 143 3 kinds of clock signals of pseudo noise code clock along separate routes.
Operation principle of the present utility model and system's characteristics are as follows:
The utility model has mainly been finished the realization and the controlling organization of false satellite baseband signal; Baseband signals such as the built-in CA code generator of the utility model, navigation message shift unit, DDS carrier wave maker generate and control logic circuit, and there are embedded type CPU and RS232 serial line interface, handled easily person to control generation and the operation and the parameters of pseudo satellite, pseudolite signal on computers flexibly.
The utility model has been realized a kind of low cost, degree of precision, control false satellite baseband signal maker flexible, easy to use.Its output signal is except carrier wave is the 10.23M intermediate frequency, and form, content and gps signal are consistent.With the gps carrier frequency of output signal up-conversion to 1575.42M, can by antenna launch and gps signal in full accord.It provides the functions such as injection, the selection of CA sign indicating number, signal time delay control of navigation message, and integrated four tunnel pseudo satellite, pseudolite signalling channels independently, makes things convenient for the research of pseudo satellite, pseudolite networking or monomer to use.The whole system core is integrated in the fpga chip, has saved the pseudo satellite, pseudolite spending of hardware, and development time and expense have improved reliability and controllability, is fit to very much the research of pseudo satellite, pseudolite indoor positioning and as the signal source of satellite navigation technical research.
The core of the utility model false satellite baseband signal maker is that the embedded system that realizes in the fpga chip of an Xilinx company is added the baseband signal maker that some necessary peripheral circuits constitute pseudo satellite, pseudolite.General fpga chip is the digital circuit that is used for realizing specific logical function, and complicated controlled function is then finished by MCU.And false satellite baseband signal maker had both needed to realize that the digital circuit of specific logical function realizes that the CA sign indicating number generates, navigation message output and the output of DDS carrier wave, and the order of host computer and realize complicated control according to this order needs again to decode.Therefore common circuit design needs FPGA+MCU to realize.And the fpga chip of the above series of the spartanIII of XILINX is all supported embedded soft nuclear microblaze, therefore the digital circuit and an embedded soft nuclear embedded SOC (system on a chip) SOC of composition (System on a Chip) of specific logical function can be realized in a fpga chip.
The benefit of doing like this is: at first saved the pseudo satellite, pseudolite spending of hardware, removed the MCU chip with and complicated peripheral circuit, and many identical pseudo satellite, pseudolites of hardware configuration are realized on a circuit, saved development time and expense greatly, reduced unreliability.In addition, because pseudo satellite, pseudolite need be subjected to master station control in system, therefore pseudo satellite, pseudolite needs hardware communication interface and communication line, if many pseudo satellite, pseudolites are realized respectively, in the communication line construction, also need to consider the multiple access communication scheme so, certainly will increase the hardware spending and the difficulty of communication system like this.In addition, pseudolite systems be an important problem synchronously, the baseband portion of many pseudo satellite, pseudolite signals is done together more convenient control.At last, convenient, flexible in the time of will revising system or increase and decrease function because system is in the inner realization of a slice fpga chip, need not redesign circuit making sheet.
See also shown in the accompanying drawing 1,2, the utility model general structure is:
The circuit structure of hardware is more common as can be seen from the primary structure of false satellite baseband signal maker, peripheral components all is some devices commonly used, common FPGA (field programmable gate array) development board can both meet the demands, and this makes that false satellite baseband signal maker is easier to realize.The core of false satellite baseband signal maker all realizes at FPGA (field programmable gate array) chip internal, primary structure as shown in Figure 2, being one serves as the embedded SOC (system on a chip) of control core with the soft nuclear of microblaze.
Embedded development external member EDK (the Embedded Development Kit) software that utilizes Xilinx is the SOC (system on a chip) of self-defined microblaze easily, Memory Controller Hub among Fig. 2, serial ports control module and interrupt control unit all are ready-made IP kernels, can directly add.It is the internal resource of FPGA that the digital dock manager is DCM again, clock and pseudo satellite, pseudolite administration module and 4 pseudo satellite, pseudolite peripheral hardwares then are custom-designed logical circuits, are connected by peripheral bus OPB on the sheet (On-chip Peripheral Bus) bus with microblaze as peripheral hardware.
Memory Controller Hub is used for microblaze and reads the outer internal memory of sheet, as the instruction and data memory; It is connected with local bus memory LMB (Local Memory Bus) with micro blaze.The serial ports control module is used to receive the control command from host computer.After receiving order, can send interrupt signal 0.DCM (digital dock manager) is that the FPGA clock is handled resource, native system has used two DCM (digital dock manager), one is used for to microblaze provides processor clock, and high steady clock input that receives 20.46M also offers clock and pseudo satellite, pseudolite administration module with its 4 frequency multiplication and is used for producing into the pseudo satellite, pseudolite peripheral hardware clock of pseudo noise code, navigation message and digital frequency synthesizer.
The pseudo satellite, pseudolite peripheral hardware is made to modular peripheral hardware, can increase and decrease flexibly, native system is integrated 4 road pseudo satellite, pseudolites.Each pseudo satellite, pseudolite all passes through OPB (peripheral bus on the sheet) bus and links to each other with microblaze, is used for transmitting navigation message and the CA sign indicating number is set selecting.Control in running is mainly finished by clock and pseudo satellite, pseudolite administration module, and clock and pseudo satellite, pseudolite administration module are respectively four pseudo satellite, pseudolite peripheral hardwares three kinds of clock signals are provided.Resetting and starting two control signals then is that four pseudo satellite, pseudolite peripheral hardwares are public, can guarantee the synchronous startup of four pseudo satellite, pseudolites like this.Every pseudo satellite, pseudolite can produce an interrupt requests after sending 30 navigation message, after clock and pseudo satellite, pseudolite administration module have been collected the interrupt requests of four pseudo satellite, pseudolites, can produce an interrupt signal 1.
Interrupt control unit guarantees that according to priority management interrupt signal 0 and interrupt signal 1 each interrupt signal can both in time be handled.
Pseudo satellite, pseudolite core logic circuit design 30
The pseudo satellite, pseudolite core logic circuit comprises " pseudo satellite, pseudolite peripheral hardware " module shown in Fig. 2 and " clock and pseudo satellite, pseudolite management " module.
" pseudo satellite, pseudolite peripheral hardware " module and " clock and pseudo satellite, pseudolite management " module all are OPB (peripheral bus on the sheet) peripheral hardwares for microblaze.After finishing the self-defined logical circuit of realizing its specific function, EDK software can be encapsulated as it peripheral hardware of supporting OPB (peripheral bus on the sheet) bus easily.Therefore OPB (peripheral bus on the sheet) device all comprises two parts, and a part is OPB (peripheral bus on a sheet) bus interface, and a part is user-defined logical circuit.Just describe self-defined logical circuit here in detail.
" pseudo satellite, pseudolite peripheral hardware " modular structure as shown in Figure 3.Mainly select maker, compositions such as navigation message shift unit and digital frequency synthesizer carrier wave maker by the CA sign indicating number.
The CA sign indicating number is selected the CA code type of maker according to the content decision output of CA sign indicating number mask register, can select the 1.023M clock of use in 1-32.The navigation message shift unit with the speed of 50Hz with one one Bits Serial output of text, whenever shift out 30 (words of corresponding GPS text) after, send interrupt request singal, and from the navigation message register, read 30 new texts.DDS carrier wave maker is to utilize the mode of look-up table to produce the sine wave of the 10.23M of 12 precision, and input clock is 81.84M.
Above-mentioned three modules are except clock separately, and sharing resets and start two controls incoming lines.The CA sign indicating number selects the CA sign indicating number output of maker and the output of navigation message shift unit to carry out mould two and computing in addition, and its result carries out the BPSK modulation with carrier wave again.The result of modulation forms 12 data output and two 81.84M clocks (two clocks are anti-phase) output, all offers the outer analog-digital chip of fpga chip.
Whole pseudo satellite, pseudolite peripheral hardware is made module, four such pseudo satellite, pseudolite peripheral hardwares in system, have been added, difference with the base address is distinguished, and the CA sign indicating number mask register of each pseudo satellite, pseudolite peripheral hardware is read and write by the OPB bus with the corresponding different offset address of navigation message register.
" clock and pseudo satellite, pseudolite management " module is to be responsible for the pseudo satellite, pseudolite peripheral hardware required clock signal is provided, and finish interrupt management, start and reset, control behavior such as time delay management.
Startup and command register by the read-write of OPB bus, according to the command word difference that writes, provide the signal that starts and reset by microblaze, and these two signals are connected to four pseudo satellite, pseudolite peripheral hardwares.
Pseudo satellite, pseudolite clock control logic 140 has four respectively corresponding four " pseudo satellite, pseudolite peripheral hardwares " among Fig. 4 in this module.It is input as the high steady clock of 81.84M, provides three kinds of clock signals that the pseudo satellite, pseudolite peripheral hardware needs by the counter frequency division.Each pseudo satellite, pseudolite clock control logic all has one group of time-delay control register and amount of delay register, and the former is used for writing and removes the time-delay command word, and the latter is used for writing the value of time-delay.These two registers can be by the read-write of OPB bus.
Claims (5)
1, a kind of false satellite baseband signal maker, this device has programmable gate array, bus, interface, antenna, logical circuit, inverter, register, memory, timer manager, delay controller, digital frequency synthesizer, interruption logging device and D/A converter, it is characterized in that: this device comprises at least:
On-site programmable gate array FPGA (1), serial line interface (2), boundary scan interface (3), memory chip (4), 75M crystal oscillator clock input (5), 20.46M high steady clock input (6), digital-to-analogue conversion (7) and intermediate-freuqncy signal (8) module, and integrated four tunnel pseudo satellite, pseudolite signalling channel independently, the digital circuit of logic function and embedded soft nuclear are formed an embedded SOC (system on a chip), the whole system core is integrated in an on-site programmable gate array FPGA (1) chip, and soft nuclear and four road pseudo satellite, pseudolite peripheral hardwares are combined as a baseband signal maker together; Wherein:
The input of one on-site programmable gate array FPGA (1) module is connected with the output of 75M crystal oscillator clock input (5) and high steady clock input (6) module of 20.46M respectively, the output of on-site programmable gate array FPGA (1) module respectively with digital-to-analogue conversion (7) module in the input of digital-to-analogue conversion A (71), digital-to-analogue conversion B (72), digital-to-analogue conversion C (73) and digital-to-analogue conversion D (74) walk abreast mutually and be connected;
The output of digital-to-analogue conversion A (71), digital-to-analogue conversion B (72), digital-to-analogue conversion C (73) and digital-to-analogue conversion D (74) respectively with intermediate-freuqncy signal (8) module in parallel mutually connection of input of intermediate-freuqncy signal A (81), intermediate-freuqncy signal B (82), intermediate-freuqncy signal C (83) intermediate-freuqncy signal D (84);
One serial line interface (2) is connected with the corresponding port of on-site programmable gate array FPGA (1) module by reception, the transmit port of chip;
One border scan interface (3) is connected by the corresponding port of interface with on-site programmable gate array FPGA (1) module;
The input/output terminal of one memory chip (4) interconnects with the I/O of on-site programmable gate array FPGA (1) module respectively by bus;
One on-site programmable gate array FPGA (1) module mainly is made up of the soft nuclear of microblaze flush bonding processor (11), pseudo satellite, pseudolite core logic circuit (30), digital dock manager A (15), digital dock manager B (16), interrupt control unit (17), serial ports control module (18) and Memory Controller Hub (20), and the clock signal of the digital dock manager DCM of this on-site programmable gate array FPGA (1) internal resource is directly delivered to the corresponding port of the soft nuclear of microblaze flush bonding processor (11) module; The logical signal of pseudo satellite, pseudolite core logic circuit (30) is delivered to each corresponding port of the soft nuclear of microblaze flush bonding processor (11) module respectively;
The output signal of one digital dock manager A (15) is delivered to the input of the soft nuclear of microblaze flush bonding processor (11), and 75M crystal oscillator clock input (5) signal is delivered to the input of digital dock manager A (15);
The output signal of one digital dock manager B (16) is delivered to the clock in the pseudo satellite, pseudolite core logic circuit (30) and the input of pseudo satellite, pseudolite administration module (14), and high steady clock input (6) signal of 20.46M is delivered to the input of digital dock manager B (16);
The interrupt signal of one interrupt control unit (17) output is delivered to the input of the soft nuclear of microblaze flush bonding processor (11), the output interrupt signal 0 of serial ports control module (18) is delivered to the input of interrupt control unit (17), and the output interrupt signal 1 of clock in the pseudo satellite, pseudolite core logic circuit (30) and pseudo satellite, pseudolite administration module (14) is delivered to the input of interrupt control unit (17);
The input/output terminal of one serial ports control module (18) is connected with the corresponding port of serial line interface (2) module, reception is from the control command of host computer, can send interrupt signal 0 after receiving order, the output transmission of serial ports control module (18) sends signal, and the I/O of serial ports control module (18) is connected with the corresponding port of the soft nuclear of microblaze flush bonding processor (11) module respectively by peripheral bus on the sheet (12);
The input/output terminal of one Memory Controller Hub (20) is connected by the corresponding port of local bus memory (19) with the soft nuclear of microblaze flush bonding processor (11).
2, false satellite baseband signal maker according to claim 1, it is characterized in that: be provided with pseudo satellite, pseudolite peripheral hardware (13) and clock and pseudo satellite, pseudolite administration module (14) in the described pseudo satellite, pseudolite core logic circuit (30), the input/output terminal of this pseudo satellite, pseudolite core logic circuit (30) is connected with the corresponding port of the soft nuclear of microblaze flush bonding processor (11) module respectively by peripheral bus on the sheet (12); The output of pseudo satellite, pseudolite core logic circuit (30) interconnects by the input of peripheral bus on the sheet (12) with analog-digital chip, wherein:
One pseudo satellite, pseudolite peripheral hardware (13) respectively by four the tunnel independently pseudo satellite, pseudolite peripheral hardware A (131), pseudo satellite, pseudolite peripheral hardware B (132), pseudo satellite, pseudolite peripheral hardware C (133) and pseudo satellite, pseudolite peripheral hardware D (134) form, the output of this pseudo satellite, pseudolite peripheral hardware (13) interconnects by the input of peripheral bus on the sheet (12) and analog-digital chip;
The pseudo noise code clock (143) of one clock and pseudo satellite, pseudolite administration module (14) output, navigation message clock (144) and digital frequency synthesizer clock (145) clock signal are delivered to four tunnel each input of pseudo satellite, pseudolite peripheral hardware A (131), pseudo satellite, pseudolite peripheral hardware B (132), pseudo satellite, pseudolite peripheral hardware C (133) and pseudo satellite, pseudolite peripheral hardware D (134) independently respectively; Resetting (141) and starting (142) two control signals of clock and pseudo satellite, pseudolite administration module (14) output is delivered to respectively on the global semaphore end of four tunnel independence pseudo satellite, pseudolite peripheral hardwares (13).
3, false satellite baseband signal maker according to claim 2, it is characterized in that: described pseudo satellite, pseudolite peripheral hardware (13) is provided with four tunnel independence pseudo satellite, pseudolite structures that different base address form, the pseudo satellite, pseudolite peripheral hardware (13) of each road independence pseudo satellite, pseudolite structure comprises at least: the CA sign indicating number is selected maker (1301), navigation message shift unit (1302), digital frequency synthesizer carrier wave maker (1303), CA sign indicating number mask register (1307) and navigation message register (1308), wherein:
The input that the CA sign indicating number is selected maker (1301) interconnects with the output of CA sign indicating number mask register (1307) and pseudo noise code clock (143) signal respectively; The input of navigation message shift unit (1302) interconnects with the output of navigation message register (1308) and navigation message clock (144) signal respectively; The output of the input of digital frequency synthesizer carrier wave maker (1303) and digital frequency synthesizer clock (145) signal interconnects; CA sign indicating number mask register (1307) corresponds to different offset addresss with navigation message register (1308);
The CA sign indicating number selects global semaphore connecting line and startup (142) the control signal end between maker (1301) and the digital frequency synthesizer carrier wave maker (1303) to interconnect; The CA sign indicating number selects the global semaphore connecting line of maker (1301), navigation message shift unit (1302) and digital frequency synthesizer carrier wave maker (1303) and (141) the control signal end that resets to interconnect;
The output that the CA sign indicating number is selected maker (1301) and navigation message shift unit (1302), is connected with the input that binary phase shift keying is modulated (1306) module with after (1304) computing module is connected via mould two again; The output of digital frequency synthesizer carrier wave maker (1303) is connected with the input of binary phase shift keying modulation (1306) module; The clock signal one tunnel of binary phase shift keying modulation (1306) module is a digital-to-analogue conversion clock 0, export via inverter (1305) on another road, be digital-to-analogue conversion clock 1,12 figure place mould translation data of two-way clock signal and the output of binary phase shift keying modulation (1306) module export the respective input of analog-digital chip respectively to;
The interrupt request singal (146) of one navigation message shift unit (1302) output is delivered to the input of clock and pseudo satellite, pseudolite administration module (14).
4, false satellite baseband signal maker according to claim 1, it is characterized in that: described clock and pseudo satellite, pseudolite administration module (14) are provided with four pseudo satellite, pseudolite peripheral hardware clock control logic (140) module, respectively corresponding four pseudo satellite, pseudolite peripheral hardwares (13), each pseudo satellite, pseudolite peripheral hardware clock control logic (140) are provided with one group of time-delay control register and amount of delay register, carrier frequency delay controller and each frequency divider; Described clock and pseudo satellite, pseudolite administration module (14) comprise three road signals at least:
The first via is provided with and starts and command register (1401) module, startup and command register (1401) are imported read-write by the soft nuclear of microblaze flush bonding processor (11) by peripheral bus (12) on the sheet, start different according to the command word that writes with the output signal of command register (1401), send out the signal of startup (142) and reset (141) respectively, the signal of this startup (142) and reset (141) is connected respectively to the global semaphore connecting line of four pseudo satellite, pseudolite peripheral hardwares (13);
The second the tunnel is provided with pseudo satellite, pseudolite peripheral hardware clock control logic (140) module;
Third Road is provided with interruption logging device (1404) module, this module is collected the interruption input signal of four pseudo satellite, pseudolites respectively, interrupt request singal (146) is delivered to the input of interruption logging device (1404), and after collection was neat, the output signal of this interruption logging device (1404) was an interrupt signal 1.
5, false satellite baseband signal maker according to claim 4, it is characterized in that: described each pseudo satellite, pseudolite peripheral hardware clock control logic (140) module is provided with pseudo satellite, pseudolite peripheral hardware A time-delay control register (1402), pseudo satellite, pseudolite peripheral hardware A amount of delay register (1403), carrier frequency delay controller (1405), 80 frequency divisions (1406) and 20460 frequency divisions (1407) module at least, wherein:
The output signal of one group of pseudo satellite, pseudolite peripheral hardware A time-delay control register (1402) and pseudo satellite, pseudolite peripheral hardware A amount of delay register (1403) is delivered to the input of carrier frequency delay controller (1405) respectively, and the high surely input signal of clock of 81.84M is delivered to the input of carrier frequency delay controller (1405); The output signal of carrier frequency delay controller (1405) passes out the required digital frequency synthesizer clock (145) of pseudo satellite, pseudolite peripheral hardware (13), navigation message clock (144) and (143) three kinds of clock signals of pseudo noise code clock along separate routes by the counter frequency division of 80 frequency divisions (1406) and 20460 frequency divisions (1407) module respectively.
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| CNU200720076280XU CN201118603Y (en) | 2007-11-16 | 2007-11-16 | Pseudo satellite baseband signal generator |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101887130A (en) * | 2010-06-09 | 2010-11-17 | 中国人民解放军第二炮兵工程学院 | Programmable navigational satellite spread spectrum sequence generator |
| CN101158717B (en) * | 2007-11-16 | 2011-01-26 | 上海伽利略导航有限公司 | False satellite baseband signal maker and control method of built-in processor thereof |
| CN106526624A (en) * | 2017-01-18 | 2017-03-22 | 桂林电子科技大学 | Satellite navigation signal simulator and simulation method thereof |
-
2007
- 2007-11-16 CN CNU200720076280XU patent/CN201118603Y/en not_active Expired - Fee Related
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101158717B (en) * | 2007-11-16 | 2011-01-26 | 上海伽利略导航有限公司 | False satellite baseband signal maker and control method of built-in processor thereof |
| CN101887130A (en) * | 2010-06-09 | 2010-11-17 | 中国人民解放军第二炮兵工程学院 | Programmable navigational satellite spread spectrum sequence generator |
| CN101887130B (en) * | 2010-06-09 | 2013-06-19 | 中国人民解放军第二炮兵工程学院 | Programmable navigational satellite spread spectrum sequence generator |
| CN106526624A (en) * | 2017-01-18 | 2017-03-22 | 桂林电子科技大学 | Satellite navigation signal simulator and simulation method thereof |
| CN106526624B (en) * | 2017-01-18 | 2023-08-15 | 桂林电子科技大学 | Satellite navigation signal simulator and simulation method thereof |
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