CN201004226Y - Minimum system module of ARM processor with FLASH and SDRAM - Google Patents
Minimum system module of ARM processor with FLASH and SDRAM Download PDFInfo
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- CN201004226Y CN201004226Y CNU2006200484439U CN200620048443U CN201004226Y CN 201004226 Y CN201004226 Y CN 201004226Y CN U2006200484439 U CNU2006200484439 U CN U2006200484439U CN 200620048443 U CN200620048443 U CN 200620048443U CN 201004226 Y CN201004226 Y CN 201004226Y
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- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
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Abstract
The utility model relates to a smallest system module of an ARM processor with a FLASH and a SDRM, comprising an ARM processor, a SDRM, a NANDFLASH, a NORFLASH, a power management and a LED instruction and a SO_DIMM200 gold finger. The smallest system module of an ARM processor is formed by an ARM processor and a FLASH, a SDRM, and a power management chip. The NANDFLASH and the NORFLASH are able to provide more flexible using to the system module, while the power management not only promises a reliable replacement for the ARM processor in the conditions of power up and power disturbance, ensuring a reliable running, but closes the corresponding power in the power saving mode such as the ARM processor sleeping; moreover, due to the SO_DIMM200 gold finger, the utility model is able to fully pin out the functional pins of the ARM processor, making the using more convenient. By integrating smallest system module of an ARM processor on the module with a general formal, the utility model not only makes the module flexible and multifunctional, but promises a more steady and reliable running; besides, provides a simple periphery circuit, directly reducing the cost of the system developing and producing.
Description
Technical field
The utility model relates to the correlative technology field of microprocessor, particularly a kind of arm processor minimum systematic module with FLASH and SDRAM.
Background technology
In the application of ARM, there are two kinds of developing thought, a kind of is in the integrated all application of same inside modules, another kind is that nucleus module is separated with application module, because being integrated in same Module Design exists debug difficulties, be not easy to problems such as co-development, trended towards at present thinking that the ARM nucleus module is separated with the peripheral expansion module, the benefit of doing like this reduces development difficulty, be convenient to co-development simultaneously, but be subjected to the restriction of interfacing at present,, and can't give full play to the characteristic of arm processor mostly because the stitch limited amount of interface.
The utility model content
The purpose of this utility model is for the arm processor minimum systematic module of a kind of FLASH of having and SDRAM is provided, solved in the conventional art, functional module such as the FLASH of arm processor, SDRAM and optional function module do not have strict the division, cause development difficulty bigger, the problem of debug difficulties; And solved in the conventional art because to be subjected to arrive interfacing most restricted, the interface pin number of minimum systematic module is restricted, and can't give full play to the function of arm processor and the problem of performance advantage.
For achieving the above object, the utility model has adopted following technical scheme:
The utility model discloses the arm processor minimum systematic module of a kind of FLASH of having and SDRAM, the SDRAM storer that comprise arm processor, is connected with arm processor, it is characterized in that: module also comprises NANDFLASH flash memory and the NOR FLASH flash memory that is connected with arm processor, has adopted NAND FLASH and NOR FLASH to provide more flexibly to system module simultaneously and has used.
Described module comprises that also one provides the power management chip of power management and the LED indicating module that is connected with arm processor for whole module, power management can not only guarantee power on and the power supply disturbed condition under the reliable reset arm processor guarantee its reliability service, close corresponding power supply in the time of can also being in battery saving modes such as sleep at arm processor.Module also comprises a memory interface that is connected with arm processor, and this memory interface is a DDR SDRAM 200PIN DDR SO-DIMM memory interface, and promptly the SO-DIMM200 golden finger can all be drawn the function pin of arm processor, uses more convenient.
Owing to adopted above scheme, the beneficial effect that the utility model is possessed is: since on the module of general format integrated arm processor minimum system, make module not only flexible multi-purpose, and make system's operation more reliable and more stable, make that also peripheral circuit is simple, directly reduce system development and production cost.
Description of drawings
Fig. 1 is a structural representation of the present utility model.
Embodiment
Below in conjunction with drawings and Examples the utility model is further described.
A kind of arm processor minimum systematic module as shown in Figure 1 with FLASH and SDRAM, comprise arm processor 1, the SDRAM storer 2 that is connected with arm processor 1, module also comprises NAND FLASH flash memory 3 and the NOR FLASH flash memory 4 that is connected with arm processor 1, has adopted NAND FLASH flash memory 3 and NOR FLASH flash memory 4 to provide more flexibly to system module simultaneously and has used.
Described module comprises that also one provides the power management chip 5 of power management and the LED indicating module 7 that is connected with arm processor for whole module, power management chip 5 can not only guarantee power on and the power supply disturbed condition under reliable reset arm processor 1 guarantee its reliability service, close corresponding power supply in the time of can also being in battery saving mode such as sleep at arm processor 1.Module also comprises a memory interface 6 that is connected with arm processor 1, and this memory interface 6 is a DDR SDRAM 200PIN DDR SO-DIMM memory interface, and promptly the SO-DIMM200 golden finger can all be drawn the function pin of arm processor, uses more convenient.
Wherein: arm processor 1 is a kind of 32 general risc processors.32 is that the external address and the data bus of finger processor is 32, and the same frequency processor performance of comparing 16 is more powerful.Adopt the ARM microprocessor of RISC framework generally to have following characteristics:
1, little, the low-power consumption of volume, low cost, high-performance;
2, support Thumb (16)/two instruction set of ARM (32), well 8/16 devices of compatibility;
3, use register in a large number, instruction execution speed is faster;
4, most of data manipulations are all finished in register;
5, addressing mode is simple flexibly, carries out the efficient height;
6, instruction length is fixed;
So far, ARM microprocessor and The Application of Technology almost have been deep into every field:
1, industrial control field: RISC framework as 32, not only occupied most of market share in high-end microcontroller market based on the microcontroller chip of ARM nuclear, also expand to low side microcontroller application gradually simultaneously, the low-power consumption of ARM microcontroller, high performance-price ratio have proposed challenge to 8/16 traditional 8-digit microcontrollers.
2, field of wireless communication: the existing at present wireless telecommunications system above 85% has adopted the ARM technology, and ARM consolidates in the status in this field day by day with its high-performance and low cost.
3, network application:, adopt the ADSL chip of ARM technology just progressively to obtain competitive edge along with the popularization of broadband technology.In addition, ARM voice and Video processing up optimization, and obtain to support that extensively also the application to DSP has proposed challenge.
4, consumer electronics product: the ARM technology is widely adopted at present popular digital audio-frequency player, top box of digital machine and game machine.
5, imaging and safety product: the overwhelming majority adopts the ARM technology in the digital camera of current trend and the printer.32 SIM smart cards in the mobile phone have also adopted the ARM technology.
In addition, ARM microprocessor and technology also are applied to many different fields, and can obtain application more widely in the future.
SDRAM storer 2 is a kind of high capacity, high-speed storer.And in various random access memory parts, the price of SDRAM is low, volume is little, speed is fast, capacity is big, is more satisfactory device.But the steering logic more complicated of SDRAM requires also very strictly to sequential, use very inconveniently, and this just requires a special controller, makes system user can operate SDRAM easily.
The pin of SDRAM device is divided into control signal, address and data three classes.Comprise several BANK among the common SDRAM, the storage unit of each BANK is by the row and column addressing.Because this special storage organization, SDRAM has following operating characteristic.
The initialization of SDRAM: SDRAM must be disposed the mould ground formula register of SDRAM by an initialize process behind 100～200 μ s that power on, the value of mode register is determining the mode of operation of SDRAM.
Storage unit access: for reducing the I/O pin number, SDRAM multiplexing address line so when read-write SDRAM, activate the BANK that will read and write by the ACTIVE order earlier, and latch row address, latchs column address then when read write command is effective.In case could activate same BANK once more after having only the preliminary filling order of execution after BANK is activated.
Refresh and preliminary filling: the storage unit of SDRAM can be understood as an electric capacity, and always therefore inclined discharge must have the refresh cycle regularly to avoid loss of data.Refresh cycle can be calculated by (minimum refresh cycle ÷ clock period) and be obtained.To BANK precharge or close the BANK that has activated, but preliminary filling particular B ANK also can act on all BANK simultaneously, and A10, BA0 and BA1 are used to select BANK.
Operation control:--the concrete control command of-SDRAM is assisted by some special-purpose control pins and address wire and is finished.CS, RAS, CAS and WR are in the state decision concrete operations action of rising edge clock, and address wire and BANK select control line to import as auxiliary parameter in the part operation action.Because special storage organization, the SDRAM operational order is many, has only simple read-write unlike SRAM.
NAND FLASH flash memory 3 and NOR FLASH flash memory 4 are two kinds of main nonvolatile flash memory technology on the present market.Intel at first developed NOR flash technology in 1988, thoroughly changed the situation that was originally ruled all the land by EPROM and EEPROM.And then, 1989, Toshiba delivered NAND FLASH structure, emphasized to reduce the cost of every bit, higher performance, and can easily upgrade by interface as disk.
In most cases flash memory just is used for storing a spot of code, and at this moment the NOR flash memory is more suitable for.NAND then is the ideal solution of the high density of data storage.
The characteristics of NOR are to carry out (XIP, eXecute In Place) in the chip, and application program can directly be moved in the FLASH flash memory like this, needn't read code among the RAM of system again.
The transfer efficiency of NOR is very high, has very high cost benefit when the low capacity of 1～4MB, but the very low performance that has influenced it with erasing speed greatly that writes.
Enable nand gate can provide high cell density, can reach high storage density, and the speed that writes and wipe is also very fast.The difficulty of using NAND is the management of FLASH and needs special system interface.
The FLASH flash memory is a nonvolatile memory, can carry out erasable and programming again to the memory cell block that is called piece.The write operation of any FLASH device can only be carried out in sky or the unit of having wiped, so in most cases, must carry out earlier before carrying out write operation and wipe.It is foolproof that the NAND device is carried out erase operation, and NOR then requires positions all in the object block all to be written as 0 earlier before wiping.Because be that piece with 64～128KB carries out when wiping the NOR device, the time of carrying out a write/erase operation is 5s, in contrast, the piece of wiping the NAND device and being with 8～32KB carries out, and the execution identical operations at most only needs 4ms.The difference of piece size had further widened the performance gap between NOR and the NADN when execution was wiped, and statistics shows, must carry out in based on the unit of NOR for the given more erase operation of a cover write operation (when especially upgrading small documents).
Like this, when selecting storage solution, the designer must weigh following every factor: the read rate of NOR is faster slightly than NAND; The writing speed of NAND is fast more a lot of than NOR; The 4ms erasing speed of NAND is fast more than the 5s of NOR; Most of write operations need be carried out erase operation earlier; The erase unit of NAND is littler, and corresponding erasing circuit still less.
The interface difference: NOR FLASH has the SRAM interface, has enough address pin to come addressing, at an easy rate each byte of its inside of access.The NAND device uses complicated I/O mouth to come access data serially, and the method for each product or manufacturer may have nothing in common with each other.8 pins are used for transmitting control, address and data message.The piece of 512 bytes is adopted in NAND read and write operation, and this point is this generic operation of picture hard disk management a bit, very naturally, just can replace hard disk or other block devices based on the storer of NAND.
Capacity and cost: the unit size of NAND FLASH almost is half of NOR device, because production run is more simple, enable nand gate can provide higher capacity in given die size, has also just correspondingly reduced price.It is the major part in 1～16MB flash memory market that NOR FLASH has occupied capacity, and NAND FLASH just is used in the middle of the product of 8～128MB, and this illustrates that also NOR is mainly used in the code storage medium, and NAND is suitable for data storage.
Reliability and durability: a problem that needs emphasis to consider is a reliability when adopting the FLASH medium.For the system of needs expansion MTBF, Flash is very suitable storage scheme.Can handle three reliabilities that comparison NOR and NAND are come in the aspect from life-span (durability), position exchange and bad piece.
Life-span (durability): the maximum erasable number of times of each piece is 1,000,000 times in nand flash memory, and the erasable number of times of NOR is 100,000 times.Nand memory is except having 10 to 1 piece erase cycle advantage, and typical NAND piece size is littler 8 times than NOR device, and the deletion number of times of each nand memory piece in the given time will lack.
The position exchange: all FLASH devices all are subjected to the puzzlement of position exchange phenomenon.(rarely found, the number of times that NAND takes place is more than NOR) in some cases, a bit can take place to reverse or reversed by report.One variation may be not clearly, if still occur on the critical file, this slight hitch may cause system-down.If just report has problem, mutiread just may solve several times.Certainly, if this position has really changed, just must adopt error detector/error correction (EDC/ECC) algorithm.The problem of bit reversal more is more common in nand flash memory, when the supplier of NAND advises using nand flash memory, uses the EDC/ECC algorithm simultaneously.This problem is not fatal for NAND storage multimedia messages the time.Certainly, if when coming storage operating system, configuration file or other sensitive informations, must use the EDC/ECC system to guarantee reliability with local memory device.
Bad piece is handled: the bad piece in the NAND device is a stochastic distribution.The effort of eliminating bad piece was also once arranged in the past, but find that yield rate is too low, cost is too high, and is not to one's profit.The NAND device need carry out initialization scan finding bad piece to medium, and bad piece is labeled as unavailable.In Manufactured device,, will cause high failure rate if can not carry out this processing by reliable method.
Be easy to use: can very directly use flash memory, can as other storeies, connect based on NOR, and can direct in the above operation code.Owing to need the I/O interface, NAND is more complex.The access method of various NAND devices is different because of producer.When using the NAND device, must write driver earlier, could continue to carry out other operations.Need suitable skill to NAND device writing information, because the designer must not write to bad piece, this just means on the NAND device all must carry out virtual map from start to finish.
Software is supported: when the software support is discussed, should distinguish basic read/write/wiping operation and higher leveled software that is used for disk emulation and flash memory management algorithm, comprise performance optimization.On the NOR device operation code without any need for the software support, when on the NAND device, operating equally, need driver usually, memory techniques driver (MTD) just, NAND and NOR device all need MTD when writing with erase operation.Needed MTD will lack relatively when using the NOR device, and many manufacturers all are provided for the more high-level software of NOR device.Drive the management that also is used for the DiskOnChip product is carried out emulation and nand flash memory, comprise error correction, the processing of bad piece and loss balancing.
DDR SDRAM 200PIN DDR SO-DIMM memory interface 6, it is the SO_DIMM200 golden finger, its dimensions meets SO-DIMM200 encapsulation standard, and this memory interface 6 is described by the DDR internal memory standard that JEDEC (meeting of electronic component industrial combination) formulates, and is of a size of the 67.6X31.75X1 millimeter.Reach 200 leading foots, fully expanded the hardware resource of system module, allow the user can not have limitation and freely carry out back-plane design.
Claims (4)
1, the arm processor minimum systematic module that has FLASH and SDRAM, the SDRAM storer that comprise arm processor, is connected with arm processor is characterized in that: module also comprises NAND FLASH flash memory and the NOR FLASH flash memory that is connected with arm processor.
2, the arm processor minimum systematic module with FLASH and SDRAM according to claim 1 is characterized in that: described module comprises that also one provides the power management chip of power management and the LED indicating module that is connected with arm processor for whole module.
3, the arm processor minimum systematic module with FLASH and SDRAM according to claim 1 and 2, it is characterized in that: described module also comprises the memory interface that is connected with arm processor.
4, the arm processor minimum systematic module with FLASH and SDRAM according to claim 3 is characterized in that: described memory interface is a DDR SDRAM 200PIN DDR SO-DIMM memory interface.
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| CNU2006200484439U CN201004226Y (en) | 2006-12-01 | 2006-12-01 | Minimum system module of ARM processor with FLASH and SDRAM |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101890923A (en) * | 2009-05-22 | 2010-11-24 | 触动多媒体技术（上海）有限公司 | Vehicle-mounted multimedia advertisement recreational interactive equipment system |
| CN102306003A (en) * | 2011-05-20 | 2012-01-04 | 烟台正信电气有限公司 | Embedded type general standardized platform |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101890923A (en) * | 2009-05-22 | 2010-11-24 | 触动多媒体技术（上海）有限公司 | Vehicle-mounted multimedia advertisement recreational interactive equipment system |
| CN101890923B (en) * | 2009-05-22 | 2014-08-06 | 触动多媒体技术（上海）有限公司 | Vehicle-mounted multimedia advertisement recreational interactive equipment system |
| CN102306003A (en) * | 2011-05-20 | 2012-01-04 | 烟台正信电气有限公司 | Embedded type general standardized platform |
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| Date | Code | Title | Description |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C41 | Transfer of patent application or patent right or utility model | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20090213 Address after: Shanghai City, Yangpu District National Road No. 335 Building No. 2 10031, zip code: 200433 Patentee after: Shanghai Hua Ping Electronic Technology Co., Ltd. Address before: Building 10, building 335, No. 2, National Road, Shanghai, Yangpu District: 200433 Patentee before: Shanghai Huacheng Network Tech Co., Ltd. |
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| ASS | Succession or assignment of patent right |
Owner name: SHANGHAI HUAPING ELECTRON SCIENCE CO., LTD. Free format text: FORMER OWNER: SHANGHAI HUACHENG NETWORKS TECHNOLOGY CO., LTD. Effective date: 20090213 |
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| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20080109 Termination date: 20151201 |
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| EXPY | Termination of patent right or utility model |