CN200982861Y - Direct storage type electronic theodolite - Google Patents
Direct storage type electronic theodolite Download PDFInfo
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- CN200982861Y CN200982861Y CN 200620026078 CN200620026078U CN200982861Y CN 200982861 Y CN200982861 Y CN 200982861Y CN 200620026078 CN200620026078 CN 200620026078 CN 200620026078 U CN200620026078 U CN 200620026078U CN 200982861 Y CN200982861 Y CN 200982861Y
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Abstract
A direct storage electronic theodolite comprises a main program single chip and a computing system single chip, characterized in a very big internal memory controlled by the main program chip, wherein the main program single chip manipulates the computing system single chip to finish collecting and computing of the measured data, which is stored in a internal memory chip, and the main program single chip reads data from the internal memory chip 104 and then transfers them to the computer. Compared with the prior art, the utility model can memory the data from a field operation directly, rather than resorting to the manual online memory between an electronic theodolite and an external storage facility in the traditional technology, thereby enjoying a high practicability and convenience, and realizing digital communication between a electronic theodolite and a computer without a exclusive chip.
Description
Technical field
The utility model relates to a kind of geodetic instrument, particularly relates to a kind of direct storing electronic transit that has very large memory.
Background technology
Electronic theodolite is a kind of instrument relatively more commonly used in the geodetic instrument, is mainly used to measure a three-dimensional viewpoin, but measured angle cooperates the stadimeter measuring distance.Common operating position is, after field operation has been measured data, can not directly be kept in the instrument, need or by serial port connecting wire measurement data be passed on notebook computer or other data processing equipments in addition with written notes record measurement data.This processing mode that can not directly carry out data storage of existing electronic theodolite has caused this instrument impracticable and inconvenient in practical operation.
On the basis of existing technology, if can directly in instrument, store thousands of groups of working point arrays, after field operation has been measured data, data can be imported into the instrument internal memory, when industry is mapped in getting back to, can directly from electronic theodolite, access the data of storage, also can utilize serial ports to import whole memory point data into computing machine, saved line numerous and diverse in the original operation, brought practical and convenient to user's use.
The utility model content
The utility model is just in order to solve above-mentioned existing in prior technology defective, and the electronics that proposes a kind of direct memory-type by very large memory is set, is realized the direct-type storage of electronic theodolite to measurement data through big instrument in electronic theodolite.
A kind of direct storing electronic that the utility model proposed is through big instrument, comprise master routine single-chip microcomputer and computing system single-chip microcomputer, it is characterized in that, this device also comprises the very large memory that is connected with the master routine single-chip microcomputer, wherein, described very large memory is by the control of master routine singlechip chip, and the computing system single-chip microcomputer is finished the collection and the calculating of measurement data, and the data that obtained deposit in the memory chip; The master routine single-chip microcomputer imports computing machine into and carries out data processing from memory chip 104 reading of data.
Compared with the prior art, the present invention can directly store the measurement data of field operation, need not conventional art in manual online storage operation between needed this instrument and the extraneous memory device, have very high practicality and convenience.
Description of drawings
Fig. 1 is the system block diagram of direct storing electronic transit of the present utility model.
Fig. 2 is the circuit diagram of direct storing electronic transit of the present utility model.
Fig. 3 for the master routine single-chip microcomputer when memory chip is carried out data write operation about the address, reply the sequential synoptic diagram that transmits with data.
Fig. 4 for the master routine single-chip microcomputer when memory chip is carried out data reading operation about the address, reply the sequential synoptic diagram that transmits with data.
Embodiment
The electronics of direct memory-type that the utility model proposes is through big instrument, as shown in Figure 1, comprise display 101, keyboard 102, master routine single-chip microcomputer 103 and computing system single-chip microcomputer 105, calculate single-chip microcomputer, electronic compensator computing system single-chip microcomputer etc. as vertical angle computing system single-chip microcomputer, horizontal angle, also comprise very large memory chip 104.Wherein, master routine single-chip microcomputer and computing system single-chip microcomputer are finished collection, the calculating of data, show measurement result at last on display, and measurement result directly is stored in the very large memory chip 104.
The concrete course of work is: in the field operation operation, master routine single-chip microcomputer 103 control computing system single-chip microcomputers 105 are finished the collection and the calculating of measurement data, and the data that obtained deposit in the memory chip 104; Master routine single-chip microcomputer 103 reads first group from memory chip 104 and counts to the single-chip microcomputer internal RAM, to the single-chip microcomputer internal RAM, imports computing machine by master routine single-chip microcomputer reading then into, so that the data manipulation in the industry in realizing finishes until all data reads.This imports process operation into can be by keyboard interrupt.
Further specify the technical solution of the utility model below by a specific embodiment.
The direct storing electronic transit that the utility model proposed, the concrete connecting circuit synoptic diagram of this device as shown in Figure 2.Memory chip pin 4 ground connection, pin 8 connect power supply, and memory chip pin 5 links to each other with master routine single-chip microcomputer pin two 6, is used to receive the data-signal of independent procedure single-chip microcomputer; Memory chip pin 6 links to each other with master routine single-chip microcomputer pin two 7; Be used to receive the clock signal of independent procedure single-chip microcomputer.Concrete data transmission is according to I
2The C communications protocol is carried out, and in this both-way communication mode, the master routine single-chip microcomputer produces the transmission direction of serial clock control bus as data transmitter, and generation initial sum stop condition sends data on the bus.Behind the single-chip microcomputer electrification reset, input, output interface are operated and finished exchanges data according to the instruction of internal program memory (ROM).Data are to read one group by one group memory chip, and the wherein temporary storage location of one group of data only is provided among the master routine single-chip microcomputer RAM.
Data of the present utility model are write process: read the data pointer in the internal memory, will treat that write data writes the address of data pointer indication; Again data pointer is added one, point to next group data, the line data write operation of going forward side by side.For write operation, the utility model adopts the byte WriteMode, and AT24C256 requires second address wire.This address field is a word address, and it is formed by eight, and the visit to any of 256 word memorys is provided.After receiving word address, AT24C256 responds with replying, and waits for and next eight bit data respond again to reply.Main frame finishes to transmit by producing stop condition then, and this moment, AT24C256 began inner write cycle time to nonvolatile memory.The AT24C256 input end is under an embargo in the internal write cycle process, does not respond any request from main frame.About the address, reply the sequential that transmits with data, as shown in Figure 3.
The pin two 6,27 of master routine single-chip microcomputer P89C58BA is connected with the pin 5,6 of memory chip, reads the data in the internal memory, and the concrete operations of read data are: main frame is visited any one memory cell with random fashion.Send read/write be changed to 1 before the address, main frame must be carried out once " pseudo-(dummy) " write operation.Main frame sends initial conditions, from the address and the follow-up word address that will read with it.After word address is replied, main frame send again immediately initial conditions and read/write be changed to 1 from the address.Be that the back is 8 words again from the replying of memory chip AT24C256 after this.Main frame finishes current the transmission by sending stop condition, has omitted replying of the 9th clock period.Address in the read data operation, reply with data and transmit sequential as shown in Figure 3.After master routine single-chip microcomputer P89C58BA reads one group of data, promptly to outside output, accept second group of data again, second group of data by that analogy, finished the read operation of 1020 groups of data in outside output.
Very large memory chip 104 adopts CMOS 262144 bit serial E
2PROM, model is AT24C256, it becomes 32768 * 8 in interior tissue.128 are used for some basic setup sum counters of store electrons transit among the AT24C256, deposit one group of number for per 4 * 8 * 8, so can store 1020 groups of numbers; Every group of number comprises the group number of horizontal angle, vertical angle, distance, storage.
The master routine single-chip microcomputer adopts P89C58BA in the utility model.
In the utility model, the TXD pin of master routine single-chip microcomputer passes to computing machine with data, for this reason, and in the circuit of the present utility model.Also be provided with four Sheffer stroke gates, in order to replace the special chip of single-chip microcomputer and intercomputer communication, specifically be connected to: the pin one 3 (TXD) on the master routine single-chip microcomputer is connected to the pin 4,5 of Sheffer stroke gate one; The pin 6 of Sheffer stroke gate one is the output of pin 4,5; It is connected to the pin 9 of Sheffer stroke gate two as an input signal of Sheffer stroke gate two; Whether the pin one 0 of Sheffer stroke gate two is used for control to computing machine transmission data; The output terminal pin 8 of Sheffer stroke gate two is connected to the pin one, 2 of Sheffer stroke gate three; The pin 3 of Sheffer stroke gate three is pin one, 2 output, and is connected to the J2 interface, and the J2 interface is connected to the serial line interface of computing machine.Thus, general single-chip microcomputer and computing machine communication need special-purpose chip, have saved special chip here, only with Sheffer stroke gate 74HCOOD just finished can with the computing machine communication again can with the work of stadimeter communication.
Claims (7)
1. direct storing electronic transit, comprise master routine single-chip microcomputer and computing system single-chip microcomputer, it is characterized in that, this device also comprises the very large memory that is connected with the master routine single-chip microcomputer, wherein, described very large memory is by the control of master routine singlechip chip, and the computing system single-chip microcomputer is finished the collection and the calculating of measurement data, and the data that obtained deposit in the memory chip; The master routine single-chip microcomputer imports computing machine into and carries out data processing from memory chip 104 reading of data.
2. direct storing electronic transit as claimed in claim 1, it is characterized in that, described memory chip pin (4) ground connection, pin (8) connect power supply, and described memory chip pin (5) links to each other with master routine single-chip microcomputer pin (26), is used to receive the data-signal of independent procedure single-chip microcomputer; Described memory chip pin (6) links to each other with master routine single-chip microcomputer pin (27); Be used to receive the clock signal of independent procedure single-chip microcomputer.
3. direct storing electronic transit as claimed in claim 1 is characterized in that, the TXD pin of described master routine single-chip microcomputer is connected to two input pins of first Sheffer stroke gate; The output terminal of first Sheffer stroke gate is connected to one of input pin of second Sheffer stroke gate as an input signal of second Sheffer stroke gate; Whether another input pin of second Sheffer stroke gate is used for control to computing machine transmission data; The output terminal of second Sheffer stroke gate is connected to two input pins of the 3rd Sheffer stroke gate; The output terminal of the 3rd Sheffer stroke gate is received the J2 interface, is connected to the serial line interface of computing machine again by the J2 interface.
4. direct storing electronic transit as claimed in claim 1 is characterized in that described data transmission is according to I
2The C communications protocol.
5. direct storing electronic transit as claimed in claim 1 is characterized in that, described memory chip adopts CMOS 262144 bit serial E
2PROM chip AT24C256, wherein 128 are used for the basic setup sum counter of store electrons transit, deposit one group of number for per 4 * 8 * 8,1020 groups of numbers of coexistence storage; Every group of number comprises the group number of horizontal angle, vertical angle, distance, storage.
6. direct storing electronic transit as claimed in claim 1 is characterized in that described master routine single-chip microcomputer is the P89C58BA chip.
7. direct storing electronic transit as claimed in claim 3 is characterized in that, described Sheffer stroke gate adopts the 74HC00D chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200620026078 CN200982861Y (en) | 2006-05-18 | 2006-05-18 | Direct storage type electronic theodolite |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200620026078 CN200982861Y (en) | 2006-05-18 | 2006-05-18 | Direct storage type electronic theodolite |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN200982861Y true CN200982861Y (en) | 2007-11-28 |
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ID=38910018
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200620026078 Expired - Fee Related CN200982861Y (en) | 2006-05-18 | 2006-05-18 | Direct storage type electronic theodolite |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN200982861Y (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111094892A (en) * | 2017-09-26 | 2020-05-01 | 天宝公司 | Data collection task queue for a surveying instrument |
| CN114935327A (en) * | 2022-04-26 | 2022-08-23 | 中国舰船研究设计中心 | Improvement method of deck theodolite |
-
2006
- 2006-05-18 CN CN 200620026078 patent/CN200982861Y/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111094892A (en) * | 2017-09-26 | 2020-05-01 | 天宝公司 | Data collection task queue for a surveying instrument |
| CN114935327A (en) * | 2022-04-26 | 2022-08-23 | 中国舰船研究设计中心 | Improvement method of deck theodolite |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20071128 Termination date: 20120518 |