CN200941100Y - Multi-channel concrete signals processor - Google Patents
Multi-channel concrete signals processor Download PDFInfo
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- CN200941100Y CN200941100Y CN 200620079515 CN200620079515U CN200941100Y CN 200941100 Y CN200941100 Y CN 200941100Y CN 200620079515 CN200620079515 CN 200620079515 CN 200620079515 U CN200620079515 U CN 200620079515U CN 200941100 Y CN200941100 Y CN 200941100Y
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- amplifying circuit
- mux
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Abstract
The utility model discloses a processing device for the multi-channel concrete ultrasonic signals, comprising a first decaying circuit connected respectively with a first choice amplifying circuit and a third choice amplifying circuit. The first choice amplifying circuit is connected with a logic control circuit which is connected respectively with a second decaying circuit, a second choice amplifying circuit, a fourth choice amplifying circuit, a third choice amplifying circuit and a PCI controller. The fourth choice amplifying circuit is connected with the second decaying circuit which is connected with the second choice amplifying circuit. This utility model can not only achieve the traditional single-channel data acquisition, but also achieve the parallel acquisition of four-path signals and the synchronous receiving of twenty-four-path signals, enabling the ultrasonic signal detector to achieve tomography, and greatly improving the detection efficiency and accuracy.
Description
Technical field
The utility model relates to a kind of intelligence instrument that detects the inside concrete characteristic, particularly a kind of multiple-pass ultrasonic signal processing device.
Background technology
At present, typical concrete Ultrasonic Detection instrument all has single channel collection or binary channels parallel acquisition function, mostly its ultrasonic signal processing device is by attenuator circuit, amplifying circuit, combine, simulating signal converts the input signal that meets the requirement of AD capture card to through ultrasonic signal processing device, the simulating signal input channel is a single channel or twin-channel, like this, during signals collecting, can only carry out single channel collection or multi-channel parallel collection, caused the Ultrasonic Detection instrument can only carry out analyzing and processing and artificial interpretation thus to the one-dimensional signal that is received, inefficiency, reliability.Because the composite material that concrete is made up of cement, sand, thick bone loose material, simultaneously owing to testing conditions circumstance complication in the actual detected, influence factor is many, directly obtains more definitely also to have sizable difficulty and uncertainty about the description of concrete internal soundness from the one dimension received signal.In addition, mostly traditional signal processing apparatus is to communicate by isa bus, parallel interface and computing machine, and transfer rate is low, has influenced the high-speed transfer of signal.
Summary of the invention
The purpose of this utility model is to overcome above-mentioned technical deficiency, a kind of multiple-pass ultrasonic signal processing device is provided, this ultrasonic signal processing device not only can be realized traditional single channel data acquisition, also can realize the parallel acquisition of 4 road signals, synchronous reception with 24 road signals, make the ultrasonic signal detector realize that tomography becomes possibility, also improved detection efficiency and accuracy of detection simultaneously greatly.
The technical solution of the utility model is achieved in that and comprises first attenuator circuit, first attenuator circuit connects first respectively and selects amplifying circuit and the 3rd to select amplifying circuit, first selects amplifying circuit to link to each other with logic control circuit, logic control circuit also selects amplifying circuit, the 4th to select amplifying circuit, the 3rd to select amplifying circuit to link to each other with pci controller with second attenuator circuit, second respectively, the 4th selects amplifying circuit to be connected with second attenuator circuit, and second attenuator circuit and second selects amplifying circuit to be connected.
Described attenuator circuit comprises a relay U1, and relay U1 is connected by the collector of pin with triode Q1, and the base stage of triode Q1 connects resistance R 2, and resistance R 2 connects programmable logic device (PLD) U11, and resistance R 3 connects emitter-base bandgap grading and the resistance R 2 of triode Q1.Resistance R 1 and capacitor C 1 are connected in parallel on the pin of relay U1, and resistance R 4 and capacitor C 2 are connected in parallel on the pin of relay U1.The pin of relay U1 is connected with the input end S1 of MUX U3, the pin of MUX U3 is connected with programmable logic device (PLD) U11, the pin of MUX U3 connects the pin of variable gain amplifier U4, the pin of variable gain amplifier U4 is connected with programmable logic device (PLD) U11, resistance R 7 connects the pin of MUX U3, resistance R 8 connects the pin of variable gain amplifier U4, and resistance R 9 connects the pin of variable gain amplifier U4.The pin of relay U1 is connected with the input end S1 of MUX U5, the pin of MUX U5 is connected with programmable logic device (PLD) U11, the pin of MUX U5 connects the pin of variable gain amplifier U6, the pin of variable gain amplifier U6 is connected with programmable logic device (PLD) U11, resistance R 10 connects the pin of MUX U5, resistance R 11 connects the pin 7 of variable gain amplifier U6, and resistance R 12 connects the pin of variable gain amplifier U6.
Described relay U1 adopts TQ2.
MUX U3, MUX U5 all adopt ADG508F.
Variable gain amplifier U4, variable gain amplifier U6 adopt PGA202.
The utility model provides 24 tunnel analog channels, by 4 MUX 24 tunnel simulating signals are carried out time-sharing multiplex, to the analog signal channel of choosing decay, processing such as amplification, attenuator circuit is by the selection of relay and triode realization attenuation multiple, and 4 amplifiers choose the simulating signal of passage to amplify to 4 MUX respectively.Use programmable logic device (PLD) to realize the sequential control and the logic decoding of whole signal processing apparatus, pci controller is realized the interface of signal processing card and computing machine.This signal processing apparatus not only can be realized traditional single channel data acquisition, also can realize the parallel acquisition of 4 road signals, synchronous reception with 24 road signals, adopt pci bus and computer interface, transmission speed is fast, support the concurrent working mode, make signal processing apparatus can with the CPU concurrent working.
Description of drawings
Fig. 1 is the utility model principle assumption diagram
Fig. 2 is the utility model circuit diagram.
Fig. 3 is the subsequent figure of Fig. 2.
Embodiment
With reference to shown in Figure 1, comprise first attenuator circuit 1, first attenuator circuit 1 connects first respectively and selects amplifying circuit 2 and the 3rd to select amplifying circuit 6, first selects amplifying circuit 2 to link to each other with logic control circuit 4, logic control circuit 4 also selects amplifying circuit the 5, the 4th to select amplifying circuit the 7, the 3rd to select amplifying circuit 6 to link to each other with pci controller 3 with second attenuator circuit 8, second respectively, the 4th selects amplifying circuit 7 to be connected with second attenuator circuit 8, and second attenuator circuit 8 and second selects amplifying circuit 5 to be connected.
Shown in Fig. 2,3, relay U1 is connected with the collector of triode Q1 by pin 10, and the base stage of triode Q1 connects resistance R 2, and resistance R 2 connects programmable logic device (PLD) U11, and resistance R 3 connects emitter-base bandgap grading and the resistance R 2 of triode Q1.Resistance R 1 and capacitor C 1 are connected in parallel on the pin 2 and 4 of relay U1, and resistance R 4 and capacitor C 2 are connected in parallel on the pin 7 and 9 of relay U1.The pin 3 of relay U1 is connected with the input end S1 of MUX U3, pin A0, the A1 of MUX U3, A2 are connected with programmable logic device (PLD) U11, the pin 8 of MUX U3 connects the pin 8 of variable gain amplifier U4, pin A0, the A1 of variable gain amplifier U4 is connected with programmable logic device (PLD) U11, resistance R 7 connects the pin 8 of MUX U3, resistance R 8 connects the pin 7 of variable gain amplifier U4, and resistance R 9 connects the pin 12 of variable gain amplifier U4.The pin 8 of relay U1 is connected with the input end S1 of MUX U5, pin A0, the A1 of MUX U5, A2 are connected with programmable logic device (PLD) U11, the pin 8 of MUX U5 connects the pin 8 of variable gain amplifier U6, pin A0, the A1 of variable gain amplifier U6 is connected with programmable logic device (PLD) U11, resistance R 10 connects the pin 8 of MUX U5, resistance R 11 connects the pin 7 of variable gain amplifier U6, and resistance R 12 connects the pin 12 of variable gain amplifier U6.Programmable logic device (PLD) U11 connects pci controller U12, and pci controller connects P1.
The course of work is: the two-way simulating signal at first enters relay U3, resistance R 1, capacitor C 1 constitute the 10:1 potential-divider network with resistance R 7, programmable logic device (PLD) U11 is by triode Q1 pilot relay, can select decay easily, enter MUX U1 through the signal of overdamping to the two-way simulating signal.This ultrasonic signal transaction card has 24 tunnel analog channels, per 6 tunnel shared MUX.Therefore, the first six road connects MUX U3, wherein, has only first via simulating signal to decay, and other five the tunnel directly connect MUX U3.MUX U3 is added in the logic level of A0, A1, A2 pin by change, selects different passages.Pin A0, the A1 of MUX U3, A2 are connected with programmable logic device (PLD) U11, and the signal of selected passage input is exported by pin D.The signal of output enters variable gain amplifier U4, and pin A0, the A1 of variable gain amplifier U4 is connected with programmable logic device (PLD) U11, is added in the logic level of A0 and A1 by change, can select different enlargement factors.Simulating signal after the processing is by the output terminal output of variable gain amplifier U4.Programmable logic device (PLD) U11 realizes decoding and logic control as control center.Programmable logic device (PLD) U11 receives the computer command that sends from pci controller U12 by 12 bit address buses and 8 bit data bus, and it is deciphered, and produces control corresponding or trigger pip according to order.
Claims (5)
1. multiple-pass ultrasonic signal processing device, comprise first attenuator circuit (1), it is characterized in that, first attenuator circuit (1) connects first respectively and selects amplifying circuit (2) and the 3rd to select amplifying circuit (6), first selects amplifying circuit (2) to link to each other with logic control circuit (4), logic control circuit (4) also respectively with second attenuator circuit (8), second selects amplifying circuit (5), the 4th selects amplifying circuit (7), the 3rd selects amplifying circuit (6) to link to each other with pci controller (3), the 4th selects amplifying circuit (7) to be connected with second attenuator circuit (8), and second attenuator circuit (8) and second selects amplifying circuit (5) to be connected.
2, multiple-pass ultrasonic signal processing device according to claim 1, it is characterized in that, described first attenuator circuit (1) comprises a relay U1, relay U1 is connected with the collector of triode Q1 by pin (10), the base stage of triode Q1 connects resistance R 2, resistance R 2 connects programmable logic device (PLD) U11, resistance R 3 connects emitter-base bandgap grading and the resistance R 2 of triode Q1, resistance R 1 and capacitor C 1 are connected in parallel on the pin (2 of relay U1,4), resistance R 4 and capacitor C 2 are connected in parallel on the pin (7 of relay U1,9) on, the pin of relay U1 (3) is connected with the input end S1 of MUX U3, pin (the A0 of MUX U3, A1, A2) be connected with programmable logic device (PLD) U11, the pin 8 of MUX U3 connects the pin 8 of variable gain amplifier U4, the pin A0 of variable gain amplifier U4, A1 is connected with programmable logic device (PLD) U11, resistance R 7 connects the pin (8) of MUX U3, resistance R 8 connects the pin (7) of variable gain amplifier U4, resistance R 9 connects the pin (12) of variable gain amplifier U4, the pin of relay U1 (8) is connected with the input end S1 of MUX U5, pin (the A0 of MUX U5, A1, A2) be connected with programmable logic device (PLD) U11, the pin 8 of MUX U5 connects the pin (8) of variable gain amplifier U6, pin (the A0 of variable gain amplifier U6, A1) be connected with programmable logic device (PLD) U11, resistance R 10 connects the pin 8 of MUX U5, resistance R 11 connects the pin (7) of variable gain amplifier U6, and resistance R 12 connects the pin (12) of variable gain amplifier U6.
3, multiple-pass ultrasonic signal processing device according to claim 2 is characterized in that, described relay U1 adopts TQ2.
4, multiple-pass ultrasonic signal processing device according to claim 2 is characterized in that, MUX U3, MUX U5 all adopt ADG508F.
5, multiple-pass ultrasonic signal processing device according to claim 2 is characterized in that, variable gain amplifier U4, variable gain amplifier U6 adopt PGA202.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200620079515 CN200941100Y (en) | 2006-08-03 | 2006-08-03 | Multi-channel concrete signals processor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200620079515 CN200941100Y (en) | 2006-08-03 | 2006-08-03 | Multi-channel concrete signals processor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN200941100Y true CN200941100Y (en) | 2007-08-29 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200620079515 Expired - Lifetime CN200941100Y (en) | 2006-08-03 | 2006-08-03 | Multi-channel concrete signals processor |
Country Status (1)
| Country | Link |
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| CN (1) | CN200941100Y (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100495020C (en) * | 2006-08-03 | 2009-06-03 | 长安大学 | Multiple-passage concrete ultrasonic signal processing device |
-
2006
- 2006-08-03 CN CN 200620079515 patent/CN200941100Y/en not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100495020C (en) * | 2006-08-03 | 2009-06-03 | 长安大学 | Multiple-passage concrete ultrasonic signal processing device |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| AV01 | Patent right actively abandoned |
Effective date of abandoning: 20060803 |
|
| C25 | Abandonment of patent right or utility model to avoid double patenting |