CN2938090Y - Network concrete ultrasonic signal collector - Google Patents

Abstract

The utility model discloses a networking concrete ultrasonic signals collecting apparatus, comprising a network interface which is connected to a complex programmable logic device array (CPLD); the complex programmable logic device array is connected with a FIFO(first in first out)memorizer and is also connected with an A/D converter and a D/A converter; a plurality of magnifiers are also comprised which are connected with a single terminal slip bleeder circuit; the single terminal slip bleeder circuit is connected to a variable gain amplifier which is connected with the A/D converter. The utility model has the advantages of high working efficiency and small occupying area and remote control and transmission.

Description

Ultrasonic signal sampler for network concrete

Technical field

The utility model relates to a kind of concrete ultrasonic signal sampler, particularly ultrasonic signal sampler for network concrete.

Background technology

At present, concrete ultrasonic signal detector mainly is divided into two kinds in SCM Based portable ultraphonic signal sampler and integrated microcomputer control concrete ultrasound acquisition instrument.For the former, normally by chip microcontroller signals collecting and work of treatment, most Acquisition Instrument communicates by serial line interface RS232, RS485 etc., because the serial communication transmission range is short, poor anti jamming capability, is difficult to realize Long-distance Control.For the latter, normally built-in A/D capture card and signal processing circuit realize in microcomputer, because of its volume, weight are big, carry inconvenience, require than higher detecting site contour, are difficult to realize the testing under the strategically located and difficult of access environment of landform.In addition, traditional concrete ultrasonic signal sampler can only be realized single-pass, road or twin-channel signals collecting, and sampling rate is low, can't realize high-speed signal acquisition.

Summary of the invention

The purpose of this utility model is to overcome above-mentioned prior art deficiency, and a kind of ultrasonic signal sampler for network concrete is provided, this monitor high efficiency, and volume is little, can realize Long-distance Control and transmission.

The technical solution of the utility model is achieved in that the network interface that comprises of the present utility model, this network interface links to each other with programmable logic array CPLD, programmable logic array CPLD is connected with storer FIFO, programmable logic array CPLD connects A/D converter and D/A converter respectively, wherein also comprise a plurality of amplifiers, this amplifier links to each other with the single-ended transfer difference circuit, and the single-ended transfer difference circuit links to each other with variable gain amplifier, and variable gain amplifier is connected with A/D converter.

The capacity of storer FIFO is 32K.

Advantage of the present utility model is:

1,24 passage high-speed parallel signal samplers can realize that hyperchannel carries out data acquisition simultaneously, and data sync receives, and has improved work on the spot efficient greatly.In addition, multi-channel synchronous receives the precision that can guarantee data sampling.

2, the utility model adopts programmable logic device (PLD) to realize the control of whole instrument, and the instrument volume is little, in light weight, easy to carry.

3, carry out data communication by Ethernet, transfer rate is fast, the reliability height.

4, with the instrument access network based on ethernet, can obtain detection information from any node of network, realize sharing of detection information, also can send control information to on-the-spot signal sampler in addition by network;

5, many signal samplers that the geographic position disperses can be connected by network, centralized management, thus improved usage ratio of equipment, saved human and material resources and financial resources.

Description of drawings

Fig. 1 is the general structure schematic diagram of the utility model signal sampler.

Fig. 2 is the utility model signal acquisition circuit schematic diagram.

Fig. 3 is the utility model network interface circuit schematic diagram.

Accompanying drawing is a specific embodiment of the utility model;

Below in conjunction with accompanying drawing content of the present utility model is described in further detail.

Embodiment

With reference to shown in Figure 1, the signal sampler in the utility model is made up of programmable logic array CPLD, network interface, signals collecting and storage array.Network interface links to each other with programmable logic array CPLD, and signals collecting and storage array have 24 paths, and 24 paths annexations are identical, narrates wherein passage at this.Receive simulating signal and at first enter prime amplifier, prime amplifier connects the single-ended transfer difference circuit, the single-ended transfer difference circuit connects variable gain amplifier, variable gain amplifier connects AD converter, AD converter connects 32K storer FIFO, and storer FIFO connects programmable logic array CPLD.The DA converter provides gain control for variable gain amplifier, and the DA converter connects variable gain amplifier and programmable logic array CPLD respectively, and AD converter connects programmable logic array CPLD.

Its course of work be will input simulating signal at first send amplifier to, be subjected to the shortcoming of external electromagnetic interference easily for fear of single-ended signal, the simulating signal through amplifying changes differential signal into by the single-ended transfer difference circuit.In order to improve lower range sensitivity, use variable gain amplifier, differential signal is selectively amplified.After the differential signal of a series of processing of process meets the requirement of A/D converter, just enter A/D converter and carry out the A/D conversion, the digital signal after the conversion is stored in reading of the medium machine to be calculated of storer FIFO.Signal sampler and computing machine carry out message exchange by network interface, computing machine will dispose by network interface and control command sends programmable logic array CPLD to, programmable logic array CPLD realizes command analysis and sends control signal, when programmable logic array CPLD receives the order of reading sampled value, data among the storer FIFO send programmable logic array CPLD to by data line, send computing machine again to through programmable logic array CPLD; When programmable logic array CPLD received the order that begins to gather, programmable logic array CPLD produced the trigger pip of transmitting transducer and AD conversion, and signals collecting and storage array begin image data and preserve.

With reference to shown in Figure 2, the two-way simulating signal that receives sends the input end (5 and 3) of two-path amplifier AD8616U1 respectively to by J1, slot J1 links to each other with the voltage input end (6 and 8) of amplifier AD8616U1 respectively, for its provide+2.5V and-aanalogvoltage of 2.5V.Simulating signal is through amplifier AD8616U1, and the signal that enters from input end 3 amplifies output by output terminal 1, and the signal that enters from input end 5 amplifies output by output terminal 7.For fear of the noise that single-ended signal brings, adopt amplifier TH4121U2 and U6 that the two-way single-ended signal from amplifier AD8616U1 output is converted to differential signal respectively because the two-way Acquisition Circuit is identical, thus following only introduce wherein a road.The output terminal of amplifier AD8616U1 links to each other with the input end 8 of amplifier TH4121U2, behind amplifier TH4121U2, signal is by the single-ended differential signal that becomes, the output terminal 4 and 5 of amplifier TH4121U2 is exported high low-voltage respectively, the output terminal 4 of amplifier TH4121U2 links to each other with 5 with the input end 4 of variable gain amplifier AD8330U3 respectively with 5, two kinds of gain modes that variable gain amplifier AD8330U3 has make gain margin can reach-30dB～70dB, and a kind of gain mode is the magnitude of voltage adjusting enlargement factor that is added in pin VDBS by change; Another kind is to reconfigure basic gain margin by pin VMAG.The pin VDBS of variable gain amplifier AD8330U3 links to each other with the pin 18 of J1, and pin VMAG links to each other with the pin 19 of J1, and controller is configured pin VDBS and VMAG by J1 on the mainboard.Differential signal is by after amplifying, and by output terminal pin 13 and pin 12 outputs of variable gain amplifier AD8330U3, pin 13 links to each other with the input end 9 of AD converter AD9235U4, and pin 12 links to each other with the input end 10 of AD converter AD9235U4.The resolution of AD converter AD9235U4 is 12, and the sampling rate maximum can arrive per second 20M sampled point.Because A/D sampling rate height, and be multi-channel parallel, and the Ethernet transmission bandwidth is limited, data after the A/D conversion can not be uploaded to remote computer in real time, so this circuit adopts the memory I DT72V275U5 temporal data of degree of depth 32K, treat once to gather and pass to remote computer by network interface successively again after finishing.Simulating signal is by the AD conversion of AD converter AD9235U4, become 12 digital signal, by output terminal D0～D11 output of AD converter AD9235U4, output terminal D0～D11 of AD converter AD9235U4 links to each other with input end D0～D11 of memory I DT72V275U5.Memory I DT72V275U5 is the first-in first-out type storer, the digital signal that collects is temporarily stored among the memory I DT72V275U5, after once collection was finished, by output terminal Q0～Q11 output of memory I DT72V275U5, Q0～Q11 and slot J1 exported controller on the mainboard to by slot J1.The input pin 64 of memory I DT72V275U5 links to each other with slot J1, and DT72V275U5 provides write control logic for memory I.The input pin 52 of memory I DT72V275U5 links to each other with slot J1, reads steering logic for memory I DT72V275U5 provides.The input pin 62 of memory I DT72V275U5 and linking to each other of slot J1, DT72V275U5 provides reset signal for memory I.The input pin 51 of memory I DT72V275U5 links to each other with slot J1 with 49, and being respectively memory I DT72V275U5 provides and read to allow control signal and storer to enable control signal.

With reference to shown in Figure 3, network interface adopts the network processing unit IP2022U10 of Ubicom company, and it can directly link to each other with various network interfaces commonly used by two full duplex serializer/de-serializers.Can realize 10Base-T Ethernet, USB and other various quick serial protocols in the sheet.Serial/deserializer in the network processing unit IP2022U10 is converted to the RS232 interface COM1 of standard by serial ports change-over circuit MAX3232U12, the pin 44 of network processing unit IP2022U10 is connected with 11 with the pin 12 of serial ports change-over circuit MAX3232U12 respectively with 46, the pin 13 of serial ports change-over circuit MAX3232U12 is connected pin 5 ground connection of RS232 interface COM1 with 2 of RS232 interface COM1 with 3 respectively with 14.On network processing unit IP2022U10 single-chip, I/O mouth operating voltage is 3.3V, and the Ethernet interface required voltage is 5V, in order to make the voltage matches at two ends, in Ethernet interface part, insert the cmos buffer device 74AHC04U11 of a 5V, after meet the RJ45 interface LF1S021T1 of built-in ethernet transformer.Connect the active crystal oscillator of 4.8M between the OSC1 of network processing unit IP2022U10 and the OSC2.

Claims (2)

1. ultrasonic signal sampler for network concrete, comprise a network interface, it is characterized in that, this network interface links to each other with programmable logic array CPLD, and programmable logic array CPLD is connected with storer FIFO, and programmable logic array CPLD connects A/D converter and D/A converter respectively, wherein also comprise a plurality of amplifiers, this amplifier links to each other with the single-ended transfer difference circuit, and the single-ended transfer difference circuit links to each other with variable gain amplifier, and variable gain amplifier is connected with A/D converter.

2, ultrasonic signal sampler for network concrete according to claim 1 is characterized in that, the capacity of storer FIFO is 32K.

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