CN1996750A

CN1996750A - Difference input range-limiting amplifier

Info

Publication number: CN1996750A
Application number: CN 200610169723
Authority: CN
Inventors: 李海松; 边疆; 权海洋
Original assignee: Mxtronics Corp
Current assignee: Beijing times people core technology Co., Ltd.; China Aerospace Modern Electronic Company 772nd Institute
Priority date: 2006-12-28
Filing date: 2006-12-28
Publication date: 2007-07-11
Anticipated expiration: 2026-12-28
Also published as: CN100550613C

Abstract

This invention relates to one different input limit range amplifier, which comprises two limit range circuits, two resistance division network, two current lens array and computation amplifier, wherein, the different input signals P1 and P2 are connected to the resistance division network and second resistance network and reference input voltage is connected to the first resistance network; the second current lens output end is connected to the input end of second limit circuit; the first limit circuit output end is connected to the input end of first current lens array and second resistance division network.

Description

Difference input range-limiting amplifier

Technical field

The present invention relates to a kind of difference input range-limiting amplifier, can realize input signal at the amplitude limit preferably in amplitude limit district with at amplification region favorable linearity amplification.

Background technology

In recent years, along with telecommunications network, computer network and INTERNET rapid network development, the extensive use of multimedia communication, the Large scale construction of information superhighway is more and more higher to the requirement of high-speed communication system.Difference input range-limiting amplifier is widely used in satellite communication, and radar system is in the systems such as optical fiber communication.Limiting amplifier has following effect: at first, it can be used as the main amplifier of receiver; Secondly, it can be used in the amplitude that limits in the clock recovery circuitry from the detected clock signal of data input pin in conjunction with passive filter; And it can also be used for inputoutput buffer data and clock signal are carried out shaping.

External a lot of to the research of limiting amplifier, the kind of limiting amplifier is also varied, can be divided into the CMOS structure on technology, BICMOS structure, SIGE structure and SI_POLAR structure; On performance, can be divided into high-gain again, low-power consumption and limiting amplifier at a high speed etc.The limiting amplifier structure that home and overseas is studied is more similar, generally comprising input buffering level, two～level Four difference amplifying unit, output buffer stage and a pair of overall direct current negative feedback network four parts forms, and the input signal in the end output of one-level amplifying unit reaches the amplitude limit state, realizes the function of amplitude limit; The input buffering level realizes impedance matching and level shift, and the output buffer stage realizes impedance matching and enough big driving force is provided; Overall situation direct current negative feedback network is used for stable operating point and DC current gain.This structure has its advantage, as to Noise Suppression, gain is big, matching is good etc., but this limiting amplifier structure more complicated, and the amplitude of amplitude limit is not easy to regulate, and the limiting amplifier of the present invention's design is not only simple in structure, and the amplitude limit amplitude range of output waveform can be that up-down adjustment is carried out at the center with level Vref easily.

Summary of the invention

Technology of the present invention is dealt with problems: overcome the deficiencies in the prior art, propose a kind of have at linear input range internal linear degree good, when the absolute value of input voltage was worth greater than certain, the amplitude limit effect was better, and loop has the difference input range-limiting amplifier of good stability.

Technical solution of the present invention: the limiting amplifier of difference input, its characteristics are: be made up of first amplitude limiter circuit, second amplitude limiter circuit, first resistance pressure-dividing network, second resistance pressure-dividing network, first current lens array, second current lens array, operational amplifier, differential input signal P1 links to each other with second resistance pressure-dividing network with first resistance pressure-dividing network respectively with P2, and reference input voltage Vref links to each other with first resistance pressure-dividing network; The output of second current lens array links to each other with the input of first current lens array, the input of first amplitude limiter circuit and the input of second amplitude limiter circuit respectively; First limit circuit output end links to each other with the input of first current lens array with second resistance pressure-dividing network respectively; Second limit circuit output end links to each other with the input of first current lens array with first resistance pressure-dividing network respectively; The output of first resistance pressure-dividing network links to each other with the input of first amplitude limiter circuit and operational amplifier respectively; The output of second resistance pressure-dividing network links to each other with the input of second amplitude limiter circuit and operational amplifier respectively; Operational amplifier output final result Vout.

The course of work of the present invention: the effect of first amplitude limiter circuit and second amplitude limiter circuit is that differential input signal P1 and P2 are carried out amplitude limit respectively, promptly when input signal P1 magnitude of voltage less than zero the time, second amplitude limiter circuit works voltage limit that Q6 order about the zero width of cloth; When input signal P2 magnitude of voltage less than zero the time, first amplitude limiter circuit works voltage limit that Q5 order about the zero width of cloth; Signal behind the amplitude limit obtains suitable level after through first resistance pressure-dividing network and the second resistance pressure-dividing network dividing potential drop and inputs to operational amplifier respectively, under the acting in conjunction of first resistance pressure-dividing network, second resistance pressure-dividing network and operational amplifier, make output as a result Vout be a piecewise function about Vref and P1, P2 voltage magnitude; First current array and second current array provide bias current to guarantee the operate as normal of circuit for circuit.

The present invention's advantage compared with prior art is: the present invention is by being provided with resistance pressure-dividing network and being used operational amplifier, in linear input range, can obtain output voltage increment and the good linear relationship of input voltage difference, when the absolute value of input voltage is worth greater than certain, output voltage values is main relevant with reference voltage and very faint with the relation of input signal, thereby reaches the purpose of amplitude limit; And loop has good stable, incoming level that can clamped negative value.By the SPECTRA simulator checking of CADENCE, the result proves that this circuit has above-mentioned function and performance.

Description of drawings

Fig. 1 is difference input range-limiting amplifier input signal P1 of the present invention and P2 sequential and magnitude relation figure;

Fig. 2 is a difference input range-limiting amplifier theory diagram of the present invention;

Fig. 3 is a difference input range-limiting amplifier electrical schematic diagram of the present invention.

Embodiment

As Fig. 2, shown in Figure 3, difference input range-limiting amplifier of the present invention is made up of first amplitude limiter circuit 811, second amplitude limiter circuit 812, first resistance pressure-dividing network 813, second resistance pressure-dividing network 814, first current lens array 815, second current lens array 816 and operational amplifier 817.

Input reference signal Vref is as the reference level of difference input range-limiting amplifier output level, and the output voltage of difference input range-limiting amplifier will be that the center swings up and down with Vref, and general Vref is 0.5 times a vdd voltage.

First resistance pressure-dividing network 813 is by resistance 131, resistance 132, resistance 133, resistance 134 is connected in series in turn, one end of resistance 134 links to each other with data input pin P1, one end of resistance 131 links to each other with reference level Vref, resistance 131 links to each other with the input (base stage of NPN pipe 174) of link to each other a Q3 and the operational amplifier 817 of resistance 132, the input of link to each other a Q2 and the amplitude limiter circuit 811 of resistance 132 and resistance 133 (collector electrode of NPN pipe 115) links to each other, and the tie point Q6 of resistance 133 and resistance 134 and the output of amplitude limiter circuit 812 (NPN pipe 124 links to each other a little with the emitter of NPN pipe 125) link to each other.

Second resistance pressure-dividing network 814 is by resistance 141, resistance 142, resistance 143, resistance 144 is connected in series in turn, one end of resistance 144 links to each other with data input pin P2, the emitter of NPN pipe 178 links to each other with the drain terminal of NMOS pipe 157 in the current lens array 815 and links to each other with a section of resistance 141 in the operational amplifier 817, resistance 141 links to each other with the input (base stage of NPN pipe 173) of link to each other a Q1 and the operational amplifier 817 of resistance 142, the input of link to each other a Q2 and the amplitude limiter circuit 812 of resistance 142 and resistance 143 (collector electrode of NPN pipe 125) links to each other, and the tie point Q5 of resistance 143 and resistance 144 and the output of amplitude limiter circuit 811 (NPN pipe 114 links to each other a little with the emitter of NPN pipe 115) link to each other.For two inputs that make circuit have good coupling input impedance, need make the resistance sum of resistance 131, resistance 132, resistance 133 and resistance 134 equal the resistance sum of resistance 141, resistance 142, resistance 143 and resistance 144, and in order to obtain good linear relationship between output voltage increment and the input voltage difference, and have good amplitude limit effect simultaneously, need to adjust each resistance of resistance 131, resistance 132, resistance 133, resistance 134, resistance 141, resistance 142, resistance 143 and resistance 144.

First amplitude limiter circuit 811 is by NPN pipe 111, NPN pipe 112, NPN pipe 113, NPN pipe 114, NPN pipe 115 is formed, the collector electrode of the base stage of the base stage of NPN pipe 111 and NPN pipe 112 and NPN pipe 113 link to each other and with current lens array 816 in PMOS manage 162 drain terminal and link to each other, NPN pipe 111 links to each other with the power supply vdd terminal respectively with the collector electrode of NPN pipe 112, the emitter of NPN pipe 111 links to each other and links to each other with the drain terminal of NMOS pipe 153 in the current source array 815 with the base stage of NPN pipe 114 and the base stage of NPN pipe 115, the emitter of NPN pipe 112 links to each other with the base stage of NPN pipe 113 and links to each other with the collector electrode of NPN pipe 114, and the emitter of NPN pipe 113 is held with receiving.Amplitude limiter circuit 811 is achieved as follows function: when input signal P1 on the occasion of, P2 is a negative value and during less than certain value, it may make the low and 0V of Q5 point, but this moment is owing to the emitter of NPN pipe 113 is held with receiving, so the base potential of NPN pipe 113 is a Vbe, therefore NPN pipe 111 is the Vbe of twice with the base potential of NPN pipe 112, emitter owing to NPN pipe 111 links to each other with the base stage of NPN pipe 114 with NPN pipe 115 again, should be 0V so easily release the emitter current potential of NPN pipe 114 and NPN pipe 115, thereby it is the current potential that Q5 is ordered is clamped to 0V, no matter how little input signal P2 value have in other words, and the current potential that Q5 is ordered also can be by clamped to 0V; Same because the existence of amplitude limiter circuit 812, no matter input signal P1 value have how little, Q6 current potential also can be arrived 0V by clamped, thereby get to the purpose of clamped input negative level.

Second amplitude limiter circuit 812 is by NPN pipe 121, NPN pipe 122, NPN pipe 123, NPN pipe 124, NPN pipe 125 is formed, the collector electrode of the base stage of the base stage of NPN pipe 121 and NPN pipe 122 and NPN pipe 123 link to each other and with current lens array 816 in PMOS manage 163 drain terminal and link to each other, NPN pipe 121 links to each other with the power supply vdd terminal respectively with the collector electrode of NPN pipe 122, the emitter of NPN pipe 121 links to each other and links to each other with the drain terminal of NMOS pipe 154 in the current source array 815 with the base stage of NPN pipe 124 and the base stage of NPN pipe 125, the emitter of NPN pipe 122 links to each other with the base stage of NPN pipe 123 and links to each other with the collector electrode of NPN pipe 124, and the emitter of NPN pipe 123 is held with receiving.

First current lens array 815 is by NMOS pipe 151, NMOS pipe 152, NMOS pipe 153, NMOS pipe 154, NMOS pipe 155, NMOS pipe 156 grid altogether is formed by connecting, and their grid link to each other and link to each other with reference current Iref with the drain terminal of NMOS pipe 151, their source end all is connected to ground, the drain terminal of NMOS pipe 152 links to each other with the drain terminal of PMOS pipe 161 in the current lens array 816, the drain terminal of NMOS pipe 155 links to each other with the point that links to each other of resistance 176 with the resistance 175 of operational amplifier 817, the drain terminal of NMOS pipe 156 respectively with operational amplifier 817 in the drain terminal of PMOS pipe 177 link to each other with the base stage of electric capacity 182 1 ends and NPN pipe 178, NPN manages 178 emitter and links to each other in the drain terminal of NMOS pipe 157 and the operational amplifier 817; Current lens array 816 is by PMOS pipe 161, PMOS pipe 162, PMOS pipe 163 grid altogether forms, and their grid link to each other with the common grid of the middle NMOS pipe of current lens array 815 and manage 161 drain terminal with the drain terminal of NMOS pipe 152 and PMOS respectively links to each other, and their source end is connected respectively to power vd D.The effect of current lens array 815 and current lens array 816 is to provide current offset to this difference input range-limiting amplifier, makes this circuit working at correct state.

Second current lens array 816 is by PMOS pipe 161, PMOS pipe 162, PMOS pipe 163 grid altogether forms, and their grid link to each other with the common grid of the middle NMOS pipe of current lens array 815 and manage 161 drain terminal with the drain terminal of NMOS pipe 152 and PMOS respectively links to each other, and their source end is connected respectively to power vd D.

Operational amplifier 817 is by PMOS pipe 171, PMOS pipe 172, NPN pipe 173, NPN pipe 174, resistance 175, resistance 176, PMOS pipe 177, NPN pipe 178, resistance 181, electric capacity 182 is formed, PMOS pipe 171 links to each other with the grid of PMOS pipe 172 and links to each other with the leakage of PMOS pipe 171 and the collector electrode of NPN pipe 173, PMOS pipe 171 is received power vd D respectively with the source end of PMOS pipe 172 and PMOS pipe 177, and the drain terminal of PMOS pipe 172 links to each other with the grid of PMOS pipe 177 and the collector electrode of NPN pipe 174, and links to each other with an end of resistance 181, the emitter of NPN pipe 173 links to each other with an end of resistance 175, one end of resistance 176 links to each other with the emitter of NPN pipe 174, and an end of resistance 181 links to each other with an end of electric capacity 182, and the collector electrode of NPN pipe 178 is received power vd D.The effect of operational amplifier 817 mainly be voltage clamping that Q1 point and Q3 are ordered at identical current potential, thereby realize that utilization resistor network 813 and resistor network 814 come computing circuit.If operational amplifier 817 is that ideal operational amplifier then can be realized when the absolute value of input voltage is worth greater than certain, output voltage values is only relevant with reference voltage and irrelevant with input signal, but the amplifier in the actual conditions is imperfect amplifier, so when the absolute value of input voltage was bigger, still can there be faint relation in output voltage values with input signal.The effect of resistance 181 and electric capacity 182 is to strengthen the degenerative stability of operational amplifier 817 loops.

Hence one can see that, and difference input range-limiting amplifier of the present invention can be realized input signal at the amplitude limit preferably in amplitude limit district with at amplification region favorable linearity amplification.

Claims

1, difference input range-limiting amplifier, it is characterized in that: form by first amplitude limiter circuit (811), second amplitude limiter circuit (812), first resistance pressure-dividing network (813), second resistance pressure-dividing network (814), first current lens array (815), second current lens array (816), operational amplifier (817), differential input signal P1 links to each other with second resistance pressure-dividing network (814) with first resistance pressure-dividing network (813) respectively with P2, and (813 link to each other reference input voltage Vref with first resistance pressure-dividing network; The output of second current lens array (816) links to each other with the input of first current lens array (815), the input of first amplitude limiter circuit (811) and the input of second amplitude limiter circuit (812) respectively; The output of first amplitude limiter circuit (811) links to each other with the input of first current lens array (815) with second resistance pressure-dividing network (814) respectively; The output of second amplitude limiter circuit (812) links to each other with the input of first current lens array (815) with first resistance pressure-dividing network (813) respectively; The output of first resistance pressure-dividing network (813) links to each other with the input of first amplitude limiter circuit (811) with operational amplifier (817) respectively; The output of second resistance pressure-dividing network (814) links to each other with the input of second amplitude limiter circuit (812) with operational amplifier (817) respectively; Operational amplifier (817) output final result Vout.

2, difference input range-limiting amplifier according to claim 1, it is characterized in that: described first resistance pressure-dividing network (813) is by resistance (131), resistance (132), resistance (133), resistance (134) is connected in series in turn, one end of resistance (134) links to each other with data input pin P1, one end of resistance (131) links to each other with reference level Vref, the input of resistance (131) and link to each other a Q3 and the operational amplifier (817) of resistance (132), the base stage that is NPN pipe (174) links to each other, the input of link to each other a Q2 and the amplitude limiter circuit (811) of resistance (132) and resistance (133), the collector electrode that is NPN pipe (115) links to each other, the output of the tie point Q6 of resistance (133) and resistance (134) and amplitude limiter circuit (812), promptly the emitter of NPN pipe (124) and NPN pipe (125) links to each other a little continuous.

3, difference input range-limiting amplifier according to claim 1, it is characterized in that: described second resistance pressure-dividing network (814) is by resistance (141), resistance (142), resistance (143), resistance (144) is connected in series in turn, one end of resistance (144) links to each other with data input pin P2, the drain terminal that NMOS manages (157) in the emitter of NPN pipe (178) and the current lens array (815) in the operational amplifier (817) links to each other and links to each other with a section of resistance (141), the input of resistance (141) and link to each other a Q1 and the operational amplifier (817) of resistance (142), the base stage that is NPN pipe (173) links to each other, the input of link to each other a Q2 and the amplitude limiter circuit (812) of resistance (142) and resistance (143), the collector electrode that is NPN pipe (125) links to each other, the output of the tie point Q5 of resistance (143) and resistance (144) and first amplitude limiter circuit (811), promptly the emitter of NPN pipe (114) and NPN pipe (115) links to each other a little continuous.

4, difference input range-limiting amplifier according to claim 1, it is characterized in that: described first amplitude limiter circuit (811) is by NPN pipe (111), NPN manages (112), NPN manages (113), NPN manages (114), NPN pipe (115) is formed, the collector electrode of the base stage of the base stage of NPN pipe (111) and NPN pipe (112) and NPN pipe (113) links to each other and links to each other with the drain terminal of the middle PMOS pipe of current lens array (816) (162), NPN pipe (111) links to each other with the power supply vdd terminal respectively with the collector electrode of NPN pipe (112), the emitter of NPN pipe (111) links to each other and links to each other with the drain terminal of NMOS pipe 153 in the current source array (815) with the base stage of NPN pipe (114) and the base stage of NPN pipe (115), the emitter of NPN pipe (112) links to each other with the base stage of NPN pipe (113) and links to each other with the collector electrode of NPN pipe (114), and the emitter of NPN pipe (113) is held with receiving.

5, difference input range-limiting amplifier according to claim 1, it is characterized in that: described second amplitude limiter circuit (812) is by NPN pipe (121), NPN manages (122), NPN manages (123), NPN manages (124), NPN pipe (125) is formed, the collector electrode of the base stage of the base stage of NPN pipe (121) and NPN pipe (122) and NPN pipe (123) links to each other and links to each other with the drain terminal of the middle PMOS pipe of current lens array (816) (163), NPN pipe (121) links to each other with the power supply vdd terminal respectively with the collector electrode of NPN pipe (122), the emitter of NPN pipe (121) links to each other and links to each other with the drain terminal of NMOS pipe (154) in the current source array (815) with the base stage of NPN pipe (124) and the base stage of NPN pipe (125), the emitter of NPN pipe (122) links to each other with the base stage of NPN pipe (123) and links to each other with the collector electrode of NPN pipe (124), and the emitter of NPN pipe (123) is held with receiving.

6, difference input range-limiting amplifier according to claim 1, it is characterized in that: described first current lens array (815) is by NMOS pipe (151), NMOS manages (152), NMOS manages (153), NMOS manages (154), NMOS manages (155), NMOS pipe (156) grid altogether is formed by connecting, and their grid link to each other and link to each other with reference current Iref with the drain terminal of NMOS pipe (151), their source end all is connected to ground, the drain terminal of NMOS pipe (152) links to each other with the drain terminal of PMOS pipe (161) in the current lens array (816), the drain terminal of NMOS pipe (155) links to each other with the point that links to each other of resistance (176) with the resistance (175) of operational amplifier (817), the drain terminal that NMOS manages (156) links to each other with the base stage of electric capacity (182) one ends and NPN pipe (178) with the drain terminal of the middle PMOS pipe of operational amplifier (817) (177) respectively, and the drain terminal of NMOS pipe (157) links to each other with the emitter that the middle NPN of operational amplifier (817) manages (178); Current lens array (816) is by PMOS pipe (161), PMOS manages (162), PMOS pipe (163) grid altogether forms, and their grid link to each other with the common grid of the middle NMOS pipe of current lens array (815) and manage the drain terminal of (152) with NMOS respectively and the drain terminal of PMOS pipe (161) links to each other, and their source end is connected respectively to power vd D.

7, difference input range-limiting amplifier according to claim 1, it is characterized in that: described second current lens array (816) is by PMOS pipe (161), PMOS manages (162), PMOS pipe (163) grid altogether forms, and their grid link to each other with the common grid of the middle NMOS pipe of current lens array (815) and manage the drain terminal of (152) with NMOS respectively and the drain terminal of PMOS pipe (161) links to each other, and their source end is connected respectively to power vd D.

8, difference input range-limiting amplifier according to claim 1, it is characterized in that: described operational amplifier (817) is imported the three-stage operational amplifier of single-ended output for both-end, with reference-input signal Vref is benchmark, realizes the amplification to the operational amplifier input signal.

9, limiting amplifier according to claim 1 or 8 described difference inputs, it is characterized in that: described operational amplifier (817) is by PMOS pipe (171), PMOS manages (172), NPN manages (173), NPN manages (174), resistance (175), resistance (176), PMOS manages (177), NPN manages (178), resistance (181), electric capacity (182) is formed, and PMOS pipe (171) links to each other with the grid of PMOS pipe (172) and links to each other with the leakage of PMOS pipe (171) and the collector electrode of NPN pipe (173), and PMOS pipe (171) is received power vd D respectively with the source end of PMOS pipe (172) and PMOS pipe (177), the drain terminal of PMOS pipe (172) links to each other with the grid of PMOS pipe (177) and the collector electrode of NPN pipe (174), and link to each other with an end of resistance (181), the emitter of NPN pipe (173) links to each other with an end of resistance (175), and an end of resistance (176) links to each other with the emitter that NPN manages (174), one end of resistance (181) links to each other with an end of electric capacity (182), and the collector electrode of NPN pipe (178) is received power vd D.

10, difference input range-limiting amplifier according to claim 1 is characterized in that: described first current lens array (815) and second current lens array (816) are to be obtained by mirror image by same reference current source.