CN1992077A - Nonvolatile semiconductor memory device - Google Patents
Nonvolatile semiconductor memory device Download PDFInfo
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- CN1992077A CN1992077A CN200610170466.1A CN200610170466A CN1992077A CN 1992077 A CN1992077 A CN 1992077A CN 200610170466 A CN200610170466 A CN 200610170466A CN 1992077 A CN1992077 A CN 1992077A
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
- H10B63/80—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
- G11C11/225—Auxiliary circuits
- G11C11/2259—Cell access
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B51/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors
- H10B51/30—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the memory core region
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
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Abstract
A nonvolatile semiconductor memory device includes three-dimensional cell arrays to reduce the chip size. The cell arrays each having unit cells arranged in row and column directions includes multi-layered unit block cell arrays. Based on the deposition direction of the cell arrays, a unit bank cell array includes the unit block cell arrays arranged in directions X, Y, and Z in a given group. A plurality of unit bank cell arrays are configured to perform read/write operations individually.
Description
Related application
The application is based on the korean patent application 10-2005-135236 that submitted on Dec 30th, 2005 and 10-2005-135237 number and requires its benefit of priority, and its all the elements are incorporated herein by reference.
Technical field
By and large, the present invention relates to non-volatile memory semiconductor device, and relate to more specifically and comprise that three-dimensional cell arrays is to reduce the semiconductor storage unit of chip size.
Background technology
Nonvolatile ferroelectric memory, for example, ferroelectric RAM (Ferroelectric Random Access Memory as the candidate of memory device of future generation, FeRAM) device, attracted considerable attention, because it has and dynamic RAM (DynamicRandom Access Memory, DRAM) equally fast data processing speed is even and also can preserve data behind power remove.
The FeRAM that has with the DRAM similar structures comprises the capacitor of being made by ferroelectric material, has high residual polarization (residual polarization), also allows the reservation of data behind power remove.
The unit cell of traditional non-volatile FeRAM device (unit cell) comprises on-off element and Nonvolatile ferroelectric capacitor.On-off element is carried out switching manipulation according to the state of word line, so that the Nonvolatile ferroelectric capacitor is connected to sub-bit-line.The Nonvolatile ferroelectric capacitor is connected between the terminal of printed line (plate line) and on-off element.At this, the on-off element of traditional F eRAM is a nmos pass transistor, and its switching manipulation is controlled by grid-control system signal.
In traditional F eRAM, when unit size becomes more hour, the data retention characteristic can reduce.Therefore, be difficult to carry out normal running to the unit.For example, when the read mode in the unit, when voltage was applied to adjacent cells, data can be destroyed owing to the interface noise (interface noise) that produces between the unit.In addition, when the pattern that writes in the unit, when writing voltage and being applied to unselected unit, the data of described unselected unit are destroyed, therefore can't facilitate random access operation.
For metallic iron Electric insulator silicon (Metal Ferroelectric Insulator Silicon, MFIS) and metallic iron electric metal insulator silicon (Metal Ferroelectric Metal Insulator Silicon, MFMIS), the data retention characteristic is depolarized electric charge (depolarization charge) and reduces.
Summary of the invention
Each embodiment of the present invention relates to provides a kind of non-volatile memory semiconductor device, described non-volatile memory semiconductor device comprises a plurality of vertical multilayer units chunk cell arrays, described a plurality of vertical multilayer units chunk cell array is arranged on the row and column direction to reduce chip size, and described a plurality of vertical multilayer units chunk cell array is divided (bank) in groups, so that carry out read by described group.
According to an embodiment consistent with the present invention, a kind of non-volatile memory semiconductor device comprises the units chunk cell array, described units chunk cell array comprises a plurality of multilevel-cell arrays, and each all has a plurality of unit cells that are arranged on the row and column direction described a plurality of multilevel-cell arrays.A plurality of unit bank cell arrays, each comprises a plurality of units chunk cell arrays with given group form, based on the placement direction of a plurality of cell arrays and be arranged in direction X, on Y and the Z, so that carry out read respectively.
According to an embodiment consistent with the present invention, a kind of non-volatile memory semiconductor device comprises: the first module array, comprise a plurality of unit cells, and each unit cell is arranged on the row and column direction; At least one second cell array, each comprises and is arranged in the row and column direction and with respect to a plurality of unit cells on the vertical direction of described first module array; The units chunk cell array comprises described first module array and described second cell array; And unit bank cell arrays, comprise at least one units chunk cell array.Described units chunk cell array comprises one that selects from described first module array and described second cell array according to vertical address.
According to an embodiment consistent with the present invention, a kind of non-volatile memory semiconductor device comprises: the units chunk cell array, comprise a plurality of vertical multilevel-cell arrays, each have arrange be expert at and column direction on a plurality of unit cells; Row-address decoder is configured to the decoded row address, the word line of one of cell array of selecting with excitation; Vertical address decoding unit, the vertical address of being configured to decode corresponding to one of cell array of selecting, and the output signal of described row-address decoder is connected to the word line of the cell array of selection; And column address decoder, be configured to the column address of decoding, to encourage the bit line of the cell array of selecting.
According to an embodiment consistent with the present invention, a kind of non-volatile memory semiconductor device comprises: the units chunk cell array, comprise a plurality of vertical multilevel-cell arrays, each have arrange be expert at and column direction on a plurality of unit cells; Column address decoder is configured to the column address of decoding, the bit line of one of cell array of selecting with excitation; Vertical address decoding unit, the vertical address of being configured to decode corresponding to one of cell array of selecting, and the output signal of described column address decoder is connected to the bit line of the cell array of selection; And row-address decoder, be configured to the decoded row address, to encourage the word line of the cell array of selecting.
Description of drawings
Fig. 1 is the diagram diagrammatic sketch of the units chunk cell array of non-volatile memory semiconductor device according to an embodiment of the invention.
Fig. 2 is the diagram diagrammatic sketch of the unit bank cell arrays of non-volatile memory semiconductor device according to an embodiment of the invention.
Fig. 3 is the diagram diagrammatic sketch of a plurality of groups of cell arrays of non-volatile memory semiconductor device according to an embodiment of the invention.
Fig. 4 is the diagram diagrammatic sketch of the address decoder unit of non-volatile memory semiconductor device according to an embodiment of the invention.
Fig. 5 is the diagram diagrammatic sketch of the address decoder unit of non-volatile memory semiconductor device according to an embodiment of the invention.
Fig. 6 to 8 is diagrammatic sketch of the address decoder unit of diagram Fig. 4.
Fig. 9 is the sectional view of the cell array of diagram Fig. 1.
Figure 10 and Figure 11 are the sectional view of the cell array of diagram Fig. 9.
Figure 12 is the sectional view of the units chunk cell array of diagram Fig. 1.
Figure 13 is the diagrammatic sketch of the cell array of diagram Fig. 9.
Embodiment
Describe the present invention in detail hereinafter with reference to accompanying drawing.
Fig. 1 is the diagram diagrammatic sketch of the units chunk cell array 100 of non-volatile memory semiconductor device according to an embodiment of the invention.
Units chunk cell array 100 can comprise a plurality of cell array CA1～CAn, wherein each cell array all has two-dimension plane structure, and described two-dimension plane structure comprises that the row address (X) that is arranged on the line direction (axle X) distinguishes and be arranged in column address (Y) district on the column direction (axle Y).
Units chunk cell array 100 has three-dimensional structure, and wherein cell array CA1～CAn can go up and place at vertical direction (axle Z).Units chunk cell array 100 can by vertical address Z come selected cell array CA1～CAn one of them.
In cell array CA1～CAn, row address X selects word line, and column address Y selects bit line.Vertical address Z selected cell array CA1～CAn one of them.
Fig. 2 is the diagram diagrammatic sketch of the unit bank cell arrays BCA of non-volatile memory semiconductor device according to an embodiment of the invention.
As above-mentioned, units chunk cell array 100 can comprise a plurality of cell array CA1～CAn, and described a plurality of cell arrays are placed in vertical direction.Unit bank cell arrays BCA can comprise a plurality of units chunk cell arrays 100.
In one embodiment, cell array CA1～CAn is described, and units chunk cell array 100 is described with a unit bank cell arrays BCA with a units chunk cell array 100.Yet in another embodiment, a unit bank cell arrays BCA can comprise a plurality of cell array CA1～CAn that is formed on one deck, and a plurality of unit bank cell arrays BCA can be placed vertically.
As shown in Figure 3, be expert at and column direction on a plurality of unit bank cell arrays BCA_1～BCA_m+m of arranging be configured to carry out read so that improve operating speed.
Though a plurality of unit bank cell arrays BCA are arranged on the row and column direction in this specific embodiments, a plurality of unit bank cell arrays BCA can be arranged in direction X according to the placement direction of cell array CA1～CAn, on Y and the Z.A unit bank cell arrays BCA, the units chunk cell array 100 that it comprises with given group form is configured to carry out read by unit bank cell arrays BCA.
Fig. 4 is the diagrammatic sketch of address decoder unit of the non-volatile memory semiconductor device of diagram one embodiment of the invention.
Address decoder unit can comprise row (X) address register 200, row-address decoder 210, vertical (Z) address register 220, vertical address demoder 230, row (Y) address register 240, column address decoder 250, group address register 260 and group address demoder 270.
But row address register 200 stored row address RADD.Row-address decoder 210 decodable codes are from the output signal of row address register 200.Vertical address register 220 can store vertical address VADD.Vertical address demoder 230 decodable codes are from the output signal of vertical address register 220.
Fig. 5 is the diagram diagrammatic sketch of the address decoder unit of non-volatile memory semiconductor device according to an embodiment of the invention.
In one embodiment, address decoder unit comprises address register 300, row address latch 310, row-address decoder 320, vertical address latch 330, vertical address demoder 340, column address latch 350, column address decoder 360, group address register 370 and group address demoder 380.
Address register 300 can store Input Address IADD.Row address latch 310 can latch the output signal from address register 300 to obtain row address.Row-address decoder 320 decodable codes are from the output signal of row address latch 310.Vertical address latch 330 can latch the output signal from address register 300 to obtain vertical address.Vertical address demoder 340 decodable codes are from the output signal of vertical address latch 330.
Column address latch 350 can latch the output signal from address register 300 to obtain column address.Column address decoder 360 decodable codes are from the output signal of column address latch 350.Group address register 370 can store group address BADD.Group address demoder 380 decodable codes are from the output signal of group address register 370.
Address register 300 can be handled the Input Address IADD by public pad I_PAD input.Address register 300 can come Input Address IADD is carried out time-division processing by time-sharing multiplex (timeshare multiplexing) system, so that output row address RADD, vertical address VADD and column address CADD.
That is row address RADD and vertical address VADD import in first timesharing, and column address CADD imports in second timesharing.Perhaps, row address RADD imports at first time slot, and vertical address VADD and column address CADD import at second time slot.Group address register 260 can be handled the group address BADD that fills up the B_PAD input from each separately.
Fig. 6 is the diagrammatic sketch of diagram about the address decoder unit of the 4th figure of row address.
Address decoder unit about row address can comprise vertical address demoder 230, row-address decoder 210 and row decoding unit 400.Row decoding unit 400 can comprise a plurality of switch SW 1～SWn of the word line WL that corresponds respectively among cell array CA1～CAn.
Switch SW 1～the SWn of row decoding unit 400 can be configured to optionally connect a line ROW and a word line WL, wherein this line ROW is by selecting from the output signal of row-address decoder 210, and this word line WL is one of them a word line of cell array CA1～CAn, and one of them is selected according to the output state of vertical address demoder 230 for described cell array CA1～CAn.
Fig. 7 is the diagrammatic sketch of diagram about the address decoder unit of the 4th figure of column address.
Address decoder unit about column address can comprise vertical address demoder 230, column address decoder 250 and row decoding unit 500.Row decoding unit 500 can comprise a plurality of switch SW 1～SWn of the bit line BL that corresponds respectively among cell array CA1～CAn.
Switch SW 1～the SWn of row decoding unit 500 can be configured to optionally connect an alignment COL and a bit line BL, wherein this alignment COL is by selecting from the output signal of column address decoder 250, and this bit line BL is one of them a bit line of cell array CA1～CAn, and one of them is selected according to the output of vertical address demoder 230 for described cell array CA1～CAn.
As shown in Figure 8, can carry out read to unit cell C, described unit cell C is in the zone that is intersected by the row decoding 400 selected word line WL of unit and the 500 selected bit line BL of unit that decoded by row.
Fig. 9 is the layout sectional view of the n layer cell array CAn of diagram Fig. 1.
A plurality of word line WL can be arranged on column direction and be parallel to a plurality of end word line BWL.A plurality of bit line BL can be arranged in perpendicular to word line WL.A plurality of unit cell C can be positioned at the zone of word line WL, end word line BWL and bit line BL intersection.
Figure 10 is the layout sectional view of n layer cell array CAn on the direction that is parallel to word line WL (A) of diagram Fig. 9.
N layer cell array CAn can be included in a plurality of insulation courses 12 on the end word line 10 and a plurality of P type channel regions 14 on insulation course 12.A plurality of ferroelectric layers 22 can form on P type channel region 14.A plurality of word lines 24 can be parallel to end word line 10 ground and be formed on the ferroelectric layer 22.As a result, a plurality of unit C are connected at the bottom of a word line WL_1 and one between the word line BWL_1.
Figure 11 is diagram n layer cell array CAn perpendicular to the layout sectional view on the direction (B) of word line WL.
In n layer cell array CAn, insulation course 12 can be formed on end word line BWL_1, BWL_2 and the BWL_3.The unsteady channel layer 20 that comprises P type drain region 16, P type channel region 14 and P type source area 18 is formed on the insulation course 12.P type drain region 16, P type channel region 14 and P type source area 18 can be connected in series.More specifically, P type source area 18 and P type drain region 16 are connected the both sides of P type channel region 14.
P type drain region 16 can be used as the source area of adjacent cells, and P type source area 18 can be used as the drain region of adjacent cells.That is p type island region 16 can be used as public drain electrode district and the common source region adjacent to two unit of p type island region 16.
The channel region 14 of drain region 16, source area 12 and unsteady channel layer 20 can form the P type.The semiconductor of unsteady channel layer 20 is selected from the group that is made up of carbon nano-tube, silicon, germanium and organic semiconductor.
Ferroelectric layer 22 can be formed on the channel region 14 of the channel layer 20 that floats, and word line WL_1, WL_2 and WL_3 are formed on the ferroelectric layer 22.End word line 10 is optionally driven by identical row-address decoder (not shown) with word line 24.
Can utilize the channel resistance of the channel layer 20 that floats to come the read/write data, this polarized state according to ferroelectric layer 22 is distinguished.That is for channel region 14, when the polar inductive of ferroelectric layer 22 just went out (+) electric charge, storage unit C became and is in high resistance state, so raceway groove is by " shutoff ".For channel region 14, when the polar inductive of ferroelectric layer 22 went out negative (-) electric charge, storage unit C became and is in low resistance state, so raceway groove is switched " on ".
Figure 12 is the sectional view of the units chunk cell array 100 of diagram Fig. 1.
As shown in figure 11, block unit cell array 100 can comprise a plurality of multilayer unit cell array CA1～CAn, and is separated by unit insulation course 26.
Channel layer 20 can comprise P type drain region 16, P type channel region 14 and P type source area 18 although float in an embodiment consistent with the present invention, but the channel layer 20 that floats also can comprise N type drain region 16, N type channel region 14 and N type source area 12, shown in the 13rd figure.
In one embodiment, as the read of the high data of non-volatile memory semiconductor device as described in explaining to get off.
When writing data " 1 ", ground voltage＜GND〉can be applied in end word line 10, and negative voltage＜-V〉can be applied in word line 24.Drain region 16 and source area 18 can be configured to be in ground voltage＜GND〉state.
Voltage by the capacitor between ferroelectric layer 22 and the insulation course 12 distributes, and voltage can be put between the P type channel region 14 of ferroelectric layer 22 and unsteady channel layer 20.As a result, can in channel region 14, induce positive charge according to the polarity of ferroelectric layer 22, so storage unit C can have low resistance state.Therefore, be written among all storage unit C writing mode data " 1 ".
When reading of data " 1 ", ground voltage＜GND〉or have on the occasion of read voltage＜+Vrd can be applied in end word line 10.Ground voltage＜GND〉can be applied in word line 17.By apply from end word line 10 read voltage＜+Vrd, can form depletion layer in the bottom of channel region 14.
Because can induce positive charge at the top of channel region 14, depletion layer can not be formed at the top of channel region 14.Therefore, channel region 14 is connected, with from source area 18 to the drain region 16 ground conduction currents.As a result, can read the data " 1 " that store among the storage unit C at read mode.Even when producing small electric pressure reduction in drain region 16 and source area 18, channel region 14 also can be connected, thereby flows through a large amount of electric currents.
In one embodiment, as the read of the low data of non-volatile memory semiconductor device as described in explaining to get off.
When writing data " 0 ", negative voltage＜-V〉can be applied in end word line 10, and ground voltage＜GND can be applied in word line 24.Negative voltage＜-V〉can be applied in drain region 16 and source area 18.
The positive voltage that applies from word line 24＜+V and the negative voltage of channel region 14＜-V between produce high voltage differential.As a result, according to the polarity of ferroelectric layer 22 and in channel region 14, induce negative charge, make storage unit C can have high resistance state.
When reading of data " 0 ", ground voltage＜GND〉or have on the occasion of read voltage＜+Vrd can be applied to end word line 10.Ground voltage＜GND〉can be applied to word line 24.
By apply from end word line 10 read voltage＜+Vrd, form depletion layer in the bottom of channel region 14.Top at channel region 14 induces negative charge, so depletion layer is formed at the top of channel region 14.The depletion layer that the raceway groove of channel region 14 is formed in the channel region 14 turn-offs, and makes that the current path between source area 18 and the drain region 16 disconnects.
Even when producing small electric pressure reduction between drain region 16 and source area 18, channel region 14 also turn-offs, thereby flows through a spot of electric current.Therefore, can read the data " 0 " that store among the storage unit C at read mode.
Because word line 24 and end word line 10 need not ferroelectric layer 22 is applied voltage stress read mode ground connection, so the data retention characteristic of storage unit C improves.
As above-mentioned, in the Nonvolatile ferroelectric memory spare according to one embodiment of the invention, non-destructive reads that (Non-Destructive Read Out, NDRO) system can prevent that cell data is destroyed at read mode.Described Nonvolatile ferroelectric memory spare has improved the reliability of storage unit and the read operation speed in the low voltage operating of nano level ferroelectric cell.A plurality of ferroelectric unit cell arrayed be expert at and column direction on.In addition, ferroelectric unit cell array is placed vertically, and improving the integration capability of storage unit, thereby reduces the overall dimensions of Nonvolatile ferroelectric memory spare.Vertical units chunk cell array of placing is divided into one group, and is configured to carry out read, thereby improves the operating speed of storage unit.Vertically one of (Z) address decoder selection unit module unit array is with driver element array effectively, thereby improves the operating speed of unit.
The foregoing description consistent with the present invention described for the purpose of illustration.This is not to want exhaustive the present invention or the present invention is limited to disclosed precise forms.Should understand can be according to above enlightenment or according to practice of the present invention being made amendment and changing.Therefore, selected and describe described embodiment so that explain principle of the present invention and practical application thereof, thus make those skilled in the art utilize the present invention with various embodiment and with the various modifications that are applicable to special-purpose of being conceived.
Label declaration in the accompanying drawing in each element
10 end word lines
12 insulating barriers
14 channel regions
16 drain regions
18 source areas
20 unsteady channel layers
22 ferroelectric layers
24 word lines
26 unit insulating barriers
100 units chunk unit battle array row
200 row (X) address registers
210 row (X) address decoders
220 vertical (Z) address registers
230 vertical (Z) address decoders
240 row (Y) address registers
250 row (Y) address decoders
260 group address registers
270 group address demoders
300 address registers
310 row (X) address latch
320 row (X) address decoders
330 vertical (Z) address latch
340 vertical (Z) address decoders
350 row (Y) address latch
360 row (Y) address decoders
370 group address registers
380 group address demoders
400 row decoding units
500 sensing amplifiers decoding unit
Claims (52)
1. non-volatile memory semiconductor device comprises:
A plurality of unit bank cell arrays, described unit bank cell arrays have a plurality of units chunk cell arrays, and described units chunk cell array comprises a plurality of cell array layer, and described cell array layer has a plurality of unit cells that are arranged on the row and column direction,
Wherein, described units chunk cell array is arranged in direction X based on the placement direction of its each cell array layer, and on Y and the Z, and described unit cell configuration becomes to carry out respectively read.
2. according to the non-volatile memory semiconductor device of claim 1, wherein, during the read/write process, described units chunk cell array is selected one of described cell array layer by vertical address.
3. according to the non-volatile memory semiconductor device of claim 1, wherein, described unit cell comprises the Nonvolatile ferroelectric capacitor.
4. according to the non-volatile memory semiconductor device of claim 1, wherein, described unit cell comprises:
End word line;
Insulation course is formed on the word line of the described end;
Unsteady channel layer is formed on the described insulation course, and remains on quick condition;
Ferroelectric layer is formed at data storing on described unsteady channel layer wherein; And
Word line is formed on the described ferroelectric layer with being parallel to word line of the described end,
Wherein,, induce variable resistor according to the polarization state of described ferroelectric layer for the channel region of described unsteady channel layer, thus the read/write data.
5. according to the non-volatile memory semiconductor device of claim 4, wherein, described unsteady channel layer comprise carbon nano-tube, silicon, germanium and organic semiconductor one of them.
6. according to the non-volatile memory semiconductor device of claim 4, wherein, described unsteady channel layer comprises: described channel region is formed on the described insulation course and remains on quick condition; And drain region and source area, be connected the both sides of described channel region.
7. according to the non-volatile memory semiconductor device of claim 6, wherein, described channel region, described drain region and described source area are the P types.
8. according to the non-volatile memory semiconductor device of claim 6, wherein, described channel region, described drain region and described source area are the N types.
9. according to the non-volatile memory semiconductor device of claim 1, wherein, described cell array layer comprises:
Word line of a plurality of ends;
Insulation course is formed on the word line of described a plurality of ends;
Unsteady channel layer is formed on the described insulation course, and comprises a plurality of drain electrodes and the source area that alternately is connected in series to described a plurality of channel regions;
Ferroelectric layer is formed on the described unsteady channel layer; And
A plurality of word lines are formed on the described ferroelectric layer, so that be connected to word line of described a plurality of ends,
Wherein,, induce different resistance according to the polarization state of described ferroelectric layer for the channel region of described unsteady channel layer, thus the read/write data.
10. according to the non-volatile memory semiconductor device of claim 9, further comprise the unit insulation course, described unit insulation course is formed between the described cell array layer, so that described cell array layer is separated from each other.
11. according to the non-volatile memory semiconductor device of claim 9, wherein, described channel region, described drain region and described source area are the P types.
12. according to the non-volatile memory semiconductor device of claim 9, wherein, described channel region, described drain region and described source area are the N types.
13. a non-volatile memory semiconductor device comprises:
Unit bank cell arrays comprises at least one units chunk cell array, and described units chunk cell array further comprises:
The first module array comprises a plurality of first unit cells, and described first unit cell is arranged on the row and column direction; And
At least one second cell array comprises a plurality of second unit cells, and described second unit cell is arranged on the row and column direction, and described second cell array is arranged on the vertical direction with respect to described first module array,
Wherein, described units chunk cell array comprises one that selects from described first module array and described second cell array according to vertical address.
14. according to the non-volatile memory semiconductor device of claim 13, wherein, described units chunk cell array is arranged in direction X, on Y and the Z, so that carry out read respectively.
15. according to the non-volatile memory semiconductor device of claim 13, wherein, described unit cell comprises the Nonvolatile ferroelectric capacitor.
16. according to the non-volatile memory semiconductor device of claim 13, wherein, described unit cell comprises:
End word line;
Insulation course is formed on the word line of the described end;
Unsteady channel layer is formed on the described insulation course, and remains on quick condition;
Ferroelectric layer is formed at data storing on described unsteady channel layer wherein; And
Word line is formed on the described ferroelectric layer with being parallel to word line of the described end,
Wherein,, induce different resistance according to the polarization state of described ferroelectric layer for the channel region of described unsteady channel layer, thus the read/write data.
17. according to the non-volatile memory semiconductor device of claim 16, wherein, described unsteady channel layer comprise carbon nano-tube, silicon, germanium and organic semiconductor one of them.
18. according to the non-volatile memory semiconductor device of claim 16, wherein, described unsteady channel layer comprises: channel region is formed on the described insulation course and remains on quick condition; And drain region and source area, be connected the both sides of described channel region.
19. according to the non-volatile memory semiconductor device of claim 18, wherein, described channel region, described drain region and described source area are the P types.
20. according to the non-volatile memory semiconductor device of claim 18, wherein, described channel region, described drain region and described source area are the N types.
21. according to the non-volatile memory semiconductor device of claim 13, wherein, described first module array and described second cell array comprise:
Word line of a plurality of ends;
Insulation course is formed on the word line of described a plurality of ends;
Unsteady channel layer is formed on the described insulation course, and comprises a plurality of drain electrodes and the source area that alternately is connected in series to described a plurality of channel regions;
Ferroelectric layer is formed on the described unsteady channel layer; And
A plurality of word lines are formed on the described ferroelectric layer, so that be connected to word line of described a plurality of ends,
Wherein,, induce different resistance according to the polarization state of described ferroelectric layer for the channel region of described unsteady channel layer, thus the read/write data.
22. non-volatile memory semiconductor device according to claim 21, further comprise the unit insulation course, described unit insulation course is formed between described first module array and described second cell array, so that described first and second cell arrays are separated from each other.
23. according to the non-volatile memory semiconductor device of claim 21, wherein, described a plurality of channel regions, described a plurality of drain regions and described plurality of source regions are the P types.
24. according to the non-volatile memory semiconductor device of claim 21, wherein, described a plurality of channel regions, described a plurality of drain regions and described plurality of source regions are the N types.
25. a non-volatile memory semiconductor device comprises:
The units chunk cell array comprises a plurality of cell array layer on the top that vertically is positioned over each other, and described cell array layer has a plurality of unit cells that are arranged on the row and column direction;
Row-address decoder is configured to the decoded row address, the word line of one of described cell array of selecting with excitation;
Vertical address decoding unit, the vertical address of one of described cell array of being configured to decode corresponding to described selection, and the output signal of described row-address decoder is connected to the word line of the cell array of described selection; And
Column address decoder is configured to the column address of decoding, with the bit line of one of cell array of encouraging described selection.
26. according to the non-volatile memory semiconductor device of claim 25, wherein, a plurality of unit bank cell arrays comprise a plurality of units chunk cell arrays, described a plurality of units chunk cell arrays are arranged in direction X, on Y and the Z, so that carry out read respectively.
27. according to the non-volatile memory semiconductor device of claim 25, wherein, described vertical address decoding unit comprises:
The vertical address demoder, described vertical address and select one of described a plurality of cell arrays is configured to decode; And
Row decoding unit is configured to the word line of the cell array of described selection optionally is connected to line, and described line provides the output signal from described row-address decoder.
28. non-volatile memory semiconductor device according to claim 27, wherein, described row decoding unit comprises a plurality of switches, and described a plurality of switches are connected between described line and the described word line, and each is configured in response to from described vertical address output signal of decoder and switch.
29. according to the non-volatile memory semiconductor device of claim 27, wherein, described vertical address demoder further comprises the vertical address register, described vertical address register configuration becomes described vertical address is outputed to described vertical address demoder.
30. the non-volatile memory semiconductor device according to claim 25 further comprises:
Row address register is configured to described row address is outputed to described row-address decoder; And
Column address register is configured to described column address is outputed to described column address decoder.
31. according to the non-volatile memory semiconductor device of claim 30, wherein, described row address, described column address and described vertical address are from the input respectively of each pad.
32. the non-volatile memory semiconductor device according to claim 26 further comprises:
The group address register is configured to export group address; And
The group address demoder, the output signal from described group address register of being configured to decode is to select one of described a plurality of unit bank cell arrays.
33. according to the non-volatile memory semiconductor device of claim 32, wherein, described group address is from an independent pad input.
34. the non-volatile memory semiconductor device according to claim 25 further comprises:
Address register is configured to control Input Address, to export described row address, described column address and described vertical address;
Row address latch is configured to latch described row address;
Column address latch is configured to latch described column address; And
The vertical address latch is configured to latch described vertical address.
35. according to the non-volatile memory semiconductor device of claim 34, wherein, described Input Address is imported by a public pad.
36. according to the non-volatile memory semiconductor device of claim 34, wherein, described address register is configured to optionally export one of described row address, described column address and described vertical address by the time-sharing multiplex system.
37. according to the non-volatile memory semiconductor device of claim 36, wherein, described address register is configured to described row address and described vertical address, and then described column address is carried out time-division processing.
38. according to the non-volatile memory semiconductor device of claim 36, wherein, described address register is configured to described row address, and then described vertical address and described column address is carried out time-division processing.
39. a non-volatile memory semiconductor device comprises:
The units chunk cell array comprises placement a plurality of cell array layer in vertical direction, and each has a plurality of unit cells that are arranged on the row and column direction;
Column address decoder is configured to the column address of decoding, the bit line of one of described cell array layer of selecting with excitation;
Vertical address decoding unit, the vertical address of the cell array layer of the described selection that is configured to decode, and the output signal of described column address decoder is connected to the bit line of the cell array layer of described selection; And
Row-address decoder is configured to the decoded row address, with the word line of the cell array layer that encourages described selection.
40. according to the non-volatile memory semiconductor device of claim 39, wherein, described units chunk cell array is based on the placement direction of described cell array layer and be arranged in direction X, on Y and the Z, so that carry out read respectively.
41. according to the non-volatile memory semiconductor device of claim 39, wherein, described vertical address decoding unit comprises:
The vertical address demoder, described vertical address and select one of described a plurality of cell array layer is configured to decode; And
Row decodings unit is configured to the bit line of the cell array layer of described selection optionally is connected to alignment, and described alignment is the output signal from described column address decoder.
42. non-volatile memory semiconductor device according to claim 41, wherein, described row decoding unit comprises a plurality of switches, and described a plurality of switches are connected between described alignment and the described bit line, and described a plurality of switches are configured in response to from described vertical address output signal of decoder and switch.
43. according to the non-volatile memory semiconductor device of claim 41, wherein, described vertical address demoder further comprises the vertical address register, described vertical address register configuration becomes described vertical address is outputed to described vertical address demoder.
44. the non-volatile memory semiconductor device according to claim 39 further comprises:
Row address register is configured to described row address is outputed to described row-address decoder; And
Column address register is configured to described column address is outputed to described column address decoder.
45. according to the non-volatile memory semiconductor device of claim 44, wherein, described row address, described column address and described vertical address are from the input respectively of each pad.
46. the non-volatile memory semiconductor device according to claim 39 further comprises:
The group address register is configured to export group address; And
The group address demoder, the output signal from described group address register of being configured to decode is to select one of described a plurality of unit bank cell arrays.
47. according to the non-volatile memory semiconductor device of claim 46, wherein, described group address is from independent pad input.
48. the non-volatile memory semiconductor device according to claim 39 further comprises:
Address register is configured to control Input Address, to export described row address, described column address and described vertical address;
Row address latch is configured to latch described row address;
Column address latch is configured to latch described column address; And
The vertical address latch is configured to latch described vertical address.
49. according to the non-volatile memory semiconductor device of claim 48, wherein, described Input Address is imported by a public pad.
50. according to the non-volatile memory semiconductor device of claim 48, wherein, described address register is configured to optionally export one of described row address, described column address and described vertical address by the time-sharing multiplex system.
51. according to the non-volatile memory semiconductor device of claim 50, wherein, described address register is configured to described row address and described vertical address, and then described column address is carried out time-division processing.
52. according to the non-volatile memory semiconductor device of claim 50, wherein, described address register is configured to described row address, and then described vertical address and described column address is advanced the processing of row time-sharing multiplex.
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| KR1020050135236 | 2005-12-30 | ||
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| KR1020050135236A KR100802248B1 (en) | 2005-12-30 | 2005-12-30 | Non-volatile semiconductor memory device |
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| CN1992077A true CN1992077A (en) | 2007-07-04 |
| CN100573708C CN100573708C (en) | 2009-12-23 |
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Cited By (3)
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|---|---|---|---|---|
| CN110265292A (en) * | 2019-04-26 | 2019-09-20 | 芯盟科技有限公司 | Three-dimensional storage and production method |
| CN111354732A (en) * | 2018-09-14 | 2020-06-30 | 长江存储科技有限责任公司 | Three-dimensional memory device and method for forming the same |
| US10776016B2 (en) | 2016-04-27 | 2020-09-15 | Micron Technology, Inc. | Data caching for ferroelectric memory |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR101448169B1 (en) | 2008-01-02 | 2014-10-13 | 삼성전자주식회사 | Tree dimentional memory device of multi-pln achitechure |
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| KR19990084635A (en) * | 1998-05-08 | 1999-12-06 | 정선종 | Ferroelectric Transistor Memory Devices |
| KR20000014361A (en) * | 1998-08-20 | 2000-03-15 | 정선종 | FERROELECTRIC TRANSISTOR USING Ba-Sr-Nb-O AND METHOD THEREOF |
| KR20000025935A (en) * | 1998-10-15 | 2000-05-06 | 정선종 | Ferroelectric field effect transistor and method for fabricating the same |
| KR20000059830A (en) * | 1999-03-09 | 2000-10-05 | 김영환 | A fuse array in a semiconductor device and a fabricating method thereof |
| WO2002025667A2 (en) * | 2000-09-25 | 2002-03-28 | Symetrix Corporation | Ferroelectric memory and method of operating same |
| JP3591497B2 (en) | 2001-08-16 | 2004-11-17 | ソニー株式会社 | Ferroelectric nonvolatile semiconductor memory |
| US6643159B2 (en) | 2002-04-02 | 2003-11-04 | Hewlett-Packard Development Company, L.P. | Cubic memory array |
| US6822903B2 (en) | 2003-03-31 | 2004-11-23 | Matrix Semiconductor, Inc. | Apparatus and method for disturb-free programming of passive element memory cells |
| JP2005136071A (en) | 2003-10-29 | 2005-05-26 | Seiko Epson Corp | Cross point type ferroelectric memory |
| KR20040079884A (en) * | 2004-08-27 | 2004-09-16 | 한국기초과학지원연구원 | Perovskite structure fatigue-free ferroelectric transistor with gallium nitride substrate and method for fabricating the same |
| KR100684875B1 (en) * | 2004-11-24 | 2007-02-20 | 삼성전자주식회사 | Semiconductor Device And Method Of Fabricating The Same |
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
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| US10776016B2 (en) | 2016-04-27 | 2020-09-15 | Micron Technology, Inc. | Data caching for ferroelectric memory |
| US11520485B2 (en) | 2016-04-27 | 2022-12-06 | Micron Technology, Inc. | Data caching for ferroelectric memory |
| CN111354732A (en) * | 2018-09-14 | 2020-06-30 | 长江存储科技有限责任公司 | Three-dimensional memory device and method for forming the same |
| CN111354732B (en) * | 2018-09-14 | 2021-04-27 | 长江存储科技有限责任公司 | Three-dimensional memory device and method for forming the same |
| US11037946B2 (en) | 2018-09-14 | 2021-06-15 | Yangtze Memory Technologies Co., Ltd. | Three-dimensional memory devices and methods for forming the same |
| CN110265292A (en) * | 2019-04-26 | 2019-09-20 | 芯盟科技有限公司 | Three-dimensional storage and production method |
| CN110265292B (en) * | 2019-04-26 | 2021-07-27 | 芯盟科技有限公司 | Three-dimensional memory and manufacturing method |
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| CN100573708C (en) | 2009-12-23 |
| KR20070071610A (en) | 2007-07-04 |
| KR100802248B1 (en) | 2008-02-11 |
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