[background technology]
Along with development of electronic technology, electric energy metrical realizes becoming the direction of electric energy meter development with chip.If all realize that with analog circuit precision can be very not high when using chip to realize, for overcoming this shortcoming of analog circuit, now typical electric energy computation chip uses ADC (analog to digital converter) that analog signal is quantified as digital signal, in digital circuit, realize operations such as filtering and power calculation, can obtain higher precision.
The result of electric energy metrical generally need become power transfer pulse signal output, promotes external mechanical type rotor, and input signal (power) is big more, and the frequency of the pulse signal of output is high more, and this just needs a numerical frequency converting unit.
Traditional numerical frequency converting unit adds up to input signal, the carry signal that adds up is exported as frequency, disclose in the U.S. Pat 5760617, its functional-block diagram as shown in Figure 1, this technical scheme belongs to a kind of particular design, if the amplitude peak of the peak frequency of output pulse, input data, the clock frequency of accumulator change, originally She Ji carry signal just can not be re-used as frequency signal output, so flexibility is very poor.
The peak frequency of output pulse signal is that requirement is configurable in some cases in the numerical frequency converting unit, in this case, even change circuit structure without carry signal, use new method to produce frequency signal, still can not solve the configurable problem of peak frequency of same chip output pulse signal; Simultaneously, the amplitude peak and the working clock frequency of input data may change equally, if the numerical frequency converting unit can be made able to programme can overcoming the above problems.
Chinese patent Granted publication CN1169291C, September 29 2004 Granted publication day, disclosed a kind of method and circuit that is used for product to pulses switch, its schematic block circuit diagram as shown in Figure 2, this technical scheme does not re-use carry signal and exports as frequency, but introduces a constant in circuit, can adapt to different output frequencies, wherein the circuit before register 1 input is the power calculation unit in the ammeter, and the circuit after register 1 output is the numerical frequency converting unit.The data rate liter that register 1 is partly exported power calculation samples on the data rate of data pulse converting unit work, obviously the numerical frequency converting unit has following shortcoming in this technical scheme: one, the course of work of numerical frequency converting unit need only be used for electric energy metrical by means of other circuit; Its two, carry out zeroth order with register 1 and keep directly data rate conversion on the input rate of numerical frequency converting unit, image frequency inevitably has influence on the conversion accuracy of system; They are three years old, when requiring output frequency to change, realize by changing constant value, but have a problem, the numerical frequency converting unit was exactly that the input signal that amplitude varies in size is transformed into different frequency output originally, if constant value also changes, it is complicated that the situation that just makes becomes, probably have influence on algorithm validity, also become complicated even guarantee the correct control of algorithm, and this technical scheme does not provide the method for configuration constant value.In addition, this technical scheme requires the working clock frequency of numerical frequency converting unit greater than input data rate, requires the input data bit width identical with the bit wide and the constant bit wide of accumulator, and these restrictions have all restricted the range of application of this method.
[summary of the invention]
Technical problem to be solved by this invention is: a kind of digital frequency switching method and circuit are provided, be applicable to the amplitude peak of different input data, the peak frequency or the working clock frequency of output pulse signal, can increase application flexibility and reduce the realization cost.
For solving the problems of the technologies described above, the technical solution adopted in the present invention is: a kind of digital frequency switching method may further comprise the steps:
1. the maximum amplitude that calculated threshold, this threshold value equal to import data multiply by the peak frequency of working clock frequency divided by output pulse signal;
2. will import data and add up, output accumulated value sum;
3. deduct threshold value with accumulated value sum, when difference is positive number or zero, described difference is added up as an initial value that adds up and input data next time; When difference is negative, accumulated value sum is added up as an initial value that adds up and input data next time;
4. the difference of accumulated value sum and threshold value is deciphered and produced pulse output.
Another technical scheme of the present invention is: a kind of numerical frequency change-over circuit comprises:
Accumulator, it comprises adder and register, and this adder will be imported data and content of registers addition, and wherein, this numerical frequency change-over circuit also comprises:
Threshold register is used for the access threshold value;
Subtracter, described adder output deducts described threshold value through this subtracter, the output difference;
Selector, select described adder or subtracter wherein an operation result import described register;
Decoder is used for described difference is deciphered the generation pulse signal.
The invention has the beneficial effects as follows: because the present invention improves traditional data frequency conversion method and circuit, introduce threshold parameter, by described accumulation result and threshold value are subtracted each other the generation pulse signal, because threshold value is the accumulated value of maximum amplitude in an output pulse period of input data, the amplitude peak of different input data, working clock frequency, the peak frequency of output pulse signal can corresponding different threshold value, thereby the present invention is applicable to the amplitude peak of different input data, the peak frequency of output pulse signal or working clock frequency, solved the configurable problem of above-mentioned parameter effectively, and then increased application flexibility, and reduced the cost of realizing.
[embodiment]
The invention will be further described below in conjunction with accompanying drawing.
Digital frequency switching method of the present invention may further comprise the steps:
1. the maximum amplitude that calculated threshold, this threshold value equal to import data multiply by the peak frequency of working clock frequency divided by output pulse signal;
2. will import data and add up, output accumulated value sum;
3. deduct threshold value with accumulated value sum, when difference is positive number or zero, described difference is added up as an initial value that adds up and input data next time; When difference is negative, accumulated value sum is added up as an initial value that adds up and input data next time;
4. the difference of accumulated value sum and threshold value is deciphered and produced pulse output.
The peak frequency of the maximum amplitude of these input data, working clock frequency and output pulse signal can be a changing value.
As shown in Figure 3, numerical frequency change-over circuit of the present invention comprises:
Accumulator, it comprises adder and register, this adder will be imported data and content of registers addition, it is characterized in that: this numerical frequency change-over circuit also comprises:
Threshold register is used for the access threshold value;
Subtracter, described adder output deducts described threshold value through this subtracter, the output difference;
Selector, select described adder or subtracter wherein an operation result import described register;
Decoder is used for described difference is deciphered the generation pulse signal.
Also be connected with decoder between this selector and the described subtracter, this sign bit detects trigger module and is used for providing a control signal to described selector.
The working clock frequency of this register is identical with the data rate of input data.
The figure place of the figure place of this adder and described input data, the figure place of threshold register not simultaneously, as long as left-justify during addition, the figure place of this adder is identical with the figure place of register.
During work, the user can calculate threshold value according to the peak frequency of the amplitude peak of importing data, working clock frequency, output pulse signal, is written in the threshold register, and the present invention just can export the frequency signal that satisfies the demands.
Threshold value calculation method is as follows: supposition Ts is the clock cycle, and P is the amplitude of input data, P
MaxBe the maximum amplitude of input data, n is the clock periodicity that comprises an output pulse period, n
MaxBe the output pulse frequency clock periodicity that pulse period comprises when maximum, f
ClkBe clock frequency, f
MaxPeak frequency for output pulse signal.According to the proportional relation between the amplitude of the frequency of exporting pulse and input data as can be known, the amplitude of input data is big more, and the clock periodicity that reaches threshold value of adding up is few more, thereby the cycle of the output pulse that obtains is short more, therefore the frequency of exporting pulse is high more, and therefore following quantitative relation is arranged
Thereby
N wherein
MaxNeed not be integer.
Adder will import data and content of registers is carried out addition output accumulated value sum, this accumulated value sum deducts threshold value through a subtracter, if both differences are more than or equal to 0, then the decoder output signal 1, and the difference between selector selection accumulated value sum and threshold value is as the input of register; Otherwise decoder output signal 0 adopts the input of accumulated value sum as register, the initial value that the output of this register will add up as next round.
Fig. 4 is the working timing figure of digital frequency switching method of the present invention and circuit one embodiment, the input data are 2 among the figure, threshold value is 11, in first clock cycle, the register register value is 6, and accumulated value sum is 8, obviously the difference of accumulated value sum and threshold value 11 is less than 0, decoder output signal 0, the input value of register are accumulated value sum (=8), the initial value that this accumulated value sum (=8) will add up as next round; In second clock cycle, register register value and input data addition, output accumulated value sum is 10, with the difference of threshold value less than 0, decoder output still is signal 0, the register input value is accumulated value sum (=10); In the 3rd clock cycle, the register register value is 12 with the accumulated value sum of input data addition output, with the difference of threshold value greater than 0, decoder output signal 1, selector is selected the input of the difference 1 of accumulated value sum and threshold value as register, the register value of register will carry out next round as an initial value of adder in the next clock cycle and add up, by that analogy.
Decoder all exported 1 in the difference of accumulated value sum and threshold value more than or equal to 0 o'clock, and in the case, the initial value that the difference of accumulated value sum and threshold value will add up as next round.Under the optimal situation, accumulated value sum just equals threshold value, and this time difference value is 0, and the register value of register is 0, and in this case, the frequency signal of output does not have phase jitter.Simultaneously, in the application with the difference between accumulated value sum and threshold value as the initial value that adds up next time, in fact constitute single order sigma-delta modulation, though output has phase jitter, on average, the average of output frequency is accurately.
Adder is identical with the bit wide of register, but does not require identically with the bit wide of importing data, and both bit wide difference under a lot of situation is as long as import left-justify when the addition with the output of register and data.The bit wide of adder does not need identical with the bit wide of threshold register yet.
The present invention can be achieved as follows application:
The amplitude maximum of input data has difference in the same chip.For example chip has the two-way input, one the tunnel is that electric current, a tunnel is a voltage, but both input maximum differences, all to export both effective values with impulse form, just the present invention can be used,, these two numerical frequency converting units time division multiplexing can also be carried out in the realization as long as change threshold value, the different moment are imported different threshold values and get final product, and this implementation method greatly reduces cost.
The peak frequency of the configurable different output pulse of same chip user is to adapt to different application.At this moment, the user should calculate threshold value according to formula (1) when using chip, and the user becomes fixed-point number to write threshold register threshold transition by chip interface then, and the present invention just can export the frequency signal of expectation.This implementation method has improved the flexibility of chip greatly.
In different projects, also might use different system clocks.For example the clock that uses among the project A is system works clock 2MHz, and the input system clock in the item B is 3.4MHz, obviously in order to make the numerical frequency converting unit in the B project still be operated in 2MHz to realize reusing of module, will carrying out frequency division to system clock so, to make the input clock of numerical frequency converting unit be 2MHz, obviously this is pretty troublesome, if but the numerical frequency converting unit just is operated on the system clock 3.4MHz, reconfigure threshold value according to formula (1) and get final product, greatly reduced the design difficulty of clock generating module.
Because the present invention improves traditional data frequency conversion method and circuit, introduce threshold parameter, by described accumulation result and threshold value are subtracted each other the generation pulse signal, because threshold value is the accumulated value of maximum amplitude in an output pulse period of input data, the amplitude peak of different input data, working clock frequency, the peak frequency of output pulse signal can corresponding different threshold value, thereby the present invention is applicable to the amplitude peak of different input data, the peak frequency of output pulse signal or working clock frequency, solved the configurable problem of above-mentioned parameter effectively, and then increased application flexibility, and reduced the cost of realizing.