CN1984042B - Method and device for managing buffer address - Google Patents
Method and device for managing buffer address Download PDFInfo
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- CN1984042B CN1984042B CN2006100608775A CN200610060877A CN1984042B CN 1984042 B CN1984042 B CN 1984042B CN 2006100608775 A CN2006100608775 A CN 2006100608775A CN 200610060877 A CN200610060877 A CN 200610060877A CN 1984042 B CN1984042 B CN 1984042B
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Abstract
The invention is applicable to communication field, providing a managerial method and device for cache addresses, the method comprises: record the distribution state of cache addresses; check the distribution state of cache addresses, distribute or recover the said cache addresses according to check result of distribution state of cache addresses. The invention check distribution state while distribute or recover the cache addresses, thereby consume less resources cache resource, avoid the repeated distribution of cache address and repeated recovery mistakes led to the switched network failure. Meanwhile, even some SRAM bit of FAFIFO mistake or fails and internal circuit error make wrong cache addresses, which should not affect its normal operation.
Description
Technical field
The invention belongs to the communications field, relate in particular to a kind of management method and management devices of buffer address.
Background technology
Switching network (Switch Fabric) is the nucleus module of router, is responsible for finishing between a plurality of ports the exchange of bag or cell, will arrive the bag of input port or cell switching to corresponding output port.Because most of switching network inside is not based on connection, therefore the situation of an output port of a plurality of input ports competitions can appear, and cause cell to block or lose.Therefore one of basic function of switching network is exactly to handle the output port conflict.Buffer memory and back-pressure are two kinds of effective means that solve port collision.According to the structure difference, buffer memory mainly comprises input-buffer, output buffers and three kinds of forms of middle shared buffer memory.Middle shared buffer memory technology can guarantee higher percent of pass, buffer memory utilance and service quality (Quality Of Service, QOS) characteristic support.
In middle shared buffer memory technology, buffer address first in first out (Free Address First In First Out, FAFIFO) management free buffer address, free buffer address be stored in FAFIFO static RAM (Static Random Access Memory, SRAM) in.Each clauses and subclauses (Entry) among the SRAM are represented a free buffer address, and each buffer address corresponding cache capacity is a cell.Suppose that buffer memory capacity is 4k, then the width of each buffer address is 12bit, and an Entry is as shown in the table among the SRAM:
| Field | Description |
| Fa[11:0] | Free address: free buffer address |
Wherein, Fa is the free buffer address in the buffer memory, for example, the Fa=0 of buffer address 0, the Fa=1 of buffer address 1, and the like, the Fa=4095 of buffer address 4095.
FAFIFO carries out initialization by internal logic, and after initialization was finished, SRAM was in full state, and the read-write pointer all points to buffer address 0.Distributing a free buffer address is exactly that FAFIFO reads an Entry from SRAM, and reclaiming a free buffer address is exactly that FAFIFO writes an Entry to SRAM.When cell was joined the team, FAFIFO distributed a free buffer address, and the cell of will joining the team stores this corresponding cache space, free buffer address into, the line output of going forward side by side queuing.After cell went out team, FAFIFO reclaimed this buffer address.
In the distribution and removal process of above-mentioned buffer address; owing to there is not protection mechanism; when some bit of the corresponding SRAM of a certain Entry lost efficacy or is wrong; FAFIFO may distribute identical address for two different cells; the cell that deposits buffer memory after causing in can cover last cell, also has two identical addresses in the buffer address of output work queue at this moment, when the scheduling cell goes out buffer memory; the cell that deposits in after will reading for twice from same address causes the cell output error.Corresponding FAFIFO has also carried out the operation of twice same buffer address of recovery, cause buffer address to repeat to reclaim, when the next round address assignment, there is identical address assignment to go out again like this, can when reclaiming the output cell error take place equally again and buffer address repeats to reclaim mistake, cause switching network to lose efficacy thereby go round and begin again.In addition, the internal circuit mistake of system (for example noise, power supply ripple or accidental hardware error) also can cause same cell is repeated repeatedly to read from buffer memory, so that same buffer address repeats to reclaim.Therefore,, can't recover automatically, and wrong can constantly take place to restart, influence the normal operation of system until system reset in case buffer address makes a mistake in the prior art.
Summary of the invention
The object of the present invention is to provide a kind of management method of buffer address, some bit that is intended to solve the SRAM that works as FAFIFO in the prior art lost efficacy or mistake, and the internal circuit mistake causes buffer address duplicate allocation, buffer address to repeat to reclaim, and influences the problem of the normal operation of system.
Another object of the present invention is to provide a kind of management devices of buffer address.
The present invention is achieved in that a kind of management method of buffer address, and described method comprises:
The distribution state of record buffer memory address;
The verification distribution state of cache addresses is distributed or is reclaimed described buffer address according to the distribution state of cache addresses check results.
When distributing buffer address, when the described buffer address of verification is in idle condition, distribute described buffer address, and to revise described distribution state of cache addresses be seizure condition.
When distributing buffer address, when the described buffer address of verification is in seizure condition, does not carry out buffer address and distribute.
Described method further comprises and reports buffer address duplicate allocation mistake, and the step of counting.
When reclaiming buffer address, when the described buffer address of verification is in seizure condition, reclaim described buffer address, and to revise described distribution state of cache addresses be idle condition.
Described method further comprises the step of calculating and storing the parity check bit of described buffer address.
When distributing buffer address, before the verification distribution state of cache addresses, described method further comprises the steps:
The parity check bit of the described buffer address of verification, the then described distribution state of cache addresses of verification is passed through in parity check, and address assignment is not then carried out in the parity check failure.
Described method further comprises and reports buffer address to repeat to reclaim mistake, and the step of counting.
When reclaiming buffer address, when the described buffer address of verification is in idle condition, does not carry out buffer address and reclaim.
Described method further comprises and reports parity error, and the step of counting.
A kind of management devices of buffer address, described device comprises:
The buffer address memory is used to store the free buffer address;
The address state memory module is used for the distribution state of record buffer memory address;
Address state verification module is used for the verification distribution state of cache addresses; And
The buffer address administration module is used for distributing or the recovery buffer address according to the distribution state of cache addresses check results.
Described device further comprises:
The parity check bit computing module is used for when the verification buffer address is in seizure condition, calculating the parity check bit of described buffer address when reclaiming buffer address; And
The parity check module is used for when distributing buffer address, before the verification distribution state of cache addresses, and the parity check bit of the described buffer address of verification.
The present invention carries out the distribution state verification when buffer address distributes or reclaim, thereby by expending less cache resources, the circulation of avoiding buffer address duplicate allocation, buffer address to repeat to reclaim makes mistakes and causes switching network to lose efficacy.Simultaneously, even some bit inefficacy of the SRAM of FAFIFO or mistake and internal circuit mistake cause the buffer address mistake, the system that also do not influence normally moves.
Description of drawings
Fig. 1 is the realization flow figure that buffer address provided by the invention distributes;
Fig. 2 is the realization flow figure that buffer address provided by the invention reclaims;
Fig. 3 is the realization flow figure that the buffer address that provides in the preferred embodiment of the present invention distributes;
Fig. 4 is the realization flow figure that the buffer address that provides in the preferred embodiment of the present invention reclaims;
Fig. 5 is the structure chart of buffer address management devices provided by the invention.
Embodiment
In order to make purpose of the present invention, technical scheme and advantage clearer,, the present invention is further elaborated below in conjunction with drawings and Examples.Should be appreciated that specific embodiment described herein only in order to explanation the present invention, and be not used in qualification the present invention.
In the present invention, the distribution state of record buffer memory address, system carries out verification to distribution state of cache addresses, thereby avoids the duplicate allocation of buffer address or repeat to reclaim mistake when distributing or reclaim buffer address.
The example structure of the Entry of record buffer memory address assignment state is as shown in the table:
| Field | Description |
| AS | Address Status: address state.FA territory corresponding cache is in idle condition among the AS=0:FAFIFO; FA territory corresponding cache is in seizure condition among the AS=1:FAFIFO. |
The state value of all buffer address is zero when initial, and promptly all buffer address are in idle condition.
Fig. 1 shows buffer address allocation flow provided by the invention, and details are as follows:
In step S101, when cell is joined the team, read a buffer address;
In step S102, this distribution state of cache addresses is carried out verification, judge whether this buffer address takies, if this buffer address is in idle condition, execution in step S103 then, otherwise execution in step S104;
In step S103, this buffer address is distributed to this cell of joining the team, revising this distribution state of cache addresses is seizure condition;
In step S104, abandon current cell, do not carry out the buffer address batch operation;
In step S105, report buffer address duplicate allocation mistake, and counting, so that system carries out error statistics and analysis;
Fig. 2 shows buffer address recovery process provided by the invention, and details are as follows:
In step S201, when cell goes out group, read the distribution state of this cell corresponding cache address;
In step S202, this distribution state of cache addresses is carried out verification, judge whether this buffer address takies, if this buffer address is in seizure condition, execution in step S203 then, otherwise execution in step S204;
In step S203, cell goes out team, reclaims this buffer address, and revising this distribution state of cache addresses is idle condition;
In step S204, cell goes out team, does not carry out follow-up buffer address reclaimer operation;
In step S205, report buffer address to repeat to reclaim mistake, and counting, so that system carries out error statistics and analysis.
As a preferred embodiment of the present invention, to buffer address configuration parity check bit Par, when distributing buffer address, before distribution state of cache addresses is carried out verification, earlier buffer address is carried out parity check, the system of being convenient to carries out location of mistake accurately, statistics and analysis.
Record has added the example structure (the supposition buffer memory capacity is 4k, and then the FAFIFO address width is 12bit) as shown in the table of the Entry of parity check bit Par:
| Field | Description |
| Par | Parity: parity check bit.Par=0: the number in expression Fa territory 1 is an odd number; Par=1: the number in expression Fa territory 1 is an even number. |
| Fa[11:0] | Free address: free buffer address |
Wherein, Par is not limited to the highest order as buffer address, also can be placed on lowest order or other positions of an Entry.
Fig. 3 shows the buffer address allocation flow under the present embodiment, and details are as follows:
In step S301, when cell is joined the team, read a buffer address;
In step S302, this buffer address is carried out parity check, verify promptly whether the value of Par is correct, if execution in step S303 then, otherwise execution in step S307 are passed through in parity check;
In step S303, this distribution state of cache addresses is carried out verification, judge whether this buffer address takies, if this buffer address is in idle condition, execution in step S304 then, otherwise execution in step S305;
In step S304, this buffer address is distributed to this cell of joining the team, revising this distribution state of cache addresses is seizure condition;
In step S305, abandon current cell, do not carry out the buffer address batch operation;
In step S306, report buffer address duplicate allocation mistake, and counting, so that system carries out error statistics and analysis;
In step S307, abandon current cell, do not carry out the buffer address batch operation;
In step S308, report parity error, and counting.
Accordingly, Fig. 4 shows the buffer address recovery process under the present embodiment, and details are as follows:
In step S401, when cell goes out group, read the distribution state of this cell corresponding cache address;
In step S402, this distribution state of cache addresses is carried out verification, judge whether this buffer address takies, if this buffer address is in seizure condition, execution in step S403 then, otherwise execution in step S405;
In step S403, cell goes out team, calculates and add the Par value of this buffer address;
In step S404, reclaim this buffer address, the state of revising this buffer address is an idle condition;
In step S405, cell goes out team, does not carry out follow-up address reclaimer operation;
In step S406, report buffer address to repeat to reclaim mistake, and counting, so that system carries out error statistics and analysis.
Fig. 5 shows the structure of buffer address management devices 500 provided by the invention, buffer address memory 501 storage free buffer addresses, the distribution state of address state memory module 502 record buffer memory addresses.When cell is joined the team, buffer address administration module 503 is read a buffer address from buffer memory addressed memory 501, address state verification module 504 is according to this distribution state of cache addresses of address state-storage module 502 records, judge whether this buffer address is in idle condition, if this buffer address is in idle condition, buffer address administration module 503 is distributed to this cell of joining the team with this buffer address, otherwise abandon this cell of joining the team, not carrying out buffer address distributes, address state verification module 504 reports buffer address duplicate allocation mistake, and counting.After buffer address distributed, address state memory module 502 was revised as seizure condition with this distribution state of cache addresses.
When cell goes out group, address state verification module 504 is according to the distribution state of this cell corresponding cache address of address state-storage module 502 records, judge whether buffer address is in seizure condition, if this buffer address is in seizure condition, buffer address administration module 503 reclaims this buffer address, write buffer address memory 501, address state memory module 502 is revised as idle condition with this distribution state of cache addresses.If this buffer address is in idle condition, buffer address administration module 503 does not carry out buffer address and reclaims, and address state verification module 504 reports buffer address to repeat to reclaim mistake, and counting.
As the preferred embodiments of the present invention, buffer address management devices 500 further comprises parity check module 505 and parity check bit computing module 506.When cell is joined the team, buffer address is carried out the branch timing, before 504 pairs of distribution state of cache addresses of address state verification module are carried out verification, parity check module 505 is carried out parity check to buffer address earlier, after verification is passed through, carry out verification by 504 pairs of distribution state of cache addresses of address state verification module again.If the parity check failure, parity check module 505 reports parity error, and buffer address administration module 503 does not distribute this buffer address, abandons current cell.
When cell goes out team, when buffer address was reclaimed, parity check bit computing module 506 calculated the parity check bit of the buffer address that reclaims, and writes buffer address memory 501.
Need to prove, more than with unicast cell to go out, join the team be that example describes buffer address guard method provided by the invention, the realization flow of relevant multicast cell is similar, repeats no more.
The present invention under the fewer situation of the extra resource that expends, thereby can avoid in the system owing to preserve that the RAM part bit of free buffer address lost efficacy and cell goes out the address duplicate allocation that team's management causes unusually and repeat recovery to cause the out of order or cell error of switching network cell.Realize that resource required for the present invention is relevant with cache size, for the buffer memory of a 4K size, need 4k (parity check)+4k (address state verification)+a small amount of control logic altogether, promptly 8k RAM and a small amount of control logic promptly can realize.
In addition, the present invention considers various possible abnormal conditions, even occurred unusually, not only can quote at corresponding abnormal conditions and interrupt and counting, and eliminated follow-up influence to switching network except abandoning corresponding cell.Even abnormal conditions occur, except that current report an error and dropped cell, system can normally move.
The above only is preferred embodiment of the present invention, not in order to restriction the present invention, all any modifications of being done within the spirit and principles in the present invention, is equal to and replaces and improvement etc., all should be included within protection scope of the present invention.
Claims (5)
1. the management method of a buffer address is used for FAFIFO (Free Address First In First Out, FAFIFO, buffer address first in first out) management free buffer address, it is characterized in that, said method comprising the steps of:
Step S101 when cell is joined the team, reads a buffer address;
Step S102, described distribution state of cache addresses is carried out verification, judge whether described buffer address takies, if described buffer address is in idle condition, then described buffer address is distributed to this cell of joining the team, revising described distribution state of cache addresses is seizure condition; If described buffer address is not in idle condition, then abandon current cell, do not carry out described buffer address batch operation, report described buffer address duplicate allocation mistake.
2. the management method of buffer address as claimed in claim 1 is characterized in that, and is further comprising the steps of:
Step S201 when cell goes out group, reads the distribution state of this cell corresponding cache address;
Step S202 carries out verification to this distribution state of cache addresses, judges whether this buffer address takies, if this buffer address is in seizure condition, then cell goes out team, reclaims this buffer address, and revising this distribution state of cache addresses is idle condition; If this buffer address is not in seizure condition, then cell goes out team, does not carry out follow-up buffer address reclaimer operation, reports buffer address to repeat to reclaim mistake.
3. the management devices of a buffer address is used for FAFIFO (Free Address First In First Out, FAFIFO, buffer address first in first out) management free buffer address, it is characterized in that described device comprises:
The buffer address memory is used to store the free buffer address;
The address state memory module is used for the distribution state of record buffer memory address;
Address state verification module is used for the verification distribution state of cache addresses; And
The buffer address administration module is used for distributing or the recovery buffer address according to the distribution state of cache addresses check results;
Wherein, when cell is joined the team, the buffer address administration module is read a buffer address from the buffer memory addressed memory, this distribution state of cache addresses of location, address state verification module base area state-storage module record, judge whether this buffer address is in idle condition, if this buffer address is in idle condition, the buffer address administration module is distributed to this cell of joining the team with this buffer address, otherwise abandon this cell of joining the team, do not carry out buffer address and distribute, address state verification module reports buffer address duplicate allocation mistake.
4. the management devices of buffer address as claimed in claim 3 is characterized in that, described device further comprises:
The parity check bit computing module is used for when the verification buffer address is in seizure condition, calculating the parity check bit of described buffer address when reclaiming buffer address; And
The parity check module is used for when distributing buffer address, before the verification distribution state of cache addresses, and the parity check bit of the described buffer address of verification.
5. the management devices of buffer address as claimed in claim 4 is characterized in that, when cell goes out team, when buffer address was reclaimed, the parity check bit computing module also was used to calculate the parity check bit of the buffer address of recovery, and writes the buffer address memory.
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| CN2006100608775A CN1984042B (en) | 2006-05-23 | 2006-05-23 | Method and device for managing buffer address |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101420372B (en) * | 2008-10-16 | 2010-12-08 | 电子科技大学 | On-chip network cache allocation method |
| CN102857446B (en) * | 2011-06-30 | 2017-09-29 | 中兴通讯股份有限公司 | The buffer memory management method and device of Ethernet switching chip |
| CN102739818B (en) * | 2012-06-21 | 2015-05-27 | 华为技术有限公司 | Address scheduling method, device and system |
| CN110971481B (en) * | 2019-11-05 | 2021-11-05 | 天津芯海创科技有限公司 | Method and device for testing cache address management logic |
| CN117424865A (en) * | 2023-12-18 | 2024-01-19 | 南京华芯科晟技术有限公司 | Message address management device, network processing chip, message reading and storing method |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1532708A (en) * | 2003-03-19 | 2004-09-29 | 华为技术有限公司 | Static internal storage management method |
| CN1581064A (en) * | 2003-08-13 | 2005-02-16 | 华为技术有限公司 | Timer management method |
| CN1752949A (en) * | 2004-09-24 | 2006-03-29 | 上海贝尔阿尔卡特股份有限公司 | Internal storage management system and method |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1532708A (en) * | 2003-03-19 | 2004-09-29 | 华为技术有限公司 | Static internal storage management method |
| CN1581064A (en) * | 2003-08-13 | 2005-02-16 | 华为技术有限公司 | Timer management method |
| CN1752949A (en) * | 2004-09-24 | 2006-03-29 | 上海贝尔阿尔卡特股份有限公司 | Internal storage management system and method |
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