CN1752949A - Internal storage management system and method - Google Patents
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- CN1752949A CN1752949A CNA2004100666555A CN200410066655A CN1752949A CN 1752949 A CN1752949 A CN 1752949A CN A2004100666555 A CNA2004100666555 A CN A2004100666555A CN 200410066655 A CN200410066655 A CN 200410066655A CN 1752949 A CN1752949 A CN 1752949A
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Abstract
The present invention provides an internal storage management method. It is characterized by including the following steps: when the internal storage cell is initialized, giving specific value to check pointer in internal storage control block of every internal storage block; buffer storage block distribution request responding to the process, and buffer storage block return request responding to the process. Said invention also provides the concrete requirement of every step. Besides, said invention also provides the internal storage management system by using said method.
Description
Technical field
The present invention relates to memory management, relate in particular to internal storage management system and method in the communication facilities.
Background technology
In the communication facilities of prior art, according to the requirement of internal storage management system, memory pool is divided into a plurality of memory blocks, and each memory block comprises a cache blocks.In response to the request of process, internal storage management system dynamically is a course allocation free buffer piece, perhaps the cache blocks given back of receiving process.Cache blocks has the capacity of regulation, for example 64 bytes, 128 bytes, 2048 bytes etc.According to the difference of cache blocks capacity, memory block correspondingly is divided into polytype.The memory block of same type is connected into chain by pointer chain, passes through corresponding memory block begin chain makeup ring then.Internal storage management system utilizes the memory block begin chain, and the memory block that is linked into ring is managed.
Fig. 1 schematically shows memory block chain structure of the prior art.As shown in Figure 1, label 110 expression memory block begin chains, label 120 expression memory blocks.As an example, only show three memory blocks 120 among Fig. 1, they all comprise the cache blocks of same capability.
Fig. 2 A is the schematic configuration diagram of the memory block begin chain among Fig. 1.Shown in Fig. 2 A, memory block begin chain 110 has fields such as precursor pointer 111, heir pointer 112, chain information 113.Precursor pointer 111 is used for depositing the start address of last memory block of memory block chain; Heir pointer 112 is used for depositing the start address of first memory block of memory block chain; Chain information 113 is used to deposit and the relevant information of current memory block chain, the type of memory block in for example current memory block chain, the capacity of for example included cache blocks etc.
Fig. 2 B is the schematic configuration diagram of the memory block among Fig. 1.Shown in Fig. 2 B, memory block 120 comprises MCB 130 and cache blocks 124.MCB 130 comprises fields such as precursor pointer 121, heir pointer 122 and block message 123.Precursor pointer 121 is used for depositing the start address of the last memory block of the current memory block of memory block chain; Heir pointer 122 is used for depositing the start address of a back memory block of the current memory block of memory block chain; Block message 123 is used to deposit the information relevant with the managing internal memory piece, and for example whether this memory block is occupied etc.Cache blocks 124 after the process of being assigned to, is used by process.Be assigned to the cache blocks of process, comprise that the memory block of this cache blocks is extractd from the memory block chain, and this memory block is linked to the process control block (PCB) of this process by operating system.Like this, when process was collapsed, the memory block that process is applied for can be operated system and discharge.Therefore, in actual conditions, the memory block that links in the memory block chain all is a free memory block.
For example use get_mem primitive when process and (for example distribute a specified type to the internal memory management system requested, during 64 bytes) cache blocks, internal storage management system at first finds in memory pool shown in Figure 1 and the corresponding memory block begin chain of this specified type (for example the memory block begin chain 110), then in the memory block chain headed by this memory block begin chain, find the memory block of its cache blocks free time, as free memory block.As mentioned before, the memory block that links in the memory block chain all is a free memory block.So, in the above-mentioned steps, only need get first memory block in the memory block chained list simply, can obtain a free memory block.Then, internal storage management system carries out allocation process to this free memory block.Allocation process for example comprises: (1) will ask to distribute the process number of the process of cache blocks to write ad-hoc location in the block message included in the MCB of this free memory block, show that this free memory block is to take; (2) from the memory block chain, extract this memory block, and this memory block is linked to the process control block (PCB) of this process.After allocation process was finished, internal storage management system returned to process with the address of this free buffer piece.After this, process can be used this free buffer piece.
When process for example used the ret_mem primitives to give back cache blocks, this process was specified a memory address to internal storage management system, as the address of waiting to give back cache blocks.Because the structure of MCB and size are predesignated (for example shown in Fig. 2 B) by internal storage management system, so internal storage management system will wait to give back a segment memory content before the address of cache blocks as the MCB corresponding to the memory block of waiting to give back cache blocks.The MCB that to so determine among the present invention is called pseudo-MCB, will be called pseudo-memory block corresponding to the memory block of pseudo-MCB.Then, internal storage management system discharges processing to pseudo-memory block.Discharge to handle and for example to comprise: the process number of process that (1) gives back request cache blocks specific location in the included block message from the pseudo-MCB of pseudo-memory block is removed, and shows that this puppet memory block becomes the free time; (2) should separate with the process control block (PCB) (1) of this process by the puppet memory block, and should insert memory block chain (inserting at last-of-chain usually) by the puppet memory block.After release was finished dealing with, the notification process cache blocks was successfully given back.
Yet above-mentioned internal storage management system has following shortcoming.For example, when process to the internal memory management system requested give back cache blocks but because a variety of causes provides sensing when waiting to give back the address (calling " invalid address " in the following text) of cache blocks, internal storage management system can not be discovered this mistake, and still as mentioned above, with the segment memory content before this invalid address as MCB (being actually a false MCB) corresponding to the memory block of waiting to give back cache blocks, to this segment memory content false make amendment.This modification is breakneck, because the content of being revised may be the content of just being used by other processes or operating system.In addition, this hack to memory content very likely destroys the various links in the memory pool.Under the serious situation, cause system crash.
In the existing internal storage management system; safeguard measure at above-mentioned situation is not provided; so; even the cache blocks address that process requested is given back is the invalid address; process also will continue operation; produce the General Protection Fault mistake until this process or other processes, the unwarranted visit to internal memory has promptly taken place.The General Protection Fault mistake occurs in the ret_mem primitive, and ret_mem primitive can be by any process transfer.So, be difficult to follow the tracks of and repair and cause the mistake of invalid address.When null pointer had destroyed memory pool, operating system had to restart.
Summary of the invention
The objective of the invention is to improve the mistake proofing performance of internal storage management system, prevent the further expansion of memory address operating mistake, avoid system crash.
For achieving the above object, the invention provides a kind of EMS memory management process, it is characterized in that may further comprise the steps:
When the initialization memory pool, particular value is composed to the inspection pointer in the MCB of each memory block;
In response to the cache blocks request for allocation of process, in described memory pool, search a free memory block, and the cache blocks that comprises in the described free memory block is distributed to described process; And
Cache blocks in response to process is given back request, according to the memory address of described process as the address appointment of pseudo-cache blocks, pseudo-MCB in location in described memory pool, and when only the value of the inspection pointer in described pseudo-MCB satisfies specified conditions, just discharge described pseudo-cache blocks.
The present invention also provides a kind of internal storage management system, it is characterized in that comprising:
Memory pool comprises a plurality of memory blocks, and each memory block comprises a MCB and a cache blocks, and the inspection pointer in the described MCB is endowed particular value;
The cache blocks distributor is used for the cache blocks request for allocation in response to process, searches a free memory block in described memory pool, and the cache blocks that comprises in the described free memory block is distributed to described process; And
The cache blocks releasing means, be used for giving back request in response to the cache blocks of process, according to the memory address of described process as the address appointment of pseudo-cache blocks, pseudo-MCB in location in described memory pool, and when only the value of the inspection pointer in described pseudo-MCB satisfies specified conditions, just discharge described pseudo-cache blocks.
According to internal storage management system of the present invention and method, can be before giving back cache blocks, detect the validity of the address of waiting to give back cache blocks.When detecting the address of waiting to give back cache blocks and be an invalid address, that is to say, when cache blocks to be given back is a false cache blocks, can not discharge this cache blocks, and process number and entry record that the process of this cache blocks is given back in this invalid address and request are got off, so that follow the tracks of and repair relevant mistake.
After reading the detailed description of embodiment of the present invention in conjunction with the accompanying drawings, other characteristics of the present invention and advantage will become clearer.
Description of drawings
Fig. 1 schematically shows memory block chain structure of the prior art;
Fig. 2 A is the schematic configuration diagram of the memory block begin chain among Fig. 1;
Fig. 2 B is the schematic configuration diagram of the memory block among Fig. 1;
Fig. 3 is the memory block schematic configuration diagram that adopts among a kind of embodiment according to internal storage management system of the present invention;
Fig. 4 is the process flow diagram according to a kind of embodiment of EMS memory management process of the present invention;
Fig. 5 is the schematic configuration diagram according to a kind of embodiment of internal storage management system of the present invention.
Embodiment
Below in conjunction with accompanying drawing embodiments of the invention are described.
Fig. 1 schematically shows memory block chain structure of the prior art, and Fig. 2 A is the schematic configuration diagram of the memory block begin chain among Fig. 1, and Fig. 2 B is the schematic configuration diagram of the memory block among Fig. 1.These figure are in the existing description of preamble.
In a kind of embodiment, adopt and the similar structure of memory block chain structure shown in Figure 1 according to internal storage management system of the present invention.That is to say that in an embodiment of the present invention, also memory pool is divided into a plurality of memory blocks, each memory block comprises a cache blocks.In response to the request of process, internal storage management system dynamically is a course allocation free buffer piece, the cache blocks that perhaps release process is given back.Cache blocks has the capacity of regulation, for example 64 bytes, 128 bytes, 2048 bytes etc.According to the difference of cache blocks capacity, memory block correspondingly is divided into polytype.The memory block of same type is connected into chain by pointer chain, passes through corresponding memory block begin chain makeup ring then.Internal storage management system utilizes the memory block begin chain, and the memory block that is linked into ring is managed.The main difference of the internal storage management system of the present invention and prior art is the structure of memory block.
Fig. 3 is the memory block schematic configuration diagram that adopts among a kind of embodiment according to internal storage management system of the present invention.As shown in Figure 3, memory block 320 comprises MCB 330 and cache blocks 325.MCB 330 comprises fields such as precursor pointer 321, heir pointer 322, block message 323 and inspection pointer 324.Precursor pointer 321 is used for depositing the start address of the last memory block of the current memory block of memory block chain; Heir pointer 322 is used for depositing the start address of a back memory block of the current memory block of memory block chain; Block message 323 is used to deposit the information relevant with the managing internal memory piece, and for example whether this memory block is occupied etc.; Check that pointer 324 is used for the start address of memory buffers piece 325.Alternately, check pointer 324 also can store a kind of by the internal storage management system regulation, be enough to differentiate that cache blocks 325 is the true cache blocks or the particular value of false cache blocks.Cache blocks 325 after the process of being assigned to, is used by process.
In the initialization procedure of the communication facilities that adopts above-mentioned internal storage management system, internal storage management system carries out initialization to each memory block chain.One of them important step is that the inspection pointer in each MCB is carried out assignment.
After the initialization, internal storage management system can dynamically be a course allocation free buffer piece in response to the request of process just, the cache blocks that perhaps release process is given back.
Fig. 4 is the process flow diagram according to a kind of embodiment of EMS memory management process of the present invention.As shown in Figure 4, flow process is carried out initialization in step 402 then from step 401.The initialization of carrying out in initialization and the conventional memory management system is similar, promptly the various pointers in each memory block chain in the memory pool, chain information, block message etc. is carried out initial assignment.One of them important step is to give particular value to the inspection pointer in each MCB (as the MCB among Fig. 3 330) (shown in the inspection pointer 324 among Fig. 3).In an example, for each memory block, this particular value is the start address of the cache blocks that comprises in this memory block.In another example, this particular value is one is enough to differentiate that pseudo-cache blocks is the true cache blocks or the value of false cache blocks, for example can be 0xFFFFFFFF.
After step 402, flow process proceeds to step 403.Step 403 to step 430 is formed a circulation, is used to the request of the process that responds, and the cache blocks of giving back for course allocation free buffer piece, release process or carry out other processing dynamically is until termination condition occurring.Below step 403 to step 430 is described in detail.
In step 403, the request of internal storage management system receiving process.
In step 404, judge whether the request of process is the request that distributes cache blocks.If the judged result of step 404 is that then flow process does not proceed to step 414, otherwise proceeds to step 405.
In step 405, in memory pool, search a corresponding memory block begin chain of the type (for example 64 bytes, 128 bytes, 2048 bytes etc.) with the cache blocks of ask distribution.The structure example of this memory block begin chain is as shown in Fig. 2 A.
Then, in step 406, in the memory block chain that this memory block begin chain is linked, search a memory block (being called free memory block) that comprises the free buffer piece.Adopting which kind of algorithm to search free memory block is not construed as limiting the present invention.The present invention can adopt any effective algorithm of the prior art to search a free memory block.Be preferably, adopt fastest algorithm.As mentioned before, usually, first memory block in the memory block chain is free memory block.
In step 407, judge whether to find a free memory block.If the judged result of step 407 is "No", then flow process proceeds to step 410; Otherwise proceed to step 408.
In step 408, to distributing the requirement of cache blocks process, the free memory block that finds is carried out allocation process according to internal storage management system.Allocation process described here is identical with the free memory block allocation process of the prior art that preamble is described, and repeats no more.
Then, in step 409, the start address of the cache blocks in this memory block is returned to process.So far, finish assigning process to a free buffer piece.
If the judged result of step 407 is that then flow process does not proceed to step 410.
In step 410, return the value that an expression cache blocks distributes failure to process.
If the judged result of step 404 is that then flow process does not proceed to step 414.
In step 414, judge whether the request of process is the request of giving back cache blocks.If the judged result of step 414 is for being that then flow process proceeds to step 415; Otherwise flow process proceeds to step 421.
In step 415, according to the memory address of process as the address appointment of pseudo-cache blocks, pseudo-MCB in location in memory pool.With memory block structure shown in Figure 3 is example.Suppose that memory address is 32, promptly four byte longs suppose that also block message 323 also is four byte longs, and then the length of MCB 330 is 16 bytes.Like this, because the memory address of process appointment is thought the start address of pseudo-cache blocks to be given back (as the cache blocks among Fig. 3 325), so, in step 415,16 bytes of memory device contents before the memory address of process appointment (as the precursor pointer 321 among Fig. 3 to the content between the inspection pointer 324) are thought to comprise the pseudo-MCB (as the MCB among Fig. 3 330) of the pseudo-memory block (as the memory block among Fig. 3 320) of pseudo-cache blocks.
In step 416, the value and the particular value of the detection pointer in the pseudo-MCB compared.
In step 417, according to the comparative result in the step 416, judge whether the value of the detection pointer in the pseudo-MCB satisfies specified conditions, promptly whether with special values match.With reference to as described in Fig. 3, check that the value of pointer can be the start address of cache blocks as preamble, also can be the internal storage management system regulation, be enough to differentiate that pseudo-cache blocks is the true cache blocks or the particular value of false cache blocks.
In the internal storage management system regulation is checked pointer, store be the start address of cache blocks the time, the situation of judging coupling in the step 417 is meant that the memory address of process appointment equates with the value of inspection pointer.
In the internal storage management system regulation is checked pointer, store be regulation particular value (such as, in the time of 0xFFFFFFFF), the situation of judging coupling in the step 417 is meant that the memory address of process appointment equates with this particular value.
In a word, step 416 and step 417 be for the memory address of checking the process requested internal storage management system to discharge whether be effective cache blocks start address.
If the judged result of step 417 is for being (that is, process is given back true cache blocks), then flow process proceeds to step 418; Otherwise (that is, process is given back false cache blocks) proceeds to step 420.
In step 418, according to the process of internal storage management system release cache blocks, the pseudo-memory block that step 415 is determined discharges processing.Release processing described here is identical with the of the prior art pseudo-memory block release processing that preamble is described, and repeats no more.
In step 420, the memory address (being defined as the invalid address in step 417) of process number and entry address and process appointment is recorded in the daily record, so that can follow the tracks of and repair relevant mistake.
After step 418 and the step 420, flow process all proceeds to step 419.
In step 419, return the value that an expression cache blocks is given back success to process.
What deserves to be explained is that specify in process under the situation of invalid address, flow process proceeds to step 419 through step 420, thus internal storage management system any content in the memory pool is not made amendment, but return the value that an expression cache blocks is given back success to process.Do like this that the process of being based on is unactual to take the storage space that memory address that its request gives back points to.
Certainly, also can be chosen in after the step 420, return the value that an expression cache blocks is given back failure, and then do corresponding processing by process to process.Perhaps, call a tracing process by internal storage management system.
In addition, between step 415 and step 416, also can add the step whether a memory address of judging that request is given back is positioned at the memory pool address space.If the memory address that the request judged is given back is outside the memory pool address space, then flow process is directly to step 420; Otherwise proceed to step 416.
In step 421, other requests of process are handled by internal storage management system.
After above-mentioned steps 410,409,419,421, flow process proceeds to step 430.
In step 430, judge whether to finish the operation of internal storage management system.For example, when communication facilities shuts down, can judge the operation that needs to finish internal storage management system.Certainly, step 430 also can be arranged in other positions of flow process, thereby is not construed as limiting the invention.
If the judged result of step 430 is that then flow process does not turn back to step 403; Otherwise flow process proceeds to step 440.
In step 440, flow process finishes.
Fig. 5 is the schematic configuration diagram according to a kind of embodiment of internal storage management system of the present invention.As shown in Figure 5, internal storage management system of the present invention comprises memory pool 501, cache blocks distributor 502, cache blocks releasing means 503 and Error Recording Device 504.Internal storage management system shown in Figure 5 is according to principle work shown in Figure 4.
Comprise a plurality of memory blocks in the internal memory 501, each memory block comprises a MCB and a cache blocks, and the inspection pointer in the MCB is endowed particular value.The structure of memory block can be as shown in Figure 3, but be not limited to Fig. 3.
Cache blocks distributor 502 is used for the cache blocks request for allocation in response to process 505, searches a free memory block in memory pool 501, and the cache blocks that comprises in this free memory block is distributed to process 505.
Cache blocks discharges adorns 503, be used for giving back request in response to the cache blocks of process 505, according to the memory address of process 505 as the address appointment of pseudo-cache blocks, pseudo-MCB in location in memory pool 501, and when only the value of the inspection pointer in this puppet MCB satisfies specified conditions, just discharge this puppet cache blocks.
The specified conditions that cache blocks releasing means 503 is judged are meant that the value of the inspection pointer in the pseudo-MCB equals particular value.In memory pool 501, for each memory block, this particular value is the start address of the cache blocks that comprises in the memory block.In addition, this particular value also can be one is enough to differentiate that pseudo-cache blocks is other values of true cache blocks or false cache blocks.
When this particular value was the start address of the cache blocks that comprises in the memory block, the specified conditions that cache blocks releasing means 503 is judged were meant that the value of the inspection pointer in the pseudo-MCB equals the memory address of process 505 as the address appointment of pseudo-cache blocks.
Though below described embodiments of the present invention in conjunction with the accompanying drawings, those skilled in the art can make various distortion or modification within the scope of the appended claims in this area.
Claims (12)
1. EMS memory management process is characterized in that may further comprise the steps:
When the initialization memory pool, particular value is composed to the inspection pointer in the MCB of each memory block;
In response to the cache blocks request for allocation of process, in described memory pool, search a free memory block, and the cache blocks that comprises in the described free memory block is distributed to described process; And
Cache blocks in response to process is given back request, according to the memory address of described process as the address appointment of pseudo-cache blocks, pseudo-MCB in location in described memory pool, and when only the value of the inspection pointer in described pseudo-MCB satisfies specified conditions, just discharge described pseudo-cache blocks.
2. according to the EMS memory management process of claim 1, it is characterized in that:
In the step of the described pseudo-cache blocks of described release, described specified conditions are meant that the value of the inspection pointer in the described pseudo-MCB equals described particular value.
3. according to the EMS memory management process of claim 2, it is characterized in that:
For each described memory block, described particular value is the start address of the cache blocks that comprises in the described memory block.
4. according to the EMS memory management process of claim 2, it is characterized in that:
Described particular value is one is enough to differentiate whether pseudo-cache blocks is the value of true cache blocks.
5. according to the EMS memory management process of claim 1, it is characterized in that:
In the step of described initialization memory pool, for each described memory block, described particular value is the start address of the cache blocks that comprises in the described memory block;
In the step of the described pseudo-cache blocks of described release, described specified conditions are meant that the value of the inspection pointer in the described pseudo-MCB equals the memory address of described process as the address appointment of pseudo-cache blocks.
6. according to the EMS memory management process of claim 1, it is characterized in that further comprising the steps of:
When the value of the inspection pointer in described pseudo-MCB does not satisfy described specified conditions, write down at least one in the entry address of described pseudo-cache blocks address, the process number of described process, described process.
7. internal storage management system is characterized in that comprising:
Memory pool comprises a plurality of memory blocks, and each memory block comprises a MCB and a cache blocks, and the inspection pointer in the described MCB is endowed particular value;
The cache blocks distributor is used for the cache blocks request for allocation in response to process, searches a free memory block in described memory pool, and the cache blocks that comprises in the described free memory block is distributed to described process; And
The cache blocks releasing means, be used for giving back request in response to the cache blocks of process, according to the memory address of described process as the address appointment of pseudo-cache blocks, pseudo-MCB in location in described memory pool, and when only the value of the inspection pointer in described pseudo-MCB satisfies specified conditions, just discharge described pseudo-cache blocks.
8. according to the internal storage management system of claim 7, it is characterized in that:
The described specified conditions that described cache blocks releasing means is judged are meant that the value of the inspection pointer in the described pseudo-MCB equals described particular value.
9. internal storage management system according to Claim 8 is characterized in that:
In described memory pool, for each described memory block, described particular value is the start address of the cache blocks that comprises in the described memory block.
10. internal storage management system according to Claim 8 is characterized in that:
Described particular value is one is enough to differentiate whether pseudo-cache blocks is the value of true cache blocks.
11. the internal storage management system according to claim 7 is characterized in that:
In described memory pool, for each described memory block, described particular value is the start address of the cache blocks that comprises in the described memory block; And
The described specified conditions that described cache blocks releasing means is judged are meant that the value of the inspection pointer in the described pseudo-MCB equals the memory address of described process as the address appointment of pseudo-cache blocks.
12., it is characterized in that also comprising according to the internal storage management system of claim 7:
Error Recording Device is used for when the value of the inspection pointer of described pseudo-MCB does not satisfy described specified conditions, writes down at least one in the entry address of described pseudo-cache blocks address, the process number of described process, described process.
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| CN1984042B (en) * | 2006-05-23 | 2010-10-27 | 华为技术有限公司 | Method and device for managing buffer address |
| CN101286878B (en) * | 2008-04-22 | 2012-02-29 | 中兴通讯股份有限公司 | Management method of memory pool for terminal |
| CN102455943A (en) * | 2010-10-19 | 2012-05-16 | 上海聚力传媒技术有限公司 | Method for carrying out data sharing based on memory pool, and computer device |
| CN102455943B (en) * | 2010-10-19 | 2016-12-14 | 上海聚力传媒技术有限公司 | A kind of method and computer equipment carrying out data sharing based on memory pool |
| CN103246608A (en) * | 2012-02-01 | 2013-08-14 | 联想(北京)有限公司 | Method and device for distributing storage space |
| CN102866929A (en) * | 2012-07-23 | 2013-01-09 | 上海斐讯数据通信技术有限公司 | Bad block repair method for memory |
| CN102866929B (en) * | 2012-07-23 | 2015-08-19 | 上海斐讯数据通信技术有限公司 | Bad block repair method for memory |
| CN103049328A (en) * | 2012-11-06 | 2013-04-17 | 苏州懿源宏达知识产权代理有限公司 | Distribution method of internal memory resources in computer system |
| CN112000471A (en) * | 2020-08-10 | 2020-11-27 | 海信电子科技(武汉)有限公司 | Memory optimization method and device |
| CN112000471B (en) * | 2020-08-10 | 2023-10-27 | Vidaa(荷兰)国际控股有限公司 | Memory optimization method and device |
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