CN1983886A - Equipment for testing SDII/SONET apparatus external clock - Google Patents
Equipment for testing SDII/SONET apparatus external clock Download PDFInfo
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- CN1983886A CN1983886A CN 200610060459 CN200610060459A CN1983886A CN 1983886 A CN1983886 A CN 1983886A CN 200610060459 CN200610060459 CN 200610060459 CN 200610060459 A CN200610060459 A CN 200610060459A CN 1983886 A CN1983886 A CN 1983886A
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Abstract
The invention is concerned with clock testing equipment outside of SDH/SONET. The clock product equipment products benchmark clock. E1/DS1 circuitry interface part changes clock outside of Bit to SDH/SONET equipment into Hz clock and exports it as test-needed signal. Sub-test equipment relates to synchronizer, device for taking count and account equipment. The sub-test equipment accepts test-needed signal, the synchronizer makes the test-needed signal from the sub-test equipment and benchmark clock in-phase, device for taking count counts the test-needed signal in-phase by benchmark clock, and account equipment counts the result of account. The test equipment relates to clock interface equipment outside test-needed Hz accepting and affording clock outside of Hz test-needed SDH/SONET as test-need signal, and equipment for Hz and Bit reference clock. The said test equipment relates to phase difference test and lightening equipment to carry phase difference test about the SDH/SONET equipment under locked or work.
Description
Invention field
The present invention relates to the clock test technical field, more specifically, relate to a kind of SDH/SONET equipment external clock testing equipment.
Background technology
Synchronous digital hierarchy (SDH, Synchronous Digital Hierarchy) be at PDH (Pseudo-synchronous Digital Hierarchy) (PDH, Plesiochronous Digital Hierarchy) a kind of digital transmission technology system that grows up on the basis, Synchronous Optical Network (SONET, Synchronous Optical Network) is the transmission standard that the U.S. adopts.According to International Telecommunication Union-Telecommunication Standardization Sector (ITU-T, International TelecommunicationsUnion-Telecommunications Standardization Sector) G.813, G.703 suggestion, GR253 R5, the requirement of GR1244 R4 standard, SDH/SONET equipment clock index mainly comprises following projects: frequency accuracy, traction is gone into and pull-out range, noise produces, drift under the locking mode, output jitter, noise margin, the drift tolerance limit, jitter toleration, noise transmission, transient response and maintenance performance, the response of short-term phase transient, long-term phase transient response, Bit/Hz electrical interface index etc.
Generally speaking, in the research and development of products stage, all should carry out assessment test to above index; In the product lot quantity delivery stage, focus on the test products function, test event can be reduced to following several: frequency accuracy, traction go into pull-out range, Bit pattern under expense test etc., other project is treated as the project of taking a sample test.
At the above test event of simplifying, it is more to build the required instrument kind of SDH/SONET external clock testing equipment, as frequency meter, high precision clock source and E1/DS1 protocol analyzer etc.Briefly carry out exemplary illustration below.
One, the frequency accuracy index request of test SDH/SONET equipment external clock under free-run mode: long-term (30 days) clock frequency accuracy should be better than ± 4.6ppm.
The test schematic diagram as shown in Figure 1.
Test process: the clock source of SDH/SONET network element is configured to inner self-oscillation clock source, and the frequency accuracy with the long-time testing network element output of calibrated frequency meter clock is the frequency accuracy under the free-run mode.
Two, the frequency accuracy of test SDH/SONET equipment external clock under locking and maintenance working method
Index request: the clock frequency accuracy should be better than ± 0.37ppm.
The test schematic diagram as shown in Figure 2.
Test process: Closing Switch K, the Bit clock that network element clock lock SDH/SONET analyzer is exported, the frequency accuracy with the long-time testing network element output of calibrated frequency meter clock is the frequency accuracy under the locking working method; Then, cut-off switch K makes the Bit clock of network element clock disengaging SDH/SONET analyzer output and enters the maintenance pattern, and the frequency accuracy with the long-time testing network element output of calibrated frequency meter clock is the frequency accuracy that keeps under the working method.
Three, the traction of test SDH/SONET equipment external clock is gone into and pull-out range
Index request: the traction of clock go into pull-out range all should be beyond ± 4.6ppm.
The test schematic diagram as shown in Figure 3.
Test process: the Bit clock with the output of SDH/SONET analyzer is a reference clock, and this reference clock of network element clock lock is set, and reads in the frequency accuracy of network element output clock under the locking working method by frequency meter.At this moment, testing network element is exported the pull-out range of clock like this: the frequency of regulating reference clock, its plus or minus frequency deviation with respect to nominal frequency is slowly strengthened, and when regulating, monitor the frequency accuracy that network element is exported clock by frequency meter, until finding such frequency, promptly exceeding this frequency network element clock will losing lock (whether losing lock is by judging whether the frequency accuracy that reads exceeds index request and determines on frequency meter for the network element clock); Then, regulate the frequency of reference clock again, it is slowly strengthened with respect to the frequency deviation of nominal frequency on other direction, and when regulating, export the frequency accuracy of clock by frequency meter monitoring network element, until finding another such frequency, promptly exceeding this frequency network element clock will losing lock.Can determine pull-out range according to these two critical frequencies.The pull-in range of testing network element clock like this: under the free-run mode that the plus or minus frequency deviation because of reference clock causes greatly, progressively turn this frequency deviation down, and when regulating, monitor the frequency accuracy that network element is exported clock by frequency meter, until reaching a frequency that makes the network element clock can just lock reference clock; Then, again because of reference clock under the free-run mode that the frequency deviation on the other direction causes greatly, progressively turn this frequency deviation down, and when regulating, monitor the frequency accuracy that network element is exported clock by frequency meter, make the network element clock can just lock the frequency of reference clock until reaching another.Can determine pull-in range according to these two critical frequencies.
For above-mentioned test, there is following defective:
1. owing to adopt frequency meter to carry out frequency test, only covered the external clock test of Hz pattern, there have been test leakage in the clock of Bit pattern and S1 overhead byte thereof etc.;
2. need to use instrument such as SDH/SONET analyzer, frequency marking (rubidium clock, caesium clock), frequency meter, testing cost height;
3. because test is not only carried out at its phase place at the frequency of equipment clock, can not detect situations such as the excessive or frequent saltus step of phase difference between network element output clock and the reference clock, may whether lock reference clock to network element and cause erroneous judgement.
Summary of the invention
The purpose of this invention is to provide the SDH/SONET equipment external clock testing equipment that a kind of SDH/SONET equipment external clock test that can cover the Bit pattern also can reduce cost.
According to the present invention, a kind of SDH/SONET equipment external clock testing equipment is provided, comprising:
Clock generating device is used to produce reference clock;
The E1/DS1 line interface unit is used for converting tested SDH/SONET equipment B it external clock to the Hz clock, and exports this Hz clock as measured signal; With,
Sub-testing apparatus, comprise synchronizer, counting device and calculation element, its neutron testing apparatus receives measured signal, it is synchronous that synchronizer is used for measured signal and reference clock that sub-testing apparatus is received, counting device is used to utilize reference clock to the measured signal counting after synchronous, and calculation element is used for calculating based on count results.
Preferably, SDH/SONET equipment external clock testing equipment also comprises and is used to receive tested SDH/SONET equipment Hz external clock and the tested Hz external clock interface arrangement of this tested SDH/SONET equipment Hz external clock as measured signal is provided.
Preferably, SDH/SONET equipment external clock testing equipment also comprises the reference clock generator that produces the Hz reference clock based on reference clock, so that provide reference clock to tested SDH/SONET equipment.
Preferably, SDH/SONET equipment external clock testing equipment also comprises and is used for the Hz reference clock is offered the Hz reference clock output device of tested SDH/SONET equipment as the reference clock.
Further preferably, SDH/SONET equipment external clock testing equipment also comprises and is used for the Hz reference clock being converted to the E1/DS1 framer of Bit reference clock and being used for this Bit reference clock is offered the Bit reference clock output device of tested SDH/SONET equipment as the reference clock.
Preferably, sub-testing apparatus also comprises the lowering freqyency device that is used for measured signal frequency reducing that it is received.
Preferably, SDH/SONET equipment external clock testing equipment also comprises phase difference detection and quantization device, for the tested SDH/SONET equipment that is operated under locking or the maintenance working method, phase difference detection and quantization device are used to detect tested SDH/SONET equipment Hz external clock or the Hz clock that is converted to by tested SDH/SONET equipment B it external clock and the phase difference between the described Hz reference clock, quantize described phase difference, and provide phase difference after the quantification as measured signal.
Preferably, phase difference detection and quantization device also comprise lowering freqyency device, are used for described tested SDH/SONET equipment Hz external clock or the Hz clock and the frequency reducing of described Hz reference clock that are converted to by tested SDH/SONET equipment B it external clock.
Preferably, clock generating device comprises:
Frequency marking is used to produce the clock signal with a frequency;
Clock raising frequency circuit is used to promote the frequency of described clock signal; With,
The Direct Digital synthetic circuit is used for producing reference clock based on the clock signal behind the raising frequency.
The beneficial effect that the present invention brings is:
1. can cover the test to the clock and the S1 overhead byte thereof of Bit pattern, no test leakage when reducing testing cost, can be finished some conventional index tests of SDH/SONET equipment external clock, and as integration apparatus, easy to carry;
2. by preferred disposition, can provide the function of test external clock, can cover test comprehensively, avoid erroneous judgement lock-out state to SDH/SONET equipment external clock phase-locked loop performance with respect to the phase difference stability of reference clock.
The accompanying drawing summary
Only by way of example, the preferred embodiments of the invention are described in more detail with reference to accompanying drawing, wherein:
Fig. 1 is that the frequency accuracy of SDH/SONET equipment Hz external clock under free-run mode of prior art is tested schematic diagram;
Fig. 2 is that the frequency accuracy of SDH/SONET equipment Hz external clock under locking and maintenance working method of prior art is tested schematic diagram;
Fig. 3 is that the traction of the SDH/SONET equipment Hz external clock of prior art is gone into and pull-out range test schematic diagram;
Fig. 4 is the block diagram of SDH/SONET equipment external clock testing equipment according to a preferred embodiment of the invention;
Fig. 5 tests schematic diagram according to the frequency accuracy of SDH/SONET equipment Hz external clock under free-run mode of the preferred embodiments of the invention;
Fig. 6 is the schematic diagram of the operation of test circuit among diagram Fig. 5;
Fig. 7 tests schematic diagram according to the frequency accuracy of SDH/SONET equipment B it external clock under free-run mode of the preferred embodiments of the invention;
Fig. 8 be according to the preferred embodiments of the invention in locking and keep the frequency accuracy of SDH/SONET equipment Hz external clock under the working method and SDH/SONET equipment Hz external clock differs stability, traction and goes into/the test schematic diagram of pull-out range;
Fig. 9 tests schematic diagram according to the frequency accuracy of SDH/SONET equipment B it external clock under locking and maintenance working method of the preferred embodiments of the invention;
Figure 10 is the schematic diagram of the operation when test circuit differs stability test among diagram Fig. 8; With,
Figure 11 is that test circuit differs the schematic diagram that quantizes and count among diagram Fig. 8 when test differs stability.
Embodiment
With reference to Fig. 4, SDH/SONET equipment external clock testing equipment according to a preferred embodiment of the invention comprises frequency marking 1, clock raising frequency circuit 2, Direct Digital synthetic circuit (DDS, Direct Digital Synthesis) 3, test circuit 5, Hz clock protection circuit 6, remove direct current shaping circuit 7, Hz clock protection circuit 8, differential drive circuit 9, Bit clock protection circuit 10, remove direct current shaping circuit 11, E1/DS1 line interface unit (LIU, LineInterface Unit) and framer (Framer) 12 and Bit clock protection circuit 13.
Frequency marking 1 can be a constant-temperature crystal oscillator, is used for exporting as required the clock signal of corresponding frequencies to clock raising frequency circuit 2.Clock raising frequency circuit 2 promotes the signal frequency from frequency marking 1 by special-purpose phase-locked loop, makes the clock behind the raising frequency satisfy the input threshold requirement of DDS, and provides it to DDS3.DDS3 is used for the clock according to the synthetic assigned frequency of DDS principle, and provides it to test circuit 5.Hz clock protection circuit 6 and 8 is provided for being connected the Hz clock interface of equipment under test (DUT, Device Under Test), and realizes the protection to warm swap.Go direct current shaping circuit 7 to be connected to Hz clock protection circuit 6, be used for removing DC component from the Hz clock signal of equipment under test.Differential drive circuit 9 is connected to test circuit 5 and Hz clock protection circuit 8, be used for receiving reference clock signal from test circuit 5, and this reference clock signal being delivered to Hz clock protection circuit 8 to strengthen the antijamming capability of this reference clock signal with differential mode, this reference clock signal is provided for equipment under test via Hz clock protection circuit 8 then.Bit clock protection circuit 10 and 13 is provided for being connected the Bit clock interface of equipment under test, and realizes the protection to warm swap.Go direct current shaping circuit 11 to be connected to Bit clock protection circuit 10 and E1/DS1 line interface unit and framer 12, be used for removing DC component, and provide it to E1/DS1 line interface unit and framer 12 from the Bit clock signal of equipment under test.E1/DS1 line interface unit and framer 12 are used for the Bit clock of 2.048Mbit/s/1.544Mbit/s is converted to the Hz clock of 2.048MHz/1.544MHz and converts the Hz clock of 2.048MHz/1.544MHz the Bit clock of 2.048Mbit/s/1.544Mbit/s to, and correspondingly finish the extraction or the insertion of S1 byte.In Fig. 4, E1/DS1 line interface unit and framer 12 are also connected to test circuit 5 and Bit clock protection circuit 13, offer test circuit 5 after being used on the one hand converting Bit clock signal to the Hz clock signal, S1 byte is extracted offer test circuit 5 simultaneously from equipment under test; Be used on the other hand receiving reference clock signal, and convert thereof into the Bit clock signal after offer equipment under test by Bit clock protection circuit 13 from test circuit 5.Test circuit 5 is used for frequency, phase place at measured clock etc. to be tested, and is described in detail below.
One, the frequency accuracy of test SDH/SONET equipment external clock under free-run mode
1. for the Hz clock
With reference to Fig. 5 and Fig. 6.As shown in Figure 5, tested SDH/SONET network element is connected to Hz clock protection circuit 6, network element is set is operated under the free-run mode.The clock signal of tested element output is protected and is isolated and after going direct current shaping circuit 7 to go direct current shaping operation, enter test circuit 5 through Hz clock protection circuit 6; The clock signal of frequency marking 1 output enters DDS3 and carries out frequency synthesis behind clock raising frequency circuit 2 raising frequencies, produces the reference clock signal of assigned frequency thus, and this reference clock signal is provided for test circuit 5.Need to prove, the frequency of synthetic reference clock signal should be recently from the high several times of clock frequency of tested element.Like this, can in test circuit 5, test.As shown in Figure 6,5 pairs of measured clock signals of test circuit carry out down conversion process, then measured clock signal after the frequency reducing and reference clock signal are carried out Synchronous Processing, utilize reference clock signal to the measured clock signal-count after synchronous again, calculate the frequency accuracy of measured clock at last according to count results.
So-called counting is meant that logic statistics measured clock signal is the rising edge of the high frequency standard clock of DDS3 output and/or the frequency of trailing edge in the period of high level in the single cycle.The nominal frequency of supposing the measured clock signal is 2.048MHz, and frequency reaches 1Hz after the frequency reducing, and hypothesis the frequency of synthetic reference clock signal be 40MHz.With measured clock signal and reference clock signal synchronously after, certain rising edge or the trailing edge of these two clock signal waveforms will be aimed at.Can suppose that this aligning edge is certain rising edge, with this aligning edge is the reference count starting point, rising edge and/or trailing edge at the reference clock signal waveform, when being high level, the measured clock signal just count value is added 1 whenever detecting, until detecting the measured clock signal is low level, with this moment count value as count results.If only detect at rising edge, then according to assumed condition, count value should be 2*10 in the ideal case
7Just can obtain the frequency accuracy of measured clock with respect to the ratio of this ideal value by the difference of calculating actual count value that test obtains and this ideal value.
Be understood that easily the purpose of carrying out above-mentioned down conversion process at measured clock is to improve certainty of measurement, thereby is not essential.
In above-mentioned counting process, according to specific requirement, can be only at rising edge or only detect and count at trailing edge, also can carry out bilaterally along counting, the latter can improve resolution.
2. for the Bit clock
With reference to Fig. 7, tested SDH/SONET network element is connected to Bit clock protection circuit 10, network element is set is operated under the free-run mode.The clock signal of tested element output is protected and is isolated and after going direct current shaping circuit 11 to go direct current shaping operation, enter E1/DS1 line interface unit and framer 12 through Bit clock protection circuit 10.E1/DS1 line interface unit and framer 12 will offer test circuit 5 after will converting the Hz clock to from the Bit clock of equipment under test, and the S1 byte that extracts the Bit clock simultaneously offers test circuit 5 so that test circuit 5 is learned information such as measured clock quality of signals grade.Other process and the operation of carrying out in test circuit 5 can no longer be described in detail here with reference to the top description of being carried out at the frequency accuracy test of Hz clock.
Two, the frequency accuracy of test SDH/SONET equipment external clock under locking and maintenance working method
1. for the Hz clock
With reference to Fig. 8, tested SDH/SONET network element is connected to Hz clock protection circuit 6 and 8.The high frequency standard frequency division of the frequency that 5 pairs of test circuits receive from DDS3 to be obtaining a reference clock signal, and exports this reference clock signal to differential drive circuit 9.Differential drive circuit 9 exports this reference clock signal to Hz clock protection circuit 8 with differential mode.Hz clock protection circuit 8 is exported to tested SDH/SONET network element with this reference clock signal then, so that tested element locks this reference clock.The clock of tested element output is via Hz clock protection circuit 6 and go direct current shaping circuit 7 to be provided for test circuit 5.Like this, can test in test circuit 5, the operation of carrying out in test circuit 5 during Hz clock frequency accuracy under the free-run mode of detailed process and test is identical.Thus, can obtain the frequency accuracy of SDH/SONET equipment external clock under the locking mode.
Then, under locking mode, disconnect the reference clock that offers tested element, network element is operated under the hold mode.Then, can test in test circuit 5, the operation of carrying out in test circuit 5 during Hz clock frequency accuracy under the free-run mode of detailed process and test is identical.Thus, can the be maintained frequency accuracy of SDH/SONET equipment external clock under the pattern.
2. for the Bit clock
With reference to Fig. 9, tested SDH/SONET network element is connected to Hz clock protection circuit 10 and 13.The high frequency standard frequency division of the frequency that 5 pairs of test circuits receive from DDS3 to be obtaining a reference clock signal, and exports this reference clock to E1/DS1 line interface unit and framer 12.E1/DS1 line interface unit and framer 12 provide it to tested SDH/SONET network element via Bit clock protection circuit 13 after converting this reference clock to the Bit clock, so that tested element locks this reference clock.The clock of tested element output is via Bit clock protection circuit 10 and go direct current shaping circuit 11 to be provided for E1/DS1 line interface unit and framer 12, and offers test circuit 5 after converting the Hz clock to by E1/DS1 line interface unit and framer 12.Like this, can test in test circuit 5, the operation of carrying out in test circuit 5 during Bit clock frequency accuracy under the free-run mode of detailed process and test is identical.Thus, can obtain the frequency accuracy of SDH/SONET equipment external clock under the locking mode.
Then, under locking mode, disconnect the reference clock that offers tested element, network element is operated under the hold mode.Then, can test in test circuit 5, the operation of carrying out in test circuit 5 during Hz clock frequency accuracy under the free-run mode of detailed process and test is identical.Thus, can the be maintained frequency accuracy of SDH/SONET equipment external clock under the pattern.
Three, the phase difference stability of test SDH/SONET equipment external clock
With the Hz clock is example.With reference to Fig. 8,5 pairs of high frequency standard clocks that receive from DDS3 of test circuit carry out frequency division to obtain a reference clock signal, via differential drive circuit 9 and Hz clock protection circuit 8 this reference clock is exported to tested SDH/SONET network element then, so that tested element locks this reference clock.Tested element is via Hz clock protection circuit 6 and go direct current shaping circuit 7 that the clock of its output is offered test circuit 5.Like this, can in test circuit 5, differ stability test, carry out brief description below.
With reference to Figure 10, test circuit 5 will carry out down conversion process from the measured clock signal and the reference clock signal of tested element, detect the phase difference of these two clock signals and phase difference is carried out quantification treatment to obtain quantizing to differ (shown in Figure 11), carry out Synchronous Processing (shown in Figure 11) with quantizing to differ the high frequency standard clock that is synthesized with DDS3, carry out monolateral edge or bilateral with reference clock to quantizing to differ then, can calculate the phase difference stability indicator of SDH/SONET equipment external clock at last according to count results along counting (shown in Figure 11).
So-called counting is meant that it is the rising edge of the high frequency standard clock of DDS3 output in period of 1 and/or the frequency of trailing edge that the logic statistic quantification differed in the single cycle, and detailed process can be with reference to the relevant description of front.
Phase difference stability test about the Bit clock is not described in detail here.
Four, the traction of test SDH/SONET equipment external clock is gone into and pull-out range
With the Hz clock is example.Refer again to Fig. 8, tested SDH/SONET network element is connected to Hz clock protection circuit 6 and 8.5 pairs of high frequency standard clocks that receive from DDS3 of test circuit carry out frequency division to obtain a reference clock signal, via differential drive circuit 9 and Hz clock protection circuit 8 this reference clock is exported to tested SDH/SONET network element then, so that tested element locks this reference clock.Tested element is via Hz clock protection circuit 6 and go direct current shaping circuit 7 that the clock of its output is offered test circuit 5.
The pull-out range of testing network element clock like this: the frequency of regulating the reference clock of DDS3 output, make the reference clock of test circuit 5 outputs have certain plus or minus frequency deviation with respect to nominal frequency, this frequency deviation is slowly strengthened, and it is stable by test circuit 5 monitoring measured clocks when regulating with respect to differing of reference clock, until finding such frequency, whether promptly surpassing this frequency network element clock will losing lock (network element clock losing lock differ stability by judgement whether exceed index request and determine); Then, regulate the frequency of the reference clock of DDS3 output again, the reference clock that makes test circuit 5 output has frequency deviation on the other direction with respect to nominal frequency, this frequency deviation is slowly strengthened, and it is stable by test circuit 5 monitoring measured clocks when regulating with respect to differing of reference clock, until finding another such frequency, promptly exceeding this frequency network element clock will losing lock.Can determine pull-out range according to these two critical frequencies.
The pull-in range of testing network element clock like this: under the free-run mode that the plus or minus frequency deviation because of the reference clock of test circuit 5 outputs causes greatly, the frequency of the reference clock by regulating DDS3 output is progressively turned this frequency deviation down, and stable by test circuit 5 monitoring measured clocks when regulating with respect to differing of reference clock, until reaching a frequency that makes network element can just lock reference clock (differ stability and can just satisfy index request this moment); Then, again because of reference clock under the free-run mode that the frequency deviation on the other direction causes greatly, the frequency of the reference clock by regulating DDS3 output is progressively turned this frequency deviation down, and stable by test circuit 5 monitoring measured clocks when regulating with respect to differing of reference clock, make the network element clock can just lock the frequency of reference clock until reaching another.Can determine pull-in range according to these two critical frequencies.
Go into test with pull-out range about the traction of Bit clock, no longer describe in detail here.
The traction of mentioning is in the above gone in the test process with pull-out range, by judging tested SDH/SONET network element clock differing stability and whether exceed index request and determine whether losing lock of network element clock with respect to reference clock; But be apparent that whether whether losing lock also can exceed index request to the network element clock in conjunction with the frequency accuracy of tested SDH/SONET network element clock determines.In addition, in the superincumbent description, test circuit 5 will be by obtaining reference clock signal from the high frequency standard clock division that DDS3 receives; But those of ordinary skill in the art should be appreciated that can also be by other prior art, based on the high frequency standard clock generating reference clock signal that receives from DDS3.In addition, with reference to the accompanying drawings with top description, reference clock produces in test circuit 5; But those of ordinary skill in the art should be appreciated that the device that produces reference clock and also can be not included in the test circuit 5.
Although described the preferred embodiments of the invention, by reading and grasping principle of the present invention and instruction, those skilled in the art can carry out various remodeling to embodiment disclosed herein.For example, in preferred embodiment shown in Figure 4, reference clock utilizes frequency marking, clock raising frequency circuit and Direct Digital synthetic circuit to produce, but also can utilize other clock generating device of prior art to produce.In addition, the tested SDH/SONET equipment Hz external clock among Fig. 4 is via Hz clock protection circuit and go the direct current shaping circuit to enter test circuit, also is possible but tested SDH/SONET equipment Hz external clock enters test circuit via the interface circuit of other form; For tested SDH/SONET equipment B it external clock, situation is similar.Therefore, being intended to scope of the present invention is limited by the claim that is attached to here.
Claims (10)
1. SDH/SONET equipment external clock testing equipment comprises:
Clock generating device is used to produce reference clock;
The E1/DS1 line interface unit is used for converting tested SDH/SONET equipment B it external clock to the Hz clock, and exports this Hz clock as measured signal; With,
Sub-testing apparatus, comprise synchronizer, counting device and calculation element, its neutron testing apparatus receives measured signal, it is synchronous that synchronizer is used for measured signal and reference clock that sub-testing apparatus is received, counting device is used to utilize reference clock to the measured signal counting after synchronous, and calculation element is used for calculating based on count results.
2. testing equipment as claimed in claim 1 is characterized in that, also comprises being used to receive tested SDH/SONET equipment Hz external clock and the tested Hz external clock interface arrangement of this tested SDH/SONET equipment Hz external clock as measured signal being provided.
3. testing equipment as claimed in claim 2 is characterized in that, also comprises the reference clock generator that produces the Hz reference clock based on reference clock, so that provide reference clock to tested SDH/SONET equipment.
4. testing equipment as claimed in claim 3 is characterized in that, also comprises being used for described Hz reference clock is offered the Hz reference clock output device of tested SDH/SONET equipment as the reference clock.
5. testing equipment as claimed in claim 3, it is characterized in that, also comprise and be used for described Hz reference clock being converted to the E1/DS1 framer of Bit reference clock and being used for this Bit reference clock is offered the Bit reference clock output device of tested SDH/SONET equipment as the reference clock.
6. as claim 4 or 5 described testing equipments, it is characterized in that tested SDH/SONET equipment work is under locking or maintenance working method.
7. as the described testing equipment of arbitrary claim among the claim 1-5, it is characterized in that described sub-testing apparatus also comprises the lowering freqyency device that is used for measured signal frequency reducing that it is received.
8. testing equipment as claimed in claim 6, it is characterized in that, also comprise phase difference detection and quantization device, Hz clock that is used to detect tested SDH/SONET equipment Hz external clock or is converted to by tested SDH/SONET equipment B it external clock and the phase difference between the described Hz reference clock, quantize described phase difference, and provide phase difference after the quantification as measured signal.
9. testing equipment as claimed in claim 8, it is characterized in that, described phase difference detection and quantization device also comprise lowering freqyency device, are used for described tested SDH/SONET equipment Hz external clock or the Hz clock and the frequency reducing of described Hz reference clock that are converted to by tested SDH/SONET equipment B it external clock.
10. testing equipment as claimed in claim 1 is characterized in that, described clock generating device comprises:
Frequency marking is used to produce the clock signal with a frequency;
Clock raising frequency circuit is used to promote the frequency of described clock signal; With,
The Direct Digital synthetic circuit is used for producing reference clock based on the clock signal behind the raising frequency.
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| CN101257361B (en) * | 2008-04-03 | 2011-05-11 | 中兴通讯股份有限公司 | Method and net element for performing accurate time transmission through synchronous digital system network |
| CN102546303A (en) * | 2012-01-18 | 2012-07-04 | 瑞斯康达科技发展股份有限公司 | System and method for testing clock capability of SDH (synchronous digital hierarchy) device |
| CN102571236A (en) * | 2011-12-29 | 2012-07-11 | 中兴通讯股份有限公司 | Method and system for measuring maximum time interval error |
| CN104678291A (en) * | 2015-02-10 | 2015-06-03 | 电信科学技术第五研究所 | Automatic performance test platform for digital synchronization network node clock devices |
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| CN103581943A (en) * | 2012-08-01 | 2014-02-12 | 中国移动通信集团公司 | Clock synchronization testing method and system for wireless access system |
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| KR100192775B1 (en) * | 1995-12-30 | 1999-06-15 | 유기범 | Apparatus for checking a clock |
| CN1213377C (en) * | 2002-08-05 | 2005-08-03 | 华为技术有限公司 | Device and method for detecting long term frequency stability of clock |
| CN100438361C (en) * | 2003-08-01 | 2008-11-26 | 华为技术有限公司 | Method for controlling master spare clock phase for synchronous digital system equipment |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101257361B (en) * | 2008-04-03 | 2011-05-11 | 中兴通讯股份有限公司 | Method and net element for performing accurate time transmission through synchronous digital system network |
| CN102571236A (en) * | 2011-12-29 | 2012-07-11 | 中兴通讯股份有限公司 | Method and system for measuring maximum time interval error |
| CN102571236B (en) * | 2011-12-29 | 2014-07-16 | 中兴通讯股份有限公司 | Method and system for measuring maximum time interval error |
| CN102546303A (en) * | 2012-01-18 | 2012-07-04 | 瑞斯康达科技发展股份有限公司 | System and method for testing clock capability of SDH (synchronous digital hierarchy) device |
| CN102546303B (en) * | 2012-01-18 | 2015-05-20 | 瑞斯康达科技发展股份有限公司 | System and method for testing clock capability of SDH (synchronous digital hierarchy) device |
| CN104678291A (en) * | 2015-02-10 | 2015-06-03 | 电信科学技术第五研究所 | Automatic performance test platform for digital synchronization network node clock devices |
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