CN1983544A - Manufacturing method for semiconductor device - Google Patents
Manufacturing method for semiconductor device Download PDFInfo
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- CN1983544A CN1983544A CNA2007100017248A CN200710001724A CN1983544A CN 1983544 A CN1983544 A CN 1983544A CN A2007100017248 A CNA2007100017248 A CN A2007100017248A CN 200710001724 A CN200710001724 A CN 200710001724A CN 1983544 A CN1983544 A CN 1983544A
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- metal bump
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
- H01L2224/7525—Means for applying energy, e.g. heating means
- H01L2224/75251—Means for applying energy, e.g. heating means in the lower part of the bonding apparatus, e.g. in the apparatus chuck
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
- H01L2224/7525—Means for applying energy, e.g. heating means
- H01L2224/75252—Means for applying energy, e.g. heating means in the upper part of the bonding apparatus, e.g. in the bonding head
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/0105—Tin [Sn]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01074—Tungsten [W]
Abstract
A method for manufacturing a semiconductor device by bonding a first metal bump formed on a first semiconductor substrate and a second metal bump formed on a second semiconductor substrate together. This method includes a low melting point metal layer forming step for forming a layer of a low melting point metal on a top portion of at least either of the first metal bump and the second metal bump, a substrate temperature controlling step for controlling, with the first semiconductor substrate and the second semiconductor substrate being separated from each other, the temperature of the first semiconductor substrate to a first temperature higher than the solidus temperature of the low melting point metal and controlling the temperature of the second semiconductor substrate to a second temperature lower than the solidus temperature of the low melting point metal, a metal bump approaching step for bringing the first metal bump and second metal bump close to each other after the substrate temperature controlling step, and a step for controlling, after the metal bump approaching step, the temperatures of the first semiconductor substrate and the second semiconductor substrate to a temperature lower than the solidus temperature of the low melting point metal.
Description
The application is an application number: 03152509.1, the applying date: on August 1st, 2003, denomination of invention: the dividing an application of the application for a patent for invention of " manufacture method of semiconductor device ".
Technical field
The present invention relates on semiconductor chip, to have engaged the manufacture method of the semiconductor device with chip base chip structure of other semiconductor chip.
Background technology
As a form of so-called multi-chip semiconductor device with high withstand voltage, there is the chip base chip structure of overlapping a plurality of semiconductor chips.In the semiconductor device of chip base chip structure, at the surface engagement sub-chip littler that is connecting outside master chip than this master chip.Sometimes at a plurality of sub-chips of the surface engagement of a master chip.
Master chip and sub-chip have a plurality of metal bump (bump) on the active face that has formed function element and wiring respectively.These metal bump mainly are made of gold (Au) refractory metal of etc.ing, on the both sides or a side of the metal bump of the metal bump of master chip and sub-chip, top ends form by tin low-melting-point metals such as (Sn) formation layer.
In first manufacture method in the past that is used for making semiconductor device with chip base chip structure, the active face of master chip is relative with the active face of sub-chip, and master chip and sub-chip are heated to the above temperature of fusing point (solidus temperature) of low-melting-point metal.In view of the above, be formed on the layer fusing that constitutes by low-melting-point metal of the top ends of metal bump.Then, the metal bump contraposition of the metal bump of master chip and sub-chip, near (contact), the temperature of master chip and sub-chip drops to below the fusing point of low-melting-point metal.In view of the above, low-melting-point metal solidifies, and the metal bump of master chip and the metal bump of sub-chip be by low-melting-point metal, at electricity with mechanically engage.
In addition, in second manufacture method in the past that is used for making semiconductor device with chip base chip structure, on master chip and sub-chip, acted on load, make after the metal bump of the metal bump of master chip and sub-chip pinned, master chip and sub-chip are heated to the above temperature of fusing point (solidus temperature) of low-melting-point metal.In view of the above, be formed on the layer fusing that constitutes by low-melting-point metal on the top of metal bump.Then, drop to by the temperature that makes master chip and sub-chip below the fusing point of low-melting-point metal, low-melting-point metal solidifies, and the metal bump of master chip and the metal bump of sub-chip be by low-melting-point metal, at electricity with mechanically engage.
At this moment, even be formed with oxide-film on the surface of the metal bump of the metal bump of master chip or sub-chip, the metal bump by pushing master chip and the metal bump of sub-chip are destroyed oxide-film, by low-melting-point metal, engage first and second metal bump well.
Also can carry out described joint under the wafer state before cutting out master chip.At this moment, behind the joint of semiconductor wafer and sub-chip, cut off semiconductor wafer, become the monolithic of semiconductor chip with chip base chip structure.
, in described first manufacture method, when the metal bump of the metal bump of master chip and sub-chip near the time, the low-melting-point metal of fusing is forced out between the metal bump of the metal bump of master chip and sub-chip, flows out to the side.In view of the above, under extreme case, electrical short between the adjacent metal projection.
In addition, when using semiconductor wafer to replace master chip, when engaging, on semiconductor wafer, engage the sub-chip of a large amount of (for example thousands of) by described method.Therefore, in long-time before connecting all chips, wafer or sub-chip are in the state of hyperthermia and superheating.In view of the above, the deterioration in characteristics of master chip and sub-chip.
In addition, semiconductor wafer has a plurality of (for example thousands of) is equivalent to the zone of master chip, is equivalent in the zone of master chip at all, can't push sub-chip simultaneously, and heating.Therefore, in described second manufacture method, must repeat by absorption folder by sub-number of chips, the bundle chip is transported to the given position on the semiconductor wafer, used load on one side on this sub-chip, heat up and the step of cooling on one side, so productivity is poor.
When carrying out the joint of master chip and sub-chip, must make the metal bump of master chip and the correct contraposition of metal bump of sub-chip, but owing to be accompanied by the thermal process that heats up and lower the temperature, and not normal in the device generation that is used for engaging, so can't improve the precision of contraposition.When the joint of master chip and sub-chip; when for example the group chip has electricity; when the contacting of the metal bump of the metal bump of master chip and sub-chip; be formed on function element on the master chip because from the discharge of sub-chip; and by electrostatic breakdown; for fear of such state of affairs, master chip is provided with the protection diode that is connected on the metal bump., the protection diode was unwanted originally, if the protection diode is set, then formed the area decreases of other function element.
Summary of the invention
The objective of the invention is to, the manufacture method that can engage the metal bump that is formed on first Semiconductor substrate well and be formed on the semiconductor device of the metal bump on second Semiconductor substrate is provided.
Other purposes of the present invention are, provide the characteristic of Semiconductor substrate to be difficult to the manufacture method of the semiconductor device of deterioration.
Another other purposes of the present invention are, the manufacture method of the high semiconductor device of productivity is provided.
Another other purposes of the present invention are, provide to reduce offset, can engage the manufacture method of the semiconductor device of a plurality of Semiconductor substrate.
Another other purposes of the present invention are, the manufacture method of semiconductor device of the protection diode of the electrostatic breakdown in the time of need not being provided for preventing engaging a plurality of Semiconductor substrate on Semiconductor substrate is provided.
The manufacture method of one of the present invention's semiconductor device is to engage the manufacture method that is formed on first metal bump on first Semiconductor substrate that is formed with function element and is formed on the semiconductor device of second metal bump on second Semiconductor substrate that is formed with function element.This method comprises: the low-melting-point metal layer that forms the layer that is made of low-melting-point metal in the top ends of described second metal bump forms step, wherein, do not form on the top of described first metal bump by low-melting-point metal constitute layer; Under the state that described first Semiconductor substrate and described second Semiconductor substrate are separated, first temperature that the solidus temperature that to make described first Semiconductor substrate be described low-melting-point metal is above, and the underlayer temperature set-up procedure of following second temperature of the solidus temperature that to make described second Semiconductor substrate be described low-melting-point metal; After this underlayer temperature set-up procedure, the metal bump contact procedure that described first metal bump is contacted with described low-melting-point metal; After this metal bump contact procedure, the step that the solidus temperature that to make described first Semiconductor substrate and described second Semiconductor substrate be described low-melting-point metal is following.
According to the present invention, for example, when on first metal bump, being formed with the layer that constitutes by low-melting-point metal, in the underlayer temperature set-up procedure, produce the fusing fluid of the layer that constitutes by this low-melting-point metal.And in the underlayer temperature set-up procedure, second metal bump is the following temperature of solidus temperature of low-melting-point metal.By the metal bump contact procedure, if the layer that is made of this low-melting-point metal contacts with second metal bump, then Rong Hua low-melting-point metal loses heat, solidifies.When even the fusing fluid of low-melting-point metal not exclusively solidifies, because temperature descends, becoming is difficult to flow.
Therefore, the fusing fluid of low-melting-point metal can not flow out between first metal bump and second metal bump.
Then, by make first Semiconductor substrate and second Semiconductor substrate for by low-melting-point metal constitute the layer solidus temperature below step, the fusing fluid of low-melting-point metal solidifies, first metal bump and second metal bump layer by being made of low-melting-point metal is at electricity with mechanically engage.
When the both sides in the top ends of the top ends of first metal bump and second metal bump are formed with the layer that is made of low-melting-point metal, also be same.
The form of Semiconductor substrate for example maybe can be used to cut out the semiconductor wafer of semiconductor chip for semiconductor chip (master chip, sub-chip).Metal bump for example can be made of gold, the alloy that the layer that is made of low-melting-point metal for example can be tin, be made of tin-lead, the alloy that is made of tin-silver-copper, is made of the scolding tin of indium etc.Second temperature can be a room temperature.
The temperature difference of first temperature and second temperature obtains above-mentioned effect greatly to a certain degree the time easily.Therefore, the temperature difference of first temperature and second temperature for example can be for more than 100 ℃.In addition, the temperature difference of first temperature and second temperature also can be for more than 200 ℃.
Described underlayer temperature set-up procedure can comprise: make the almost relative configuration step of the relative up and down configuration of level of described first Semiconductor substrate and described second Semiconductor substrate.
By relative configuration step, make first Semiconductor substrate and almost maintenance level of second Semiconductor substrate, relative up and down.First Semiconductor substrate and second Semiconductor substrate can keep this state and contact in the metal bump contact procedure.At this moment the fusing fluid of low-melting-point metal is clipped from above-below direction by first metal bump and second metal bump.Therefore, the fusing fluid of low-melting-point metal is difficult to flow out between first metal bump and second metal bump.
The layer that is made of described low-melting-point metal is formed on the top ends of described second metal bump, can not be formed on the top ends of described first metal bump.
According to this structure, in the underlayer temperature set-up procedure, because second Semiconductor substrate is below the solidus temperature of low-melting-point metal, so the layer that is made of low-melting-point metal does not melt.And first metal bump is in the underlayer temperature set-up procedure, more than the solidus temperature for low-melting-point metal.And, by the metal bump contact procedure, if first metal bump contact form on second metal bump by low-melting-point metal constitute the layer, then provide heat near the layer that constitutes by low-melting-point metal of first metal bump contact site, temperature becomes more than the solidus temperature of low-melting-point metal, produces fusing fluid.
Then, by make first Semiconductor substrate and second Semiconductor substrate for by low-melting-point metal constitute the layer solidus temperature below step, the fusing fluid of low-melting-point metal solidifies, first metal bump and second metal bump layer by being made of low-melting-point metal is at electricity with mechanically engage.
At this moment, by the metal bump contact procedure, in the low-melting-point metal layer on second metal bump, have only the part and near the fusing it of the contact of first metal bump.Therefore, the fusing fluid of low-melting-point metal can not flow out between first metal bump and second metal bump.Engage first metal bump and second metal bump like this, well.
It is desirable to, observe from the direction perpendicular to first and second Semiconductor substrate, first metal bump is littler than the area of second metal bump, and first metal bump is engaged to overlapping fully on second metal bump.At this moment, the contact site that occupies layer first all metal bump that is made of low-melting-point metal reduces, and it is remarkable that described effect becomes.
Described first Semiconductor substrate can be a semiconductor chip, and at this moment, described second Semiconductor substrate can be a semiconductor wafer.
Semiconductor wafer can comprise and a plurality of (for example thousands of) zone that semiconductor chip is corresponding.
According to this structure, can on semiconductor wafer, carry out the joint of semiconductor chip.In the underlayer temperature set-up procedure, the semiconductor wafer of second Semiconductor substrate is that second temperature is the following low temperature of fusing point of low-melting-point metal.Therefore, for example thousands of semiconductor chips are bonded on the semiconductor wafer required long-time in, even semiconductor wafer is second temperature, the characteristic of semiconductor wafer also is difficult to deterioration.
After having engaged whole semiconductor chips on the semiconductor wafer, can cut out semiconductor chip from semiconductor wafer.In view of the above, obtain first and second semiconductor chips with chip base chip structure.In the manufacture method of such semiconductor device, be the joint that wafer-level carries out semiconductor chip at a side semiconductor chip, so productivity is good.
The manufacture method of the present invention's two semiconductor device is the manufacture method that engages the semiconductor device that lip-deep first metal bump of a side that is formed on first Semiconductor substrate constitutes with being formed on lip-deep second metal bump of a side of second Semiconductor substrate.This method comprises: the step that forms the layer that is made of low-melting-point metal on the top of at least one side in described first and second metal bump; The flux applying step of coating flux on the top of at least one side in described first and second metal bump; After this flux applying step, make the described side surface of the described side surface of described first Semiconductor substrate and described second Semiconductor substrate relative, with described flux described first metal bump and the temporary transient temporary transient fixing step of fixing of described second metal bump; After this temporary transient fixing step, described first and second Semiconductor substrate are heated to the heating steps of temperature more than the solidus temperature of the layer that constitutes by described low-melting-point metal.
According to the present invention, temporarily fix first metal bump and second metal bump by the flux of insulator.Therefore, temporary transient fixedly the time at this when a side of first and second Semiconductor substrate has electricity, can not discharge, so the function element that is formed on the opposing party's Semiconductor substrate electrostatic breakdown can not take place yet.The protection diode of the electrostatic breakdown in the time of therefore, on first and second Semiconductor substrate, need not being provided for preventing these joints.
After temporary transient fixing, be more than the solidus temperature of low-melting-point metal by making first and second Semiconductor substrate, produce the fusing fluid of low-melting-point metal.Then, be below the solidus temperature of low-melting-point metal by making first and second Semiconductor substrate, first metal bump and second metal bump layer by low-melting-point metal is at electricity and joint mechanically.At this moment, even when being formed with oxide-film on the surface of first metal bump or second metal bump, because the effect of flux, oxide-film is removed, and the fusing fluid of low-melting-point metal can have good soakage for first and second metal bump.Therefore, the layer by low-melting-point metal engages first and second metal bump well.
First and second metal bump for example can be made of gold, and the layer that is made of low-melting-point metal for example can be made of tin.
Can not add under the no-load condition in fact of the load of pushing them for described first and second Semiconductor substrate, carry out described heating steps.
According to this structure, substantially under the no-load condition, for example, the opposing party's Semiconductor substrate side thereon, heat the method, semiconductor substrate horizontal positioned in first and second Semiconductor substrate.Under this state, in first and second Semiconductor substrate, the Semiconductor substrate of top is only pushed down the Semiconductor substrate of below with deadweight, rather than will force together forcibly each other by external loading, so can relatively move.Therefore, by temporary transient fixing step, first metal bump and second metal bump are staggered a little, temporary transient fixedly the time, if produce the fusing fluid of low-melting-point metal by heating steps, then because the surface tension of the fusing fluid of low-melting-point metal, first metal bump and second metal bump move (alignment certainly), and skew diminishes.In view of the above, offset be can reduce, first Semiconductor substrate and second Semiconductor substrate engaged.
In addition, can be omitted in the step of used load on first and second Semiconductor substrate, so productivity is good.
Described temporary transient fixing step can comprise: the step of fixing a plurality of described first Semiconductor substrate on a described side surface of described second Semiconductor substrate.
According to this structure, behind the state that a plurality of first Semiconductor substrate temporarily is fixed on second Semiconductor substrate, can unify heating first and second Semiconductor substrate.Promptly need not repeat to heat up and cooling by sub-chip-count.In view of the above, can unify to engage second Semiconductor substrate and a plurality of first Semiconductor substrate, so productivity is good.
First Semiconductor substrate for example can be a semiconductor chip, and second Semiconductor substrate for example can be a semiconductor wafer.At this moment, behind the joint, cut off Semiconductor substrate, can cut out the monolithic of semiconductor chip with chip base chip structure.
By the following embodiment that illustrates with reference to accompanying drawing, above-mentioned or other purposes, feature and effect of the present invention become clear.
Description of drawings
Fig. 1 is the graphic front view of the semiconductor device obtained of the manufacture method by embodiment of the present invention 1.
Fig. 2 (a), Fig. 2 (b) and Fig. 2 (c) are the diagram front views of manufacture method that is used for the semiconductor device of key diagram 1.
Fig. 3 (a), Fig. 3 (b) have amplified near the cutaway view of obtaining the metal bump of Fig. 2 (a), Fig. 2 (b).
Fig. 4 is the graphic front view of the semiconductor device obtained of the manufacture method by embodiment of the present invention 2.
Fig. 5 (a), Fig. 5 (b) and Fig. 5 (c) are the diagram front views of manufacture method that is used for the semiconductor device of key diagram 4.
Fig. 6 (a), Fig. 6 (b) and Fig. 6 (c) have amplified near the cutaway view of obtaining the metal bump of Fig. 5 (a), Fig. 5 (b) and Fig. 5 (c).
Embodiment
Fig. 1 is the graphic front view of the semiconductor device obtained of the manufacture method by embodiment of the present invention 1.
This semiconductor device has: overlappingly engaged sub-chip 2 as first Semiconductor substrate, sub-chip 3 and as so-called chip base chip (Chip-On-Chip) structure of the master chip 1 of second Semiconductor substrate.Sub-chip 2,3 is littler than master chip 1.
The surfaces opposite to each other of master chip 1 and sub-chip 2,3 become active face 1a, 2a, the 3a that forms function element and wiring etc. respectively.The active face 1a of master chip 1 is provided with a plurality of metal bump (bump) 4.Metal bump 4 is made of gold (Au).Near the periphery of active face 1a,, be provided with outside the taking-up with electrode 7 in the not relative part of active face 2a, 3a.
On active face 2a, the 3a of sub-chip 2,3, be provided with metal bump 5,6 in the position corresponding with metal bump 4.Metal bump 5,6 is made of gold (Au).At the thin layer (not shown) that metal bump 4 and 5,6 existence of metal bump are made of tin (Sn), metal bump 4 engages by this tin layer with metal bump 5,6.
In the side of master chip 1,, dispose the lead frame 9 that extends to the side with master chip 1 devices spaced apart.The outside taking-up with electrode 7 is connected by bonding wire 8 with lead frame 9.The zone of connecting portion that comprises master chip 1, sub-chip 2,3, bonding wire 8 and bonding wire 8 and lead frame 9 is protected by sealing resin 10 (among Fig. 1, being represented by double dot dash line).
Fig. 2 (a)～Fig. 2 (c) is the diagram front view of manufacture method that is used for the semiconductor device of key diagram 1, and Fig. 3 (a) and Fig. 3 (b) are near the cutaway views that has amplified this metal bump 4,5.Fig. 3 (a) is corresponding to Fig. 2 (a), and Fig. 3 (b) is corresponding to Fig. 2 (b).
At first, semiconductor wafer (following is called wafer) W almost flatly is placed on (Fig. 2 (a)) on the objective table 11.Wafer W comprises the corresponding unit area U (for example thousands of) (dotting the border of adjacent unit area U in Fig. 2 (a) and Fig. 2 (b)) of a plurality of and master chip 1.One side surface of wafer W becomes the active face Wa corresponding with active face 1a, forms metal bump 4 on active face Wa.The top ends of metal bump 4 almost becomes smooth face, forms layer (the tin layer) 20 (Fig. 3 (a)) that is made of tin on this face.Active face Wa is towards the top, and wafer W is placed on the objective table 11.
Be provided with heater 12 and temperature sensor 13 in the inside of objective table 11, can the wafer W that be placed on the objective table 11 be heated to fixed temperature according to the output of temperature sensor 13.
Then, sub-chip 2 has adsorbed the face of the opposite side of active face 2a by absorption folder 14, makes active face 2a towards the below, with horizontal state almost, is configured in (Fig. 2 (a)) on the wafer W.The top ends of metal bump 5 is almost smooth face.Do not form the layer that constitutes by tin on the surface of metal bump 5.In addition, the width of metal bump 5 is observed from the direction perpendicular to active face 1a, 2a than the width of metal bump 4 narrow (Fig. 3 (a)), and the area of metal bump 5 is littler than the area of metal bump 4.
Absorption folder 14 for example can pass through vacuum suction, adsorbs sub-chip 2.In the inside of absorption folder 14, near the part the face of contact shoe chip 2 is provided with heater 15 and temperature sensor 16.According to the output of temperature sensor 16,, can be heated to the sub-chip 2 that is adsorbed on the absorption folder 14 to fixed temperature by heater 15.
Then, by heater 15, bundle chip 2 is heated to first temperature T 1 than 232 ℃ also high of the fusing points of tin, by heater 12, wafer W is heated to second temperature T 2 than 232 ℃ also low of the fusing points of tin.The poor Δ T of first temperature T 1 and second temperature T 2 for example can be 100 ℃.The poor Δ T of first temperature T 1 and second temperature T 2 for example can be 200 ℃.
Under this state, metal bump 4 contrapositions of the metal bump 5 of sub-chip 2 and corresponding wafer W, absorption folder 14 descends, and metal bump 4 and metal bump 5 engage (Fig. 2 (b)).At this moment, (observe from the direction perpendicular to active face 1a, 2a) in vertical view, metal bump 4 is almost overlapping fully with metal bump 5.
At this moment, tin layer 20 becomes near the contact site more than the fusing point of tin by contacting with the metal bump 5 with first temperature T 1 higher than the fusing point of tin, fusing (among Fig. 3 (b), the melt portions of tin layer 20 having been adopted symbol 20M).Simultaneously, metal bump 5 loses heat by metal bump 4, and temperature descends.Then, sub-chip 2 separates from absorption folder 14.In view of the above, do not provide heat to sub-chip 2, the tin layer 20 of metal bump 5 or fusing loses heat rapidly from metal bump 4.
Therefore, sub-chip 2 becomes below the fusing point of tin, and the tin layer 20 of fusing solidifies.In view of the above, metal bump 4 and metal bump 5 engage on machinery and electricity.Near the fusing part of contacting metal projection 5 of 20 on tin layer is not so even metal bump 4 and metal bump 5 are near (contact), the tin layer 20 of fusing is also from flowing out between metal bump 4 and the metal bump 5.In other words, first temperature T 1 and second temperature T 2 are set to the local fully fusing of tin layer 20, and the temperature that do not flow out of the tin layer 20 of fusing.
For example, cross when low when first temperature T 1 or second temperature T 2, metal bump 5 loses heat after having contacted tin layer 20, become below the fusing point of tin, so the 20 insufficient fusing of tin layer at once.Therefore, can not obtain big bond strength between metal bump 4 and the metal bump 5.In addition, when first temperature T 1 or second temperature T 2 are too high, if metal bump 5 contact tin layers 20, then metal bump 5 become the fusing point of tin following till, provide a large amount of heat to tin layer 20, all fusings of tin layer 20 are flowed out between metal bump 4 and metal bump.
As mentioned above, in tin layer 20, near the contact site of a deposite metal projection 5, the poor Δ T of first temperature T 1 and second temperature T 2 preferably arrives certain degree greatly.Consider these factors, determine first and second temperature T 1, T2.
Then, bundle chip 3 joins on the wafer W.The metal bump 6 of sub-chip 3 is same with the metal bump 5 of sub-chip 2, and top ends becomes almost smooth, does not form the layer that is made of tin on the surface.In addition, the width of metal bump 6 is narrower than the width of metal bump 4, observes from the direction perpendicular to active face 1a, 3a, and the area of metal bump 6 is littler than the area of metal bump 4.By the method same with sub-chip 2, bundle chip 3 joins on the wafer W.
Like this, on a unit area U, obtained the wafer W of joint element chip 2,3.Equally, on all unit area U of wafer W, engaged sub-chip 2,3.
At this moment, only in the short time that is used for engaging with wafer W, the high temperature (first temperature T 1) that the fusing point that sub-chip 2,3 is a tin is above.In addition, when bundle chip 2,3 joins on all unit area U, heated chip W, but this temperature is low-melting second temperature than tin.Therefore, the characteristic of wafer W (master chip 1) and sub-chip 2,3 deterioration hardly.
Then, shown in Fig. 2 (c),,, cut out the master chip 1 that has engaged sub-chip 2,3 from wafer W by cutting off wafer W with wafer dicing saw 21 along the border of adjacent unit area U.Connected outside taking-up usefulness electrode 7 and lead frame 9 by bonding wire 8 after, die forming sealing resin 10 around master chip 1, sub-chip 2,3 etc. is obtained semiconductor device shown in Figure 1.
In the manufacture method of semiconductor device, be the joint that carries out sub-chip 2,3 under the level of wafer W at master chip 1, so productivity is good.
In the manufacture method of above semiconductor device, as long as tin layer 20 fully melts, even heated chip W (being room temperature) is impassable yet.
The tin layer can not be formed on the metal bump 4 of master chip 1, and is formed on the metal bump 5,6 of sub-chip 2,3.At this moment, be heated to first temperature T 1,20 fusing of tin layer by heater 15 bundle chips 2,3 with absorption folder 14.And, if 20 contacts of the tin layer of fusing have the metal bump 4 of second temperature T 2, then lose heat from metal bump 4, solidify at once, not from flowing out between metal bump 4 and the metal bump 5,6.When even the fusing fluid of tin layer 20 not exclusively solidifies, because temperature descends, becoming is difficult to flow.
Tin layer 20 is formed on the part of the part of metal bump 5 and metal bump 6, and, can be formed with the metal bump 4 corresponding with the metal bump 5,6 that does not form tin layer 20.
In addition, can cut off wafer W before the joint of sub-chip 2,3, the joint element chip 2,3 on master chip 1.At this moment, making master chip 1 is first temperature T 1, and sub-chip 2,3 is second temperature T 2.Because be used on master chip 1, engaging the time weak point of two sub-chips 2,3, so even master chip 1 is heated to first temperature T 1, the characteristic of master chip 1 is deterioration hardly.
Fig. 4 is the graphic front view of the semiconductor device obtained of the manufacture method by embodiments of the present invention 2.
This semiconductor device has as the sub-chip 52 of first Semiconductor substrate and sub-chip 53, as so-called chip base chip (Chip-On-Chip) structure of the master chip 51 overlapping joints of second Semiconductor substrate.Sub-chip 52,53 is littler than master chip 51.
Master chip 51 and sub-chip 52,53 surfaces opposite to each other become active face 51a, 52a, the 53a that has formed function element or wiring etc. respectively.The active face 51a of master chip 51 is provided with a plurality of metal bump (bump) 54.Metal bump 54 is made of gold (Au).Near the periphery of active face 51a, be provided with outside the taking-up with electrode 57 in the not relative part of active face 52a, 53a.
On active face 52a, the 53a of sub-chip 52,53, be provided with metal bump 55,56 in the position corresponding with metal bump 54.Metal bump 55,56 is made of gold (Au).Have the thin layer (not shown) that is made of tin (Sn) between metal bump 54 and metal bump 55,56, metal bump 54 and metal bump 55,56 engage by this tin layer.
On master chip 51 and sub-chip 52,53; when not being formed on the joint of master chip 51 and sub-chip 52,53, be used to protect on master chip 51 or the sub-chip 52,53 the not protection diode of destruction by electrostatic field (being connected the diode on the metal bump 54,55,56) of the element that forms.Therefore, master chip 51 is compared with the semiconductor chip that has formed such protection diode with sub-chip 52,53, can form more other function element.
The face of an opposite side with active face 51a of master chip 51 is bonded on support portion (island) 59a of lead frame 59.In the side of support portion 59a,, dispose the 59b of lead terminal portion of the lead frame 59 that extends to the side with support portion 59a devices spaced apart.The outside taking-up with electrode 57 is connected by bonding wire 58 with the 59b of lead terminal portion.The zone of connecting portion that comprises master chip 51, sub-chip 52,53, support portion 59a, bonding wire 58 and bonding wire 58 and the 59b of lead terminal portion is protected by sealing resin 60 (among Fig. 4, being represented by double dot dash line).
Fig. 5 (a)～Fig. 5 (c) is the diagram front view of manufacture method that is used for the semiconductor device of key diagram 4, and Fig. 6 (a)～Fig. 6 (c) is near the cutaway view that has amplified this metal bump 54,55.Fig. 6 (a) is corresponding with Fig. 5 (a), and Fig. 6 (b) is corresponding with Fig. 5 (b), and Fig. 6 (c) is corresponding with Fig. 5 (c).
The wafer W of using in the manufacturing of semiconductor device comprises a plurality of (for example thousands of) the unit area U (among Fig. 5 (a) and Fig. 5 (b) dot the border of adjacent unit area U) corresponding with master chip 51.The active face Wa of wafer W is corresponding to the active face 51a of master chip 51.On active face Wa, form metal bump 54.The top ends of metal bump 54 almost becomes smooth face, is formed with layer (the tin layer) 70 (with reference to Fig. 6 (a)) that is made of tin on this face.
At first, on the top that is formed on the metal bump 54 on the active face Wa of wafer W, by flooding, duplicate etc., coating flux 22.Then, make active face Wa upwards, wafer W is almost flatly placed on the objective table 61.Be provided with heater 62 and temperature sensor 63 in objective table 61 inside, can the wafer W that be placed on the objective table 61 be heated to fixed temperature according to the output of temperature sensor 63.
Then, shown in Fig. 5 (a), sub-chip 52 has adsorbed the face of the opposite side of active face 52a by absorption folder 64, makes active face 52a towards the below, and is with horizontal state almost, relative with wafer W.The top of metal bump 55 is almost smooth face.There is not to form the layer (with reference to Fig. 6 (a)) that constitutes by tin on the surface of metal bump 55.Absorption folder 64 for example can pass through vacuum suction, adsorbs sub-chip 52.
Under this state, metal bump 54 contrapositions of the metal bump 55 of sub-chip 52 and corresponding wafer W, absorption folder 64 descends.At this moment, the position of metal bump 54 and metal bump 55 can be offset shown in Fig. 6 (a) a little.If metal bump 54 and metal bump 55 are close to a certain degree, the decrease speed of sub-chip 52 is reduced.
Then, behind the surface of the following end in contact flux 22 of metal bump 55, before the surface that touches tin layer 70, the decline of sub-chip stops (with reference to Fig. 5 (b) and Fig. 6 (b)), and sub-chip 52 separates from absorption folder 64, is placed on the wafer W.In view of the above, become with flux 22 metal bump 55 temporarily is fixed on state on the metal bump 54.
Like this, it is desirable to, by absorption folder 64 bundle chips 52 by on wafer W, applied load not on wafer W or sub-chip 52.In view of the above, can avoid wafer W or 52 breakages of sub-chip.Even it is on wafer W or sub-chip 52, add some loads, also out of question.
In above step, for example temporary transient sometimes fixing preceding sub-chip 52 is charged., under temporary transient fixing state, metal bump 54 and metal bump 55 by the flux 22 of insulator by electric insulation, so can not take place from of the discharge of sub-chip 52 to wafer W.Therefore, even do not form protection diode on the metal bump 55 of the metal bump 54 that is connected wafer W (master chip 51) and sub-chip 52, can not cause electrostatic breakdown to the function element that is formed on the wafer W (master chip 51) yet.
Then, same with sub-chip 52, temporary transient stator chip 53 on wafer W.The metal bump 56 of sub-chip 53 is same with the metal bump 55 of sub-chip 52, and the top becomes almost smooth, does not form the layer that is made of tin in its surface.
Like this, in a unit area U, obtain the wafer W of temporarily having fixed sub-chip 52,53.Equally, in all unit area U of wafer W, temporarily fixed sub-chip 52,53.Under this state, only effect is based on the load of the weight of sub-chip 52,53 on wafer W, and wafer W and sub-chip 52,53 are non-loaded in fact.Above step is carried out at normal temperatures.
Then, by being arranged on the heater 62 on the objective table 61, wafer W is heated to the temperature (for example more than 240 ℃) more than the fusing point of tin in preset time.In view of the above, 70 fusing of tin layer are solidified, and the metal bump 55,56 of all sub-chips 52,53 joins on the metal bump 54 of wafer W by tin layer 70.At this moment, when on surface of metal bump 54,55,56 etc., being formed with oxide-film, because the effect of flux 22, remove oxide-film, fully improve for the soakage of the fusing fluid of tin on the surface of metal bump 54,55,56, and metal bump 54 and metal bump 55,56 engage well by tin layer 70.
Because wafer W and sub-chip 52,53 are non-loaded in fact, sub-chip 52,53 can change the position to wafer W.Therefore, when metal bump 55,56 during for metal bump 54 skew, the surface tension of the fusing fluid by tin, metal bump 54 and metal bump 55,56 move (alignment certainly), make skew diminish (with reference to Fig. 6 (c)).Can reduce offset, joint wafer W (master chip 51) and sub-chip 52,53.
Then, clean wafer W, remove the residue of flux 22.Then, shown in Fig. 5 (c),, cut off wafer W, cut out the master chip 51 that has engaged sub-chip 52,53 from wafer W with wafer dicing saw 71 along the border of adjacent unit area U.Be bonded on the 59a of support portion with the face of the opposite side of active face 51a of master chip 51, by bonding wire 58 connected outside taking-up with electrode 57 and the 59b of lead terminal portion after, around master chip 51, sub-chip 52,53 etc., form sealing resin, obtain semiconductor device shown in Figure 4.
In the manufacture method of above semiconductor device, the joint of master chip 51 and sub-chip 52,53 has temporarily been fixed sub-chip 52,53 by heating in all unit area U wafer W is unified to carry out, so productivity is good.In addition, in manufacture method in the past, repeat to load and heating for wafer,, in above method, do not produce such problem so wafer etc. are damaged easily according to sub-chip-count.
In addition, can cut off wafer W before the joint of sub-chip 52,53, the joint element chip 52,53 on master chip 51.
In the manufacture method of the semiconductor device of execution mode 1 and 2, for example, can pass through blowing warm air, heated chip W and sub-chip 2,3,52,53 when not carrying out temperature closely when adjusting to wafer W and sub-chip 2,3,52,53.
Semiconductor device can only engage 1 sub-chip 2 (3), 52 (53) on a master chip 1,51, also can engage the sub-chip more than 3.On sub-chip 2 (3), 52 (53), can engage other sub-chip.
Replace tin layer 20,70, can form by other low-melting-point metals or its alloy (scolding tin) for example indium (In), tin-lead (Pb) class alloy, Xi-Yin (Ag)-copper (Cu) class alloy etc. constitute layer.In execution mode 1, when replacing tin layer 20 to form the layer that is made of alloy, first temperature can be more than the solidus temperature for this alloy, and second temperature is below the solidus temperature of this alloy.In addition, in execution mode 2, when replacing the tin layer to form the layer that is made of alloy, the heating-up temperature of master chip 51 (wafer W) and sub-chip 52,53 can be more than the solidus temperature for this alloy.
The joint sequency of sub-chip 2,3 (52,53) is engaged sub-chip 2 (52) in all unit area U of wafer W after, joint element chip 3 (53) in all unit area U of wafer W.
More than, describe embodiments of the invention in detail, but they only are the concrete examples that uses for clear and definite technology contents of the present invention, and the present invention should not be interpreted as being defined in these concrete examples, and the spirit and scope of the present invention are only limited by additional claims.
The application is willing to 2002-225097 number with the spy who proposed to Patent Office of Japan on August 1st, 2002 and on August 13rd, 2002 was willing to the spy that Patent Office of Japan proposes that 2002-236036 was corresponding, by reference, whole descriptions of these applications is included in here.
Claims (4)
1. the manufacture method of a semiconductor device, be the manufacture method that engages the semiconductor device that lip-deep first metal bump of a side be formed on first Semiconductor substrate constitutes with being formed on lip-deep second metal bump of a side of second Semiconductor substrate, comprise:
Form the step of the layer that constitutes by low-melting-point metal on the top of at least one side in described first and second metal bump;
The flux applying step of coating flux on the top of at least one side in described first and second metal bump;
After this flux applying step, make the described side surface of the described side surface of described first Semiconductor substrate and described second Semiconductor substrate relative, with described flux described first metal bump and the temporary transient temporary transient fixing step of fixing of described second metal bump;
After this temporary transient fixing step, described first and second Semiconductor substrate are heated to the heating steps of temperature more than the solidus temperature of the layer that constitutes by described low-melting-point metal.
2. the manufacture method of semiconductor device according to claim 1 wherein, to described first and second Semiconductor substrate, is not added under the no-load condition in fact of the load of pushing them, carries out described heating steps.
3. the manufacture method of semiconductor device according to claim 1, wherein, described temporary transient fixing step comprises: the step of temporary transient fixing a plurality of described first Semiconductor substrate on a described side surface of described second Semiconductor substrate.
4. the manufacture method of semiconductor device according to claim 1, wherein, described first Semiconductor substrate is a semiconductor chip, described second Semiconductor substrate is a semiconductor wafer; Behind the described heating steps, also comprise the step of cutting off described semiconductor wafer.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2002225097A JP3850352B2 (en) | 2002-08-01 | 2002-08-01 | Manufacturing method of semiconductor device |
| JP2002225097 | 2002-08-01 | ||
| JP2002236036 | 2002-08-13 |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB031525091A Division CN100356530C (en) | 2002-08-01 | 2003-08-01 | Mfg. method for semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN1983544A true CN1983544A (en) | 2007-06-20 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNA2007100017248A Pending CN1983544A (en) | 2002-08-01 | 2003-08-01 | Manufacturing method for semiconductor device |
Country Status (2)
| Country | Link |
|---|---|
| JP (1) | JP3850352B2 (en) |
| CN (1) | CN1983544A (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4782177B2 (en) * | 2008-08-29 | 2011-09-28 | キヤノンマシナリー株式会社 | Chip stack manufacturing equipment |
| US7854365B2 (en) * | 2008-10-27 | 2010-12-21 | Asm Assembly Automation Ltd | Direct die attach utilizing heated bond head |
| JP5187341B2 (en) * | 2010-04-14 | 2013-04-24 | ルネサスエレクトロニクス株式会社 | Manufacturing method of semiconductor device |
| US8349116B1 (en) * | 2011-11-18 | 2013-01-08 | LuxVue Technology Corporation | Micro device transfer head heater assembly and method of transferring a micro device |
| KR102190382B1 (en) | 2012-12-20 | 2020-12-11 | 삼성전자주식회사 | Semiconductor package |
-
2002
- 2002-08-01 JP JP2002225097A patent/JP3850352B2/en not_active Expired - Lifetime
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2003
- 2003-08-01 CN CNA2007100017248A patent/CN1983544A/en active Pending
Also Published As
| Publication number | Publication date |
|---|---|
| JP3850352B2 (en) | 2006-11-29 |
| JP2004071648A (en) | 2004-03-04 |
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