CN1979815A - Film transistor mfg. method - Google Patents
Film transistor mfg. method Download PDFInfo
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- CN1979815A CN1979815A CN 200510130090 CN200510130090A CN1979815A CN 1979815 A CN1979815 A CN 1979815A CN 200510130090 CN200510130090 CN 200510130090 CN 200510130090 A CN200510130090 A CN 200510130090A CN 1979815 A CN1979815 A CN 1979815A
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Abstract
The method includes steps: forming buffer layer on substrate; forming first and second islands of polysilicon on the buffer layer; forming grid insulating layer on the substrate; forming first and second grid electrodes on the grid insulating layer; forming sacrificial layer on the substrate, and forming photoresist layer on the sacrificial layer; using photoresist layer being as mask to remove sacrificial layer above the first island of polysilicon; carrying out first ion implantation procedure in order to form first source electrode/drain electrode inside first island of polysilicon; removing photoresist layer, and then carrying out second ion implantation procedure in order to form second source electrode/drain electrode inside second island of polysilicon; the second ion implantation procedure makes ions implant inside the buffer layer under two sides of second grid electrode; removing the sacrificial layer, and then carrying out ion implantation procedure with shallow doping.
Description
Technical field
The present invention relates to a kind of method of manufacturing thin film transistor, and be particularly related to a kind of manufacture method of low-temperature polysilicon film transistor.
Background technology
Early stage polycrystalline SiTFT (poly-silicon thin film transistor, poly-siliconTFT) solid-phase crystallization (solid phase crystallization is adopted in making, SPC) technology, because its technological temperature is up to 1000 degree Celsius, so the essential higher quartz base plate of fusing point that adopts.In addition, because the quartz base plate cost is expensive more many than glass substrate, and under the limited situation of substrate size, therefore can only develop small panel (panel approximately only has 2 to 3 inches) in the past.Along with the continuous progress of laser technology, (excimer laser annealing, ELA) technology also is applied in the manufacturing process of polycrystalline SiTFT quasi-molecule laser annealing in recent years.
Quasi-molecule laser annealing technology mainly is to use laser beam irradiation in amorphous silicon layer (amorphoussilicon layer, a-Si layer), make that crystallization again (recrystallization) becomes polysilicon layer (poly-silicon layer) after the amorphous silicon layer fusion (melting).Can below temperature 600 degree Celsius, finish whole technologies owing to adopt the polycrystalline SiTFT manufacturing process of quasi-molecule laser annealing technology, therefore the formed polycrystalline SiTFT of this kind technology low-temperature polysilicon film transistor (low temperature poly-silicon TFT, LTPS TFT) that is otherwise known as.
Figure 1A to Fig. 1 C is the schematic diagram of the manufacture method of known low-temperature polysilicon film transistor.Please earlier with reference to Figure 1A, the manufacture method of known low-temperature polysilicon film transistor comprises the following steps.At first, on substrate 110, form resilient coating (buffer layer) 120, on resilient coating 120, form first polysilicon island thing (poly-silicon island) 130a and the second polysilicon island thing 130b then.Then, on the first polysilicon island thing 130a and the second polysilicon island thing 130b, form gate insulation layer 140.Come again, on gate insulation layer 140, form first grid 150a and second grid 150b.
Please refer to Figure 1B, on substrate 110, form photoresist layer 210, to cover second polysilicon island thing 130b and the second grid 150b.Then, carry out first ion and implant operation (ion implantationprocess) S110, with the formation first source/drain 132a in the first polysilicon island thing 130a, and promptly first passage district (channel region) 134a between the first source/drain 132a.
Please refer to Fig. 1 C, after forming the first source/drain 132a, remove photoresist layer 210.Then, on substrate 110, form photoresist layer 220, to cover first polysilicon island thing 130a and the first grid 150a.Then, carrying out second ion and implant operation S120, with the formation second source/drain 132b in the second polysilicon island thing 130b, and promptly is second channel district 134b between the second source/drain 132b.Come again, remove photoresist layer 220, so far roughly finish the manufacturing of known low-temperature polysilicon film transistor.It should be noted that the manufacture method of this known low-temperature polysilicon film transistor must form photoresist layer 210 and 220 respectively in order to form the first source/drain 132a and the second source/drain 132b.In other words, the manufacture method of this known low-temperature polysilicon film transistor must use the twice photo etched mask just can finish the manufacturing of the first source/drain 132a and the second source/drain 132b.Therefore, in order to reduce the photo etched mask number, develop the manufacture method that another kind of known low-temperature polysilicon film transistor.
Fig. 2 A to Fig. 2 B is the schematic diagram of the manufacture method of another known low-temperature polysilicon film transistor.Please earlier with reference to Fig. 2 A, the manufacture method of known low-temperature polysilicon film transistor comprises the following steps.At first, on substrate 110, form resilient coating 120, the first polysilicon island thing 130a, the second polysilicon island thing 130b, gate insulation layer 140, first grid 150a and second grid 150b successively as above-mentioned manufacture method.Then, carrying out first ion and implant operation S110, with the formation first source/drain 132a in the first polysilicon island thing 130a, and promptly is first passage district 134a between the first source/drain 132a.It should be noted that the operation of ion implantation for the first time S110 implants the boron ion in the second polysilicon island thing 130b equally.
Please refer to Fig. 2 B, then, on substrate 110, form photoresist layer 230, to cover first polysilicon island thing 130a and the first grid 150a.Then, carrying out second ion and implant operation S130, with the formation second source/drain 132c in the second polysilicon island thing 130b, and promptly is second channel district 134c between the second source/drain 132c.Come again, remove photoresist layer 230, so far roughly finish the manufacturing of known low-temperature polysilicon film transistor.Can reduce photo etched mask one though it should be noted that this kind manufacture method, yet the operation of ion implantation for the first time S110 implants the boron ion in the second polysilicon island thing 130b equally.In other words, the previous boron ion of implanting will influence the phosphonium ion that the operation of ion implantation for the second time S130 is implanted.In addition, above-mentioned two kinds of manufacture methods all can't form shallow doped-drain (Light Doped Drain, structure LDD) is to improve the phenomenon of leakage current.
Summary of the invention
In view of the foregoing, purpose of the present invention just provides a kind of method of manufacturing thin film transistor, reducing employed photo etched mask number, and forms the thin-film transistor of the structure with shallow doped-drain.
Based on above-mentioned purpose or other purpose, the present invention proposes a kind of method of manufacturing thin film transistor, and it comprises the following steps.At first, on substrate, form resilient coating, on resilient coating, form the first polysilicon island thing and the second polysilicon island thing then.On substrate, form gate insulation layer, and cover the first polysilicon island thing and the second polysilicon island thing.On the gate insulation layer above the first polysilicon island thing, form first grid, and on the gate insulation layer above the second polysilicon island thing, form second grid.Then, on substrate, form sacrifice layer, and cover first grid and second grid.On the sacrifice layer above the second polysilicon island thing, form photoresist layer, utilize photoresist layer to be mask then, remove the sacrifice layer of first polysilicon island thing top.Then, carrying out first ion and implant operation, with formation first source/drain in the first polysilicon island thing of first grid down either side, and promptly is the first passage district between first source/drain.Remove photoresist layer, carry out second ion then and implant operation, in the second polysilicon island thing of second grid down either side, to form second source/drain, and promptly be the second channel district between second source/drain, second ion implantation operation is implanted in the resilient coating of second grid down either side ion simultaneously.Remove this sacrifice layer, carry out shallow dopant ion then and implant operation, between second source/drain and second channel district, to form shallow doped-drain.
According to the embodiment of the invention, the material of sacrifice layer can be silicon nitride (silicone nitride).
According to the embodiment of the invention, the thickness of sacrifice layer can be between 50 to 2000 dusts (angstrom).
According to the embodiment of the invention, the ion concentration that second ion implantation operation is implanted can be between 1E14 to 1E15ions/cm
2Between.
According to the embodiment of the invention, it can be between 10 to 200keV that second ion is implanted the employed implantation energy of operation.
According to the embodiment of the invention, after forming this shallow doped-drain, this method of manufacturing thin film transistor can also form pattern dielectric layer on substrate, and wherein pattern dielectric layer exposes part first source/drain and part second source/drain.Then, on pattern dielectric layer, form the first source/drain conductor layer and the second source/drain conductive layer, wherein the first source/drain conductor layer is electrically connected with first source/drain respectively, and the second source/drain conductor layer is electrically connected with second source/drain respectively.
According to the embodiment of the invention, on gate insulation layer, form after first grid and the second grid, this method of manufacturing thin film transistor can also utilize first grid and second grid as mask, etch-gate insulating barrier partly is so that the thickness of the gate insulation layer under first grid and the second grid is greater than the thickness of the gate insulation layer of other parts.
According to the embodiment of the invention, on gate insulation layer, form after first grid and the second grid, this method of manufacturing thin film transistor can also utilize first grid and second grid as mask, and the etch-gate insulating barrier is to remove not by the gate insulation layer of first grid and second grid covering.
According to the embodiment of the invention, after forming gate insulation layer with form before first grid and the second grid, this method of manufacturing thin film transistor can also be carried out the 3rd ion implantation operation, to be implanted into ion in the first polysilicon island thing.
According to the embodiment of the invention, after forming gate insulation layer with form before first grid and the second grid, this method of manufacturing thin film transistor can also be carried out the 4th ion implantation operation, to be implanted into ion in the second polysilicon island thing.
Based on above-mentioned, the present invention formed sacrifice layer and the photoresist layer that covers second grid earlier before forming first source/drain.After forming first source/drain, remove photoresist layer and carry out second ion implantation operation, in the second polysilicon island thing, to form second source/drain.At this moment, owing to sacrifice layer is covered on the second grid, so the ion implantation depth of zones of different and inequality.In other words, second ion is implanted operation ion is implanted in the second polysilicon island thing in the resilient coating with first polysilicon island thing below, therefore do not cover under the situation of photoresist layer at the first polysilicon island thing, the ion that second ion implantation operation is implanted can reduce for the electrical influence of the first polysilicon island thing.In addition, compare with known technology, photo etched mask number required for the present invention is less.
For above and other objects of the present invention, feature and advantage can be become apparent, preferred embodiment cited below particularly, and conjunction with figs. are described in detail below.
Description of drawings
Figure 1A to Fig. 1 C is the schematic diagram of the manufacture method of known low-temperature polysilicon film transistor.
Fig. 2 A to Fig. 2 B is the schematic diagram of the manufacture method of another known low-temperature polysilicon film transistor.
Fig. 3 A to Fig. 3 E is the schematic diagram according to the method for manufacturing thin film transistor of the present invention's first preferred embodiment.
Fig. 4 A to Fig. 4 F is the schematic diagram according to the method for manufacturing thin film transistor of the present invention's second preferred embodiment.
Fig. 5 A to Fig. 5 E is the schematic diagram according to the method for manufacturing thin film transistor of the present invention's the 3rd preferred embodiment.
The main element description of symbols
110,310: substrate
120,320: resilient coating
130a, 330a: the first polysilicon island thing
130b, 330b: the second polysilicon island thing
132a, 332a, 432a, 532a: first source/drain
132b, 132c, 332b, 432b, 532b: second source/drain
134a, 334a, 434a, 534a: first passage district
134b, 134c, 334b, 434b, 534b: second channel district
140,340,440,540: gate insulation layer
150a, 350a: first grid
150b, 350b: second grid
210,220,230,610: photoresist layer
300,400,500: thin-film transistor
336b, 436b, 536b: shallow doped-drain
360: sacrifice layer
370: pattern dielectric layer
380a: the first source/drain conductor layer
380b: the second source/drain conductor layer
S110, S210, S310, S410: first ion is implanted operation
S120, S130, S220, S320, S420: second ion is implanted operation
S230, S330, S430: shallow dopant ion is implanted operation
Embodiment
First embodiment
Fig. 3 A to Fig. 3 E is the schematic diagram according to the method for manufacturing thin film transistor of the present invention's first preferred embodiment.Please refer to Fig. 3 A, the method for manufacturing thin film transistor of present embodiment comprises the following steps.At first, on substrate 310, form resilient coating 320, the method that wherein forms resilient coating 320 can be low-pressure chemical vapor deposition (low pressure CVD, LPCVD) technology or plasma enhanced chemical vapor deposition (plasma enhanced CVD, a PECVD) technology.More specifically, resilient coating 320 for example is the mono-layer oxidized silicon or the double-decker of silica/silicon nitride.In addition, substrate 310 can be glass substrate, quartz base plate or plastic base.
Then, on resilient coating 320, form the first polysilicon island thing 330a and the second polysilicon island thing 330b.More specifically, the step that forms the first polysilicon island thing 330a and the second polysilicon island thing 330b for example is to form the amorphous silicon layer (not shown) earlier on substrate 310, and the thickness of amorphous silicon layer can be between 100 dust to 1000 dusts, and preferable thickness is 500 dusts.In addition, the mode of formation amorphous silicon layer for example is chemical vapour deposition (CVD) (chemical vapor deposition, CVD) technology or plasma enhanced chemical vapor deposition (PECVD) technology.Then, carry out laser annealing (laser annealing) technology for this amorphous silicon layer, so that amorphous silicon layer is transformed into polysilicon layer.Then, carry out photoetching (photolithography) technology and etching (etching) technology, on substrate 310, to form the first polysilicon island thing 330a and the second polysilicon island thing 330b for this polysilicon layer.
Above-mentioned laser annealing technique for example be excimer laser, solid-state laser (solid-state laser) or diode excitation formula solid-state laser (diode pumped solid state laser, DPSS).More particularly, before carrying out laser annealing technique, also can carry out dehydrogenation (dehydrogenation) technology earlier, to reduce the hydrogen content in the amorphous silicon layer for amorphous silicon layer.What deserves to be mentioned is, the resilient coating 320 of suitable thickness not only can avoid the metal ion in the substrate 310 to diffuse among the first polysilicon island thing 330a and the second polysilicon island thing 330b of follow-up formation, also can reduce the cooldown rate of laser annealing technique, to form bigger silicon crystalline particle.In addition, above-mentioned resilient coating 320 also can improve metal ions in the substrate 310 and diffuses to phenomenon in the polysilicon island thing 330.
Please continue A, then, on substrate 310, form gate insulation layer 340, and cover the first polysilicon island thing 330a and the second polysilicon island thing 330b with reference to Fig. 3.In addition, the material of gate insulation layer 340 can be silica or other insulating material.More specifically, the mode that forms silica can be to adopt pecvd process, and cooperates SiH
4/ N
2O or TEOS/O
2Deng reacting gas.What deserves to be mentioned is, in order to adjust the electrical property of the first polysilicon island thing 330a and the second polysilicon island thing 330b, after gate insulation layer 340, also can carry out ion implantation operation for the first polysilicon island thing 330a and the second polysilicon island thing 330b respectively, (channeldoping) operation of passage doping just.
Then, on the gate insulation layer 340 above the first polysilicon island thing 330a, form first grid 350a, and on the gate insulation layer 340 above the second polysilicon island thing 330b, form second grid 350b.More specifically, the mode that forms first grid 350a and second grid 350b can be first on gate insulation layer 340 with sputter (sputtering) technology or physical vapour deposition (PVD) (physics vapordeposition, PVD) technology forms the gate material layers (not shown), wherein the material of gate material layers can be chromium (Cr) or other metal material, and the thickness of gate material layers can be between 1000 dust to 8000 dusts, and the preferred thickness of gate material layers is 4000 dusts.Then, again this gate material layers is carried out photoetching process and etch process, to form first grid 350a and second grid 350b.
After forming first grid 350a and second grid 350b, on substrate 310, form sacrifice layer 360, and cover first grid 350a, second grid 350b and gate insulation layer 340, wherein the thickness of sacrifice layer 360 can be between 50 dust to 2000 dusts, and preferable thickness for example is 1000 dusts.In addition, the material of sacrifice layer 360 for example is silicon nitride (silicon nitride), and the mode of formation silicon nitride for example is to adopt pecvd process, and complex reaction gas SiH
4/ NH
3
Please refer to Fig. 3 B, on the sacrifice layer 360 above the second polysilicon island thing 350b, form photoresist layer 610, utilize photoresist layer 610 to be mask then, remove the sacrifice layer 360 of first polysilicon island thing 350a top.When the material of sacrifice layer 360 was silicon nitride, the mode that removes sacrifice layer 360 for example was to use phosphoric acid (phosphoric acid) to carry out etch process.Then, carrying out first ion and implant operation S210, with the formation first source/drain 332a in the first polysilicon island thing 330a of first grid 350a down either side, and promptly is first passage district 334a between the first source/drain 332a.
In addition, first ion is implanted ion that operation S210 implanted can P type alloy, and wherein p type alloy can be the boron ion.In addition, the doping content of boron ion can be between 2E14 to 2E15ions/cm
2, and preferable doping content for example is 1E15ions/cm
2In addition, preferable implantation energy for example is 30keV.
Please refer to Fig. 3 C, after forming the first source/drain 332a, remove photoresist layer 610.Then, carrying out second ion and implant operation S220, with the formation second source/drain 332b in the second polysilicon island thing 330b of second grid 350b down either side, and promptly is second channel district 334b between the second source/drain 332b.In addition, the ion that second ion implantation operation S220 is implanted can be a n type alloy, and wherein n type alloy can be a phosphonium ion.In addition, the doping content of phosphonium ion for example is between 1E14 to 1E15ions/cm
2, and preferable concentration for example is 5E14ions/cm
2In addition, implant energy and for example be 10 to 200keV, and preferable implantation energy for example is 125keV.
It should be noted that because the influence of sacrifice layer 360 therefore second ion is implanted operation S220 and not only ion implanted in the second polysilicon island thing 330b, also pass through the first polysilicon island thing 330a and implant in the resilient coating 320.In other words, for the first polysilicon island thing 330a, the ion that ion that first ion implantation operation S210 is implanted and second ion implantation operation S220 are implanted can't interact, and that is to say the influence owing to sacrifice layer 360, so the doping depth of zones of different and inequality.In addition because sacrifice layer 360 has the function of mask, therefore second ion implant the formed second source/drain 332b of operation S220 the edge not can with the justified margin of second grid 350b.
Then, please refer to Fig. 3 D, remove after the sacrifice layer 360, with second grid 350b is that mask carries out shallow dopant ion implantation operation S230, to form shallow doped-drain 336b between the second source/drain 332b and channel region 334b, it is in order to improve hot carrier's effect (hot carrier effect).So far, tentatively finish the manufacturing of thin-film transistor.In addition, the ion that shallow dopant ion implantation operation S230 is implanted can be a n type alloy, and wherein n type alloy can be a phosphonium ion.In addition, the doping content of phosphonium ion for example is between 1E13 to 1E14ions/cm
2, and preferable concentration for example is 5E3ions/cm
2In addition, implanting energy for example is between 10 to 100keV, and preferable implantation energy can be 65keV.
Compare with known technology, the present invention adopts sacrifice layer 360 and second grid 350b to form the second source/drain 332b as mask with elder generation earlier, and after removing sacrifice layer 360, then can directly utilize second grid 350b to form shallow doped-drain 336b, so the present invention need not use other one photo etched mask operation to define shallow doped-drain 336b as mask.
Please refer to Fig. 3 E, after forming shallow doped-drain 336b, form pattern dielectric layer 370 on substrate 310, wherein pattern dielectric layer 370 exposes part first source/drain 332a and the part second source/drain 332b.More specifically, the mode that forms pattern dielectric layer 370 can be to form dielectric layer with CVD technology on substrate 310 earlier, and the material of this dielectric layer for example is silica, silicon nitride or other insulating material.In addition, the thickness of this dielectric layer can be between 2000 dust to 8000 dusts, is preferably 4000 dusts.After forming dielectric layer, carry out thermal process for the formed structure of above-mentioned technology, its can be flash annealing technology (rapid thermalannealing, RTA), its temperature range for example is 500 to 650 degree Celsius, and preferable temperature for example is 600 degree Celsius.In addition, annealing time can be between 10 to 120 seconds, and preferable annealing time can be 70 seconds.Then, carry out photoetching process and etch process, to form pattern dielectric layer 370 for this dielectric layer.
Then, on pattern dielectric layer 370, form the first source/drain conductor layer 380a and the second source/drain conductor layer 380b, to finish the manufacturing of thin-film transistor 300, wherein the first source/drain conductor layer 380a is electrically connected with the first source/drain 332a respectively, and the second source/drain conductor layer 380b is electrically connected with the second source/drain 332b respectively.More specifically, the mode that forms the first source/drain conductor layer 380a and the second source/drain conductor layer 380b can be to form the source/drain conductor material layer with sputtering process or PVD technology on pattern dielectric layer 370 earlier, and wherein the material of source/drain conductor material layer can be chromium (Cr) or other metal material.In addition, the thickness of source/drain conductor material layer can be between 1000 dust to 8000 dusts, is preferably 4000 dusts.Then, again this source/drain conductor material layer is carried out photoetching process and etch process, to form the first source/drain conductor layer 380a and the second source/drain conductor layer 380b.
Second embodiment
Fig. 4 A to Fig. 4 F is the schematic diagram according to the method for manufacturing thin film transistor of the present invention's second preferred embodiment.Please refer to Fig. 4 A, second embodiment is similar to first embodiment, its difference is: after forming resilient coating 320, the first polysilicon island thing 330a, the second polysilicon island thing 330b, gate insulation layer 440, first grid 350a and second grid 350b successively, utilize first grid 350a and second grid 350b as mask, partly the etch-gate insulating barrier 440, so that the thickness of the gate insulation layer 440 under first grid 350a and the second grid 350b is greater than the thickness of the gate insulation layer 440 of other parts.More specifically, the thickness of the gate insulation layer after the etching 440 is preferably 400 dusts.
The step of Fig. 4 B to Fig. 4 F is similar to previous Fig. 3 A to Fig. 3 E, it comprises formation sacrifice layer 360, form photoresist layer 610, remove partial sacrifice layer 360, form the first source/drain 432a and the first passage district 434a between the first source/drain 432a, form the second source/drain 432b and the second channel district 434b between the second source/drain 432b, between the second source/drain 432b and second channel district 434b, form shallow doped-drain 436b, form pattern dielectric layer 370, form steps such as the first source/drain conductor layer 380a and the second source/drain conductive layer 380b, to finish the manufacturing of thin-film transistor 400.
Compare with first embodiment, because the thinner thickness of gate insulation layer 440, therefore the implantation energy of first ion implantation operation S310 can be between between the 5keV to 100keV, and preferable implantation energy is 20keV.In addition, the preferable implantation energy of second ion implantation operation S320 is 80keV.In addition, the implantation energy that shallow dopant ion is implanted operation S330 can be between between the 5keV to 100keV, and preferable implantation energy is 40keV.
It should be noted that, as first embodiment, because sacrifice layer 360 is covered on the second polysilicon island thing 330b, therefore implant among the operation S320 at second ion, the ion that second ion implantation operation S320 is implanted runs through the first polysilicon island thing 330a and implants in the resilient coating 320 of first polysilicon island thing 330a below.In other words, second ion is implanted ion that operation S320 implanted and can be reduced for the influence of the electrical quality of the first polysilicon island thing 330a.In addition, use lower implantation energy because second ion is implanted operation S320, it is less for the damage of the lattice structure of the first polysilicon island thing 330a that therefore second ion is implanted operation S320.
The 3rd embodiment
Fig. 5 A to Fig. 5 E is the schematic diagram according to the method for manufacturing thin film transistor of the present invention's the 3rd preferred embodiment.Please refer to Fig. 5 A, the 3rd embodiment is similar to first embodiment, its difference is: after forming resilient coating 320, the first polysilicon island thing 330a, the second polysilicon island thing 330b, gate insulation layer 540, first grid 350a and second grid 350b successively, utilize first grid 350a and second grid 350b as mask, etching is not by the gate insulation layer 540 of first grid 350a and second grid 350b covering fully.
The step of Fig. 5 B to Fig. 5 E is also similar to previous Fig. 3 B to Fig. 3 E, it comprises formation sacrifice layer 360, form photoresist layer 610, remove partial sacrifice layer 360, form the first source/drain 532a and the first passage district 534a between the first source/drain 532a, form the second source/drain 532b and the second channel district 534b between the second source/drain 532b, between the second source/drain 532b and second channel district 534b, form shallow doped-drain 536b, form pattern dielectric layer 370, form steps such as the first source/drain conductor layer 380a and the second source/drain conductive layer 380b, to finish the manufacturing of thin-film transistor 500.
Especially, compare with second embodiment, because remove fully not by the gate insulation layer 540 of first grid 350a and second grid 350b covering, therefore the implantation energy of first ion implantation operation S410 can be between 5keV to 100keV, preferable implantation energy is 10keV.In addition, the implantation energy that second ion is implanted operation S420 can be between 10keV to 200keV, and preferable implantation energy is 65keV.In addition, the implantation energy that shallow dopant ion is implanted operation S430 can be between 5keV to 100keV, and preferable implantation energy is 10keV.
In sum, compare with known technology, because the present invention is before carrying out first and second ion implantation operation, on second grid, form earlier sacrifice layer, and when second ion is implanted operation, the ion that second ion implantation operation is implanted can run through the first polysilicon island thing and implant the resilient coating that is positioned at first polysilicon island thing below, so the ion that second ion implantation operation is implanted can alleviate for the influence that first ion implantation operation is implanted in the ion in the first polysilicon island thing.In other words, compare with known technology, the present invention not only can reduce photo etched mask one, can also improve interacting between doped with boron ion and the Doping Phosphorus ion.
In addition, therefore the formed sacrifice layer of the present invention can also can save the photo etched mask operation that together shallow doped-drain is implanted as the mask of shallow doped-drain.
In addition, restriction along with the implantation energy of ion implantation equipment, the present invention also proposes different manufacture methods, not only can be applicable to the low ion implantation equipment of implanting energy, also can improve the damage that lattice structure caused of ion implantation technology for polysilicon island thing.
Though the present invention discloses as above with preferred embodiment; right its is not in order to limit the present invention; any person of ordinary skill in the field; without departing from the spirit and scope of the present invention; when can doing a little change and improvement, so protection scope of the present invention is as the criterion when looking the claim person of defining.
Claims (10)
1. method of manufacturing thin film transistor is characterized in that comprising:
On substrate, form resilient coating;
On this resilient coating, form the first polysilicon island thing and the second polysilicon island thing;
On this substrate, form gate insulation layer, and cover this first polysilicon island thing and this second polysilicon island thing;
On this gate insulation layer above this first polysilicon island thing, form first grid, and on this gate insulation layer above this second polysilicon island thing, form second grid;
On this substrate, form sacrifice layer, and cover this first grid and this second grid;
On this sacrifice layer above this second polysilicon island thing, form photoresist layer;
Utilize this photoresist layer to be mask, remove this sacrifice layer of this first polysilicon island thing top;
Carrying out first ion and implant operation, with formation first source/drain in this first polysilicon island thing of this first grid down either side, and promptly is the first passage district between this first source/drain;
Remove this photoresist layer;
Carry out second ion and implant operation, in this second polysilicon island thing of this second grid down either side, to form second source/drain, and promptly be the second channel district between this second source/drain, this second ion implantation operation is implanted in this resilient coating of this second grid down either side ion simultaneously;
Remove this sacrifice layer; And
Carry out shallow dopant ion and implant operation, between this second source/drain and this second channel district, to form shallow doped-drain.
2. method of manufacturing thin film transistor according to claim 1 is characterized in that the material of this sacrifice layer comprises silicon nitride.
3. method of manufacturing thin film transistor according to claim 1, the thickness that it is characterized in that this sacrifice layer is between 50 to 2000 dusts.
4. method of manufacturing thin film transistor according to claim 1 is characterized in that this second ion implants ion concentration that operation implants between 1E14 to 1E15ions/cm
2Between.
5. method of manufacturing thin film transistor according to claim 1 is characterized in that the employed implantation energy of this second ion implantation operation is between 10 to 200keV.
6. method of manufacturing thin film transistor according to claim 1 is characterized in that also comprising after forming this shallow doped-drain:
Form pattern dielectric layer on this substrate, wherein this pattern dielectric layer exposes this first source/drain of part and this second source/drain of part; And
On this pattern dielectric layer, form the first source/drain conductor layer and the second source/drain conductive layer, wherein this first source/drain conductor layer is electrically connected with this first source/drain respectively, and this second source/drain conductor layer is electrically connected with this second source/drain respectively.
7. method of manufacturing thin film transistor according to claim 1 is characterized in that forming after this first grid and this second grid on this gate insulation layer, also comprises:
Utilize this first grid and this second grid as mask, this gate insulation layer of etching partly is so that the thickness of this gate insulation layer under this first grid and this second grid is greater than the thickness of this gate insulation layer of other parts.
8. method of manufacturing thin film transistor according to claim 1 is characterized in that forming after this first grid and this second grid on this gate insulation layer, also comprises:
Utilize this first grid and this second grid as mask, this gate insulation layer of etching is to remove not by this gate insulation layer of this first grid and the covering of this second grid.
9. method of manufacturing thin film transistor according to claim 1, it is characterized in that after forming this gate insulation layer with this first grid of formation and this second grid before, comprise that also carrying out the 3rd ion implants operation, to be implanted into ion in this first polysilicon island thing.
10. method of manufacturing thin film transistor according to claim 1, it is characterized in that after forming this gate insulation layer with this first grid of formation and this second grid before, comprise that also carrying out the 4th ion implants operation, to be implanted into ion in this second polysilicon island thing.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005101300907A CN100466234C (en) | 2005-12-08 | 2005-12-08 | Film transistor mfg. method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005101300907A CN100466234C (en) | 2005-12-08 | 2005-12-08 | Film transistor mfg. method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1979815A true CN1979815A (en) | 2007-06-13 |
| CN100466234C CN100466234C (en) | 2009-03-04 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104882482A (en) * | 2015-03-31 | 2015-09-02 | 上海和辉光电有限公司 | Semiconductor structure and preparation method thereof |
| CN111725138A (en) * | 2019-03-22 | 2020-09-29 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JP2003282880A (en) * | 2002-03-22 | 2003-10-03 | Hitachi Displays Ltd | Display |
| TW587309B (en) * | 2003-02-25 | 2004-05-11 | Toppoly Optoelectronics Corp | Manufacturing method of CMOS thin film transistor |
| CN1259731C (en) * | 2003-02-26 | 2006-06-14 | 友达光电股份有限公司 | Method for producing low-temperature polysilicon thin film transistor |
| TW595004B (en) * | 2003-05-28 | 2004-06-21 | Au Optronics Corp | Manufacturing method of CMOS TFT device |
| CN100339964C (en) * | 2005-04-29 | 2007-09-26 | 友达光电股份有限公司 | Method for making MOS having light doped drain electrode |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104882482A (en) * | 2015-03-31 | 2015-09-02 | 上海和辉光电有限公司 | Semiconductor structure and preparation method thereof |
| CN111725138A (en) * | 2019-03-22 | 2020-09-29 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing semiconductor device |
| CN111725138B (en) * | 2019-03-22 | 2023-05-02 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing semiconductor device |
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