Preferred embodiment describes in detail
Figure 1A and 1B illustrate the emission chain block diagram of 1xEV-DO forward communication link.Those skilled in the art will recognize that the parts shown in Figure 1A and the 1B represent to launch the illustrative example of chain, and the present invention is limited to never in conjunction with the enforcement with reflector of the explicit structure that illustrates among Figure 1A and Figure 1B.Therefore, the content of Figure 1A and Figure 1B and other accompanying drawing purposes as herein described only are explanation, not delimit the scope of the invention.
The emission chain of Figure 1A and Figure 1B is implemented in the base station that its can be in the communication network of forward link or other network elements, comprises the signal path of Traffic Channel or control channel, MAC channel and pilot channel.
Business or control channel signals path comprise encoder 10, illustrate that with the Turbo encoder of encoding rate R=1/3 or R=1/5 it is connected to combiner 12, and combiner 12 is also connected to scrambler 14 and channel interleaver 16.The sequence that is connected to channel interleaver 18 repeats and symbol perforation (symbol puncturing) parts 20, and business/control channel transmit signal path is extended to symbolic solution multiplexer 22, walsh codes parts 24, Walsh channel gain elements 26 and Walsh chip level adder 28.
MAC channel path among Figure 1A and the 1B comprises: preceding guiding path, and it comprises signaling point mapping means 30, multiplier 31 and sequence duplicate components 32; MAC RPC (reverse power control) path, it comprises signaling point mapping means 34, RPC Walsh channel gain elements 36 and multiplier 38; And MAC RA (reverse activity) path, it comprises (RABLENGTH) bit duplicate components 44, signaling point mapping means 46, RA channel gain component 48 and the multiplier 50 of the repetition factor with a plurality of RA bits.The RPC and the RA bit of multiplier 38 and 50 outputs make up in Walsh chip level adder 40, and Walsh chip level adder 40 is connected to the sequence duplicate components 42 with repetition factor 1.
In this pilot frequency channel signal path, signaling point mapping means 52 is connected to multiplier 54.
All above-mentioned signal paths are connected to adaptive multiplexer (TDM) 56, and it outputs to widening parts 58 with multiplexing signal.Baseband filter 60 and 62 is connected to widening parts 58, and the signal of filtering is outputed to multiplier 64,66.The baseband filter 60 and 62 of Fig. 1 typically is non-nyquist filter, and can have response for example shown in Figure 2.Combiner 68 combination is from the modulation signal of multiplier 64,66 outputs, and modulated waveform is outputed to antenna or other emitter assemblies with for example emission.
The signal that the emission chain operation of Figure 1A and 1B has structure shown in Figure 3 with generation, Fig. 3 is the block diagram that 1xEV-DO frame and structure of time slot are shown.The operation of the emission chain of Figure 1A and Figure 1B will become apparent to those skilled in the art that therefore this paper is not to this detailed description.
General introduction as mentioned, the downlink physical channel of 1xEV-DO takies the 1.25MHz frequency spectrum, spreading rate 1.2288Mcps, and the frame 70,72 that this physical channel is divided into 32768 chips or 26.67 milliseconds.Again each frame 70,72 is divided into length and is 16 time slots of 2048 chips or 1.67 milliseconds.With business, control, pilot tone and MAC channel multiplexing in time slot.Time slot shown in Fig. 2 is included in the control or the business datum of 400 chips of 74, is 76,96 pilot chip 78 of 64 MAC chips, 64 MAC chips 80 of another piece and 400 controls of another piece or professional chip 82 subsequently.This pattern repeats 84,86,88,90,92.Thus, per half time slot has 96 pilot chip, a 2*64 MAC chip and 800 control or professional chip 82.
Embodiments of the invention use frequency domain equalization to solve the various performance issues that are associated with the enforcement of 1xEV-DO terminal.In certain embodiments, similar to OFDM, convert multipath channel in the frequency domain single path.But well-known is that ofdm system changes into cyclical signal by using said identical Cyclic Prefix (Identical Cyclic Prefix) with signal, to realize the advantage of circular convolution.In CDMA technology, Cyclic Prefix in OFDM System is supposed from being false, because the CDMA signal is all the time by PN sequence scrambler.The frequency-domain equalizer that is proposed does not need this hypothesis.
Downlink throughput can improve by frequency-domain equalizer is provided, and causes ICI and stops the multipath distortion problem and the non-nyquist filter problem of the use of high level modulation with alleviation.
Utilize the downlink time slots structure to remove multipath in the frequency domain according to the frequency-domain equalizer of an embodiment, and use IFFT (invert fast fourier transformation) for example to convert the frequency domain data of equilibrium to time domain.Though specific example provided herein is applicable to 1xEV-DO, this standard all is incorporated into this paper by reference, is appreciated that application of the present invention is not limited to the context of this standard.
Fig. 4 is the block diagram of the structure of time slot of Fig. 3, and the data of buffering according to an embodiment of the invention are shown.As the skilled person will appreciate, receiving terminal is carried out as is obtained system, comprises frame regularly and the operation of slot timing, so that correctly detect the structure of time slot of Fig. 4.Therefore, receiving terminal can or be carried out these operations before the equalization operation that this paper describes in detail substantially simultaneously.Can also be before equilibrium under the prerequisite that does not deviate from the scope of the invention, simultaneously or carry out other operation afterwards.
In an illustrated embodiment, time slot comprises 400 control of the control of the control of 400 chips or business datum 100,64 MAC chip, 96 pilot chip 104,64 MAC chips 106 of another piece, 400 chips of another piece or business datum 108 and parallel pattern or 114,64 MAC chips 116 of 112,96 pilot chip of 110,64 MAC chips of professional chip and 400 control or professional chip 118, and buffering 1024 chips wherein are used for handling in FIFO (first in first out) register in the storage device for example.The data of buffering comprise control or the business datum part 108,110 between two adjacent pilot frequencies parts 104,114.Therefore preferably select buffer sizes and timer with the adaptive channel encoding block.The data of buffering comprise 48 pilot chip samples and 48 the pilot chip samples of rear end and 2 the MAC parts 106,112 that surround 2 business datum parts 108,110 of front end.
Though hereinafter mainly in the context of the data block of as shown in Figure 4 buffering, embodiments of the invention are described, but should be realized that and to use other buffering schemes to come balanced control or business module 100,108, for example to use the similar substantially mode of pilot chip 104 and MAC chip 102,106.
For simplicity, the complex data schedule of samples of buffering be shown r (0), r (1) ..., r (1023).Certainly, can use the sample of other quantity, though 2 power can be preferred.The time domain channel impulse response of estimating similarly be expressed as ch (0), ch (1) ..., ch (N), wherein select N to influence, and it is 14 in one embodiment with the target delay expansion (delay spread) and the non-Nyquist ICI of overlay environment.
Can at first extract the pilot portion that contains given data sequence or pattern from the data two ends of buffering.This can for example use the short scrambler of determining according to data block starting point index to realize.Suppose corresponding pilot tone scrambler section be respectively spn (0), spn (1) ..., spn (47) and spn (915), spn (916) ..., spn (1023), can be by following generation prefix z (N):
For n=0:N-1
Finish
With z (0) ..., z (N-1) replaces the sample that top n receives, the data of new buffering be z (0), z (1) ..., z (N-1), r (N) ..., r (1023).This expression is a kind of, and to be used for being that CDMA signal in the CDMA signal of emission and the reception of the linear convolution between the multipath communication channel changes into be new CDMA signal with the circular convolution of channel estimating.
More generally, in certain embodiments, the influence from the interference of preceding surface launching is generally MAC or pilot tone, by this interference of reconstruct and deduct it it is removed from the data of buffering.In some other embodiment, can also from the signal that receives, remove this known or repeating data sequence in the known portions of signal.
Preferably with channel tap ch (0), the ch (1) of reconstruct ..., ch (N) converts frequency domain to from time domain.In one embodiment, the identical DFT (discrete Fourier transform (DFT)) of data block size that in size and this example is 1024 buffering is used for time domain changes, though it is also contemplated that the conversion or the conversion of other types to frequency domain.The frequency domain components of channel tap be expressed as cf (0), cf (1) ..., cf (N-1), cf (N) ..., cf (1023) is used for hereinafter describing.
Also preferably use DFT or another conversion or the conversion data block that will receive and cushion to convert frequency domain to, with obtain rf (0), rf (1) ..., rf (N-1), rf (N) ..., rf (1023).In certain embodiments, the data block of this reception or its part can comprise the frequency domain components that can directly use in frequency domain equalization.For example, the symbolic solution multiplexer 22 launched in the chain of Fig. 1 converts frequency domain symbol to time domain.But, if frequency domain components is transmitted into receiver, then can avoid time domain to arrive at least a portion of frequency domain conversion at receiver, between reflector and receiver, effectively equilibrium treatment is split thus.On this meaning, reflector can aid in the processing operation that receiver is carried out.
Can wait the multi-path influence that reduces in the frequency domain by carrying out one by one multiple division of component (complex division) or Maximum Likelihood Detection then.Here we for example use simply again division to produce frequency domain representation re (k)=rf (the k)/cf (k) of equalizing signal.
Then can by data block re (0), re (1) ..., re (1023) go up to carry out IDFT (reverse DFT) or other and changes the data block of consequent equilibrium is changed back time-domain signal.The time domain output of conversion comprises balanced data flow, can handle it again for example to go scrambler and decoding then.
Therefore, more generally, can comprise the operation shown in the flow chart of Fig. 5 according to the method for the embodiment of the invention.The method of Fig. 5 relates to a balanced part of passing through the CDMA signal of multipath communication channel reception.This CDMA signal has data division and comprises the known portions of given data sequence.
Method 120 is included in 122 and determines the channel estimating of communication channel from this known portions.124, use this channel estimating to adjust the CDMA signal frequency-domain and represent to produce the frequency domain equalization signal.Adjustment 124 can comprise carries out the division of component one by one that CDMA signal frequency-domain for example represents to estimate divided by frequency domain channel to produce the frequency domain equalization signal.
Can channel estimating be defined as time domain channel 122 at first and estimate, and for example use DFT to convert frequency domain channel to then and estimate, for when 124 adjust frequency-region signals, using.
This method also preferably include will expression emission signal and the CDMA signal of the reception of the linear convolution between the multipath channel to change into be new CDMA signal with the circular convolution of channel estimating.Above-mentioned replacement or the known portions or its interference effect that remove the signal of reception are the examples that can be used to realize this transformed technology.This transformation function can also relate to time domain/frequency domain conversion, specifically depends on the territory that will carry out conversion.Preferably adjust consequent new CDMA signal 124 then.
In one embodiment, method also comprises the interference effect of use time domain channel estimation reconstruct known portions data portion and deducts the part of this interference effect with the interference compensation of generation CDMA signal from this data division.Converting the part of the interference compensation of this CDMA signal to frequency domain then represents to produce the CDMA signal frequency-domain.
According to a further embodiment of the invention, this method comprises at least some of known portions of replacing the CDMA signal with new portion, is the new CDMA signal of the circular convolution estimated with time domain channel so that the CDMA conversion of signals is become.Represent to produce the CDMA signal frequency-domain to the frequency domain conversion by on new CDMA signal, carrying out time domain.
In another embodiment of the present invention, represent to remove the influence of estimating the communication channel of expression as frequency domain channel from the CDMA signal frequency-domain.
Can also or replace and use time domain channel to estimate to remove the ISI influence to produce the CDMA signal of interference compensation, the CDMA conversion of signals of this interference compensation can be become frequency domain to represent to produce this CDMA signal frequency-domain from the CDMA signal.
Detailed consideration channel estimating more in the context of above-mentioned demonstration structure of time slot can have two pilot data pieces during each time slot, they can be used to estimate time domain channel impulse response.For illustrative purposes, suppose that the chip data { s (k) } of emission are by the multipath channel by the following formula definition
Random delay and Rayleigh fading are arranged on every paths.Channel impulse response ch (t) will be relatively stable in a complete time slot or half time slot.In this multipath channel, N is arranged
τIndividual active path.τ (l) is the delay of l paths, and α (l) is the respective channels gain that belongs to rayleigh distributed.Notice that all these delays will be referred to identical clock (for example system obtains the frame/boundary of time slot of catching afterwards).
In receiving terminal one side, the baseband signal that receives can be modeled as:
N (t) represents noise.
Suppose that sampling rate is Mf
c, it represents each chip M sample.Refer to that at the synchronization of modules of receiving terminal or rake detection module will find shortest path, illustrate that with No. 2 paths any paths all can be the shortest certainly, regularly/rake refers to be cited as τ ' (2), it can with Mf
cIndex is directly relevant.Note Δ=τ ' (2)-τ (2) because the reason of sampling resolution can be non-vanishing, but less Δ generally is preferred.Be reduced to 1f
cSampling obtains
Notice that clock only locks onto (open eye) some τ ' (2) that widens the view now.If this widens the view accurately, then Δ will disappear.Otherwise Δ will influence every other path.In force, still can quote frame/boundary of time slot by the conversion relative timing.
For the purpose of channel reconstruction, observed data { r (k) } can be used for whole channel reconstruction be
The quantity of supposing channel tap is N+1 and ch (m)=0, and when m<0 and m>N, then above-mentioned equation can be expressed as simply again
This equation is the basis of LMS (lowest mean square) channel estimating.As mentioned above, { r (k) } is the data sequence and the known array of periodic transmission and the reception that therefore is received at receiving terminal.
We suppose from index K now
1Begin to launch the part of known chip sequence, and known chip K in the end
2Finish.From previous equation, the data sequence r (K of Jie Shouing as can be seen
1+ N) ..., r (K
2) be the s (K that is attributable to known array fully
1) ..., s (K
2) unique part.Therefore can also regularly derive reflector regularly from the data that receive, obtain the linear equality of the reduction of following previous equation based on this part of using known array:
k=K
1+N,...,K
2。
In matrix form,
This group linear equality has N+1 unknown quantity and (K
2-K
1-N) individual equation.Specifically, in two pilot blocks of above-mentioned example, for 96 continuous known pilot chips, we have (96-N) individual equation, as shown in Figure 6.Curve shown in Figure 6 illustrates receiver regularly to reflector regularly, and the catching of whole multipath impulse response of using relative timing.Two parts of given data can be interlocked, and can obtain two equatioies like this, and by that analogy, or can carry out channel estimating substantially individually based on each known portions, these mean values of estimating channel are used as final channel estimating.
In any situation, need during channel estimating, separate as above-mentioned those general linear equality.Because noise, these equatioies are preferably separated by the LMS method.Explicit solution can be expressed as
Wherein
The more effective means that derivation is separated is directly to separate following linear equality:
Coefficient matrix that it should be noted that this linear equality is integer Hermetian (Hermitian) matrix of (N+1) * (N+1) dimension.Can use Cholesky or SVD (singular value decomposition) method to separate these linear equalities.The specific decomposition method that uses is a design option.Therefore on the other hand, matrix S is only relevant with scrambler and can describe with formula after just setting up communication link in certain embodiments.This decomposition also preferably each link only carry out once, and till using link and stopping.
Can use time domain channel to estimate to carry out time domain equalization, though the complexity of time domain equalization estimates to be about 8 times of complexity of frequency domain equalization.
In the embodiment of the invention described above, equilibrium relates to multiple division, and wherein the little value of cf (k) may strengthen noise.Though above-mentioned division has been simplified enforcement, it may not be optimum in noise and fading environment are arranged.For example, multipath channel may have null value or trap (notch) in frequency domain.Unlike OFDM, this noise strengthens the follow-up IFFT result of influence, and therefore it may represent global impact.In order to alleviate this deficiency, can use other technologies hereinafter described, can be higher though implement complexity.
Suppose that β is the predetermined threshold of the system tolerance of reflection noise enhancing.Can then frequency tone be categorized into two groups, promptly " good " or melodious group of Ω and " poor " or unmelodious group Ψ are defined as them
Ω={k‖cf(k)|>β},Ψ={k‖cf(k)|≤β}。
Obviously, good sound k ∈ Ω will can not strengthen noise, or strengthen by permissible amount, so that equalizer can use above-mentioned multiple division scheme, and bad sound k ∈ Ψ will too much strengthen noise, and this division is infeasible thus.
In one embodiment, for k ∈ Ψ, each rf (k) multiply by β.According to another embodiment, determine weight and be applied to the component rf (k) of k ∈ Ψ.
The definition of demonstration weight calculation technology
Note, spn (0), spn (1) ..., spn (47) is the known pilot chip before the data block of buffering.The separating of following double optimization provides optimum weights omega.
If the quantity of bad sound is less than certain number, 48 (can use last 48 known chips to handle maximum 96 bad sounds) for example, above-mentioned optimization has the unique solution that obtains by following explicit formula
E wherein
ΨBe by rf (k) and
The matrix that forms, wherein k ∈ Ψ and m=0,1 ..., 47.Note matrix E
ΨHave very special structure, and therefore can be very effectively with its inversion.After this computation optimization, balanced block of frequency domain data becomes
Re (k)=rf (k)/cf (k), k ∈ Ω and re (k)=ω (k) rf (k), k ∈ Ψ.
The block length of previous weight calculation equation 1024 chips of supposition and the buffering of 48 pilot chip.But, should be realized that the present invention is in no way limited to these length-specifics.In general, can calculate weight with block length b in similar substantially mode to any known data patterns length a.
Fig. 7 is the block diagram that can implement the system of the embodiment of the invention.This system comprises the communication equipment 130,132 that connects by communication link 131.But will be obvious that for those skilled in the art communication system can comprise than two covers can set up many communication equipments that the communication equipment of communication is Duoed therebetween.
Though Fig. 7 is depicted as connection, it is physical connection that link 131 not necessarily needs.For example, in one embodiment, communication equipment 130 and 132 is respectively network element and the communication terminal in the wireless communication system.It is directly to connect and can comprise connection by for example one or more networks or intermediary's assembly that link 131 also need not.
Communication equipment 130 comprises processor 136 and the transceiver 140 that is connected with memory 134.Communication equipment 132 has similar structure, comprises the processor 144 and the transceiver 142 that are connected with memory 146.Should be realized that other assemblies those that clearly illustrate can be provided, and this depends on the particular type of communication equipment 130,132 in Fig. 7.Have identical general structure though should also be noted that communication equipment 130,132 in Fig. 7, embodiments of the invention can be implemented in conjunction with different substantially communication equipments.In the example of said network element and communication terminal, processor, memory and the transceiver shown in network element and communication terminal can comprise, but in other situations then be very different equipment.
Processor 136 can be to carry out the microprocessor that is stored in the software in the memory 134.Processor 136 can change into and be embodied as microcontroller, DSP (digital signal processor), ASIC (application-specific integrated circuit (ASIC)) or other processing unit.The processor that can use application specific processor or also carry out other functions is implemented the embodiment of the invention.For example, processor 136 can executive operating system software and software application support non-those function disclosed herein.
Memory 134 expression storage devices and can comprise that for example solid-state storage device, dish drive and other storage devices of being suitable for operating with fixing or removable storage medium in any device.
Transceiver 140 allows communicating by letter via communication link 131 and communication equipment 132.Many dissimilar transceivers 140 will be obvious for those skilled in the art, and they use in conjunction with the communication link of corresponding types.Also imagine transceiver 140 and comprise that assembly is to allow the embodiment by the communication of polytype communication link.Should be realized that the present invention never is limited in conjunction with communication equipment that can two-way communication and implements.Therefore, balancing technique disclosed herein can be implemented at the communication equipment that comprises receiver rather than transceiver 140.Similarly, the transmitting terminal function can be carried out at the communication equipment that only comprises reflector.
Processor 144 in the communication equipment 132, transceiver 142 and memory 146 can be substantially to above-mentioned communication equipment 130 in processor 136, memory 134 similar with transceiver 140.
In operation, the emission communication equipment illustrates with communication equipment 130, generates the CDMA signal to be transmitted into received communication equipment, illustrates with communication equipment 132.Because communication equipment 130,132 comprise can transmitt or receive signal transceiver 140,142, so these demonstration titles of reflector and receiver are only for purpose of explanation.In the system of Fig. 7, signal of communication can send with any one direction on link 131.
The above-mentioned example that will transmit to communication equipment 132 according to communication equipment 130, by the software in the execute store 134 for example processor 136 is configured to receive data to be launched from input, and these data and known or repeating data sequence are multiplexed in the CDMA signal.Export this CDMA signal then and be used for emission.Signal can be launched when output signal substantially in real time, or time emission after a while, and signal can for example be stored in the memory 134 in the case.Multiplexing data can comprise time domain component and/or frequency domain components.As mentioned above, in frequency domain components is multiplexed into situation in the CDMA signal, reduced with frequency domain equalization before carry out the treating capacity that time domain is associated to frequency domain conversion at receiver.In one embodiment, processor 136 is implemented transform engine, illustrates with IDFT or IFFT engine, converts the time domain component to the frequency domain components that is used for generating during the digital coding.
At received communication equipment 132, processor 144 is configured to receive the CDMA signal from the input that can be connected to transceiver 142, determining that from the given data sequence frequency domain channel estimates, and be configured to use frequency domain channel to estimate to adjust the CDMA signal frequency-domain to represent to produce the frequency domain representation of equalizing signal.The configuration of processor 144 with regard to above-mentioned processor 136, can realize to be carried out by processor 144 by software for example is provided in memory 146.
Processor 144 can estimate to convert to corresponding frequency domain components with time domain component or definite time domain channel of the CDMA signal that receives.This translation function can be supported by the transform engine of for example implementing in the software of memory 146 such as DFT or FFT engine.Balanced frequency-region signal can similarly be provided by for example IDFT or IFFT engine to the conversion of time domain.
Memory 146 can also be used to store CDMA signal or its part.With reference to figure 4, in one embodiment of the invention, 1024 chips of the CDMA signal that receives are stored in the memory 146.
Can also carry out other functions by processor 136 and 144, comprise aforesaid additional equalization function and/or other signal processing function, as go scrambler and conventional CDMA signal decoding with the data of recovering and output is launched.Can provide independent processor or functional part to be used for equilibrium, remove scrambler, decoding and other operations.Therefore, though only show a processor among Fig. 7 in the communication equipment 130,132, can with one or more implement balanced, go scrambler, decoding and other to receive operation and the one or more parts of implementing respective operations on the emission communication equipment are implemented embodiments of the invention.
In a preferred embodiment of the invention, the forward link in the cordless communication network is implemented frequency domain equalization, so that supporting firing operation and receiving operation in the communication terminal support as the network element of base station.But frequency domain equalization can also or change on reverse link and implementing.
Embodiments of the invention can be added in the existing communication equipment, for example, convert DFT/IDFT or the FFT/IFFT that frequency domain carries out equilibrium and equalizing signal converted to time domain from frequency domain to from time domain such as being used for by comprising extra mapping function.This can be integrated on the existing chip or in independent chip provides.Can make up with certain of hardware, software or they and implement it.
Foregoing only is the explanation to the application of the principles of the present invention.Under the prerequisite that does not deviate from the scope of the invention, those skilled in the art can also implement other layouts and method.
For example,, also imagine other enforcements of the present invention, as be stored in the instruction on the computer-readable medium though mainly be in the context of method and system, to describe.