CN1956046A - Shift scratch system, method and liquid crystal display driving circuit - Google Patents
Shift scratch system, method and liquid crystal display driving circuit Download PDFInfo
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- CN1956046A CN1956046A CN 200510100768 CN200510100768A CN1956046A CN 1956046 A CN1956046 A CN 1956046A CN 200510100768 CN200510100768 CN 200510100768 CN 200510100768 A CN200510100768 A CN 200510100768A CN 1956046 A CN1956046 A CN 1956046A
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Abstract
A shift scratch system comprises a shift buffer including initial pulse end, multiple output end and a control end; a counter including multiple output end, a signal receiving end and pulse output end; a level shifter including multiple output end and multiple input end; multiple switching element as each element including multiple input end, multiple output end and an opening/closing end. The chip area can be greatly reduced by applying said system so that production cost can be decreased much.
Description
[technical field]
The present invention relates to a kind of shift scratch system.
[background technology]
Because advantages such as LCD has gently, approaches, power consumption is little, so be widely used in fields such as portable DVD player, PDA(Personal Digital Assistant), visual music player, mobile phone and notebook computer.Usually, LCD comprises and is multi-strip scanning line and many data lines that ranks are arranged, and a plurality of pixels, is positioned at this sweep trace with the data line infall and the control circuit that is used to drive a plurality of switches of these a plurality of pixels, the scan drive circuit that is connected with the multi-strip scanning line, the data drive circuit that is connected with many data lines, is used to control this scan drive circuit and this data drive circuit.This scan drive circuit and this data drive circuit are used for these a plurality of pixels of these a plurality of switch drive of control, to realize these a plurality of pixel display images.
Wherein, offset buffer is widely used in scan drive circuit and the data drive circuit, offset buffer in the scan drive circuit of LCD passes through sweep trace output scanning signal line by line, and the data drive circuit of LCD is used for picture signal is write data line by offset buffer.
Seeing also Fig. 1, is a kind of synoptic diagram of prior art LCD.Do not comprise on the glass substrate of this LCD 100 (figure show): n horizontal scanning line 101, m column data line 102, be positioned at a plurality of thin film transistor (TFT)s (Thin FilmTransistor of sweep trace 101 and data line 102 infalls, TFT, figure does not show), a plurality of pixel (figure do not show), scan drive circuit 110, data drive circuit 120 and controller 130.These a plurality of pixels constitute a viewing area 107.Each pixel comprises a pixel electrode 103, a public electrode 105 and is sandwiched in two liquid crystal molecules (figure does not show) between the electrode.Each pixel electrode 103 is connected with a data line 102 with one scan line 101 respectively by a thin film transistor (TFT).Data drive circuit 120 comprises an offset buffer (ShiftRegister) 121, a sampling controller 122 and an output buffer (Output Buffer) 123.Scan drive circuit 110 comprises an offset buffer 111, one level shifters (Level Shifter) 112 and one output buffer 113.
Wherein, to drive pixel electrode 103, public electrode 105 is positioned at the opposite of pixel electrode 103 to thin film transistor (TFT) as switch, and a common fixed voltage Vc is applied to public electrode 105; Scan drive circuit 110 and data drive circuit 120 drive n horizontal scanning line 101 and m column data line 102 respectively; Data drive circuit 120 by offset buffer 121 sampled image signals after sampling controller 122 and output buffer 123 provide it to data line 102, scan drive circuit 110 is successively by offset buffer 111, level shifter 112 and output buffer 113 output scanning pulses are to sweep trace 101, and controller 130 is provided for time signal and other signal of gated sweep driving circuit 110 and data drive circuit 120.
[summary of the invention]
In order to solve offset buffer cost problem of higher in the prior art, be necessary to provide a kind of lower-cost shift scratch system.
In order to solve offset buffer cost problem of higher in the prior art, be necessary to provide a kind of lower-cost shift register method.
In order to solve liquid crystal display drive circuit cost problem of higher in the prior art, be necessary to provide a kind of lower-cost liquid crystal display drive circuit.
A kind of shift scratch system, it comprises an offset buffer, a counter, a level shifter and a plurality of on-off element.This offset buffer comprises: one is used to receive the initial pulse end of external signal, a plurality of output terminals that are used to export the external signal that receives and a control end.This counter comprises a plurality of output terminals, a signal receiving end that is connected with the control end of this offset buffer and a pulse output end that is connected with the initial pulse end of this offset buffer.This level shifter comprises a plurality of output terminals and is connected to a plurality of input ends of a plurality of output terminals of this offset buffer.A plurality of output terminals that each on-off element comprises a plurality of input ends of being connected to a plurality of output terminals of this level shifter, be connected with external circuit with one with one of them open and close end that is connected of a plurality of output terminals of this counter.
A kind of shift register method, constitute the shift scratch system of n * m output terminal by an individual on-off element of offset buffer, a counter and m (m 〉=1) with the individual output terminal of n (n 〉=1), this method comprises the steps: step 1, adopts offset buffer to receive external signal; Step 2 adopts counter to receive outside initial pulse, and (1≤j≤m) individual on-off element triggers and is opening, and remaining on-off element is a closed condition with this offset buffer and j simultaneously; Step 3, the signal of n output terminal output of this offset buffer offers this level shifter, this level shifter moves to required level with level, and this level shifter offers this j+1 on-off element with this required level then, and by this j+1 on-off element output; Step 4, (1≤i≤n) is after the individual clock period for i when j on-off element is in opening, this counter produces a pulse and to this j+1 on-off element its triggering is opening, remaining on-off element is a closed condition, the signal of the n of this offset buffer output terminal output offers this j+1 on-off element, and by this j+1 on-off element output; Step 5, after m on-off element finished required level output, this counter produced a pulse to this offset buffer, and this offset buffer is output signal again.
Another kind of shift scratch system, it comprises an offset buffer, a level shifter and a plurality of on-off element.This offset buffer comprises a plurality of input ends that are used to receive external signal; Be used to export a plurality of output terminals of the external signal that is received; One initial pulse end is used to receive outside initial pulse; One resets end; Two control ends, it connects and is used to control the external signal that these a plurality of output terminals are periodically exported this a plurality of input end and received.This level shifter comprises a plurality of output terminals and is electrically connected to a plurality of input ends of a plurality of output terminals of this offset buffer.These a plurality of on-off elements comprise a plurality of input ends, a plurality of output terminal, an open and close end and a control end respectively.Wherein, these a plurality of on-off elements are connected successively, except that being connected serially to last on-off element, the control end of each on-off element is connected to the open and close end of the on-off element that is series at thereafter, this control end that is connected serially to last on-off element is connected with the end of reseting of this offset buffer, and first is connected with the initial pulse end of this offset buffer by the open and close end of switch in series; The input end of these a plurality of on-off elements is electrically connected with a plurality of output terminals of this level shifter by a bus, the input end of this level shifter connects respectively at a plurality of output terminals of this offset buffer, by this, shift scratch system expands to self many times, these the many times quantity that depend on on-off element with the quantity of this offset buffer output terminal.
Another kind of shift register method, comprise with this method of shift scratch system that formation has n * m output terminal by an offset buffer and an individual on-off element of m (m 〉=1) with the individual output terminal of n (n 〉=1): step 1 receives an external signal and an outside initial pulse; Step 2, by this outside initial pulse trigger this offset buffer and j (the individual on-off element of 1≤j≤m), it is closed condition that this j on-off element is triggered remaining on-off element of opening; Step 3, be in the i (i 〉=1) of opening after the individual clock period at j on-off element, this offset buffer is provided to this level shifter by n the output terminal of self with the external signal that is received, this level shifter moves to required level with level, this level shifter offers j on-off element with this required level then, and by this j on-off element output; Step 4, when i clock period that j on-off element is in opening finished, it was opening to this j+1 on-off element with its triggering that this j on-off element produces a pulse, remaining on-off element is a closed condition; Step 5, this offset buffer is provided to this level shifter by n the output terminal of self with the external signal that is received, this level shifter moves to required level with level, this level shifter offers this j+1 on-off element with this required level then, and by this j+1 on-off element output.After m on-off element finished signal output, this m on-off element produced a pulse to this offset buffer, and this offset buffer stops output signal.
A kind of liquid crystal display drive circuit, it comprises the control circuit that is multi-strip scanning line that ranks arrange and many data lines, the scan drive circuit that is connected with the multi-strip scanning line, the data drive circuit that is connected with many data lines, is used to control this scan drive circuit and this data drive circuit.This scan drive circuit comprises a shift scratch system, and it comprises an offset buffer, a counter, a level shifter and a plurality of on-off element.This offset buffer comprises that one is used to receive the initial pulse end of external signal, a plurality of output terminals that are used to export the external signal that receives and a control end.This counter comprises a plurality of output terminals, a signal receiving end that is connected with the control end of this offset buffer and a pulse output end that is connected with the initial pulse end of this offset buffer.This level shifter comprises a plurality of output terminals and is connected to a plurality of input ends of a plurality of output terminals of this offset buffer.A plurality of output terminals that each on-off element comprises a plurality of input ends of being connected to a plurality of output terminals of this level shifter, be connected with external circuit with one with a plurality of output terminals of this counter one of them open and close end that is connected.
Another kind of liquid crystal display drive circuit, it comprises the control circuit that is multi-strip scanning line that ranks arrange and many data lines, the scan drive circuit that is connected with the multi-strip scanning line, the data drive circuit that is connected with many data lines, is used to control this scan drive circuit and this data drive circuit.This scan drive circuit comprises a kind of shift scratch system, and it comprises an offset buffer, a level shifter and a plurality of on-off element.This offset buffer comprises a plurality of input ends, is used to receive external signal; A plurality of output terminals are used to export the external signal that this a plurality of input end receives; One initial pulse end is used to receive outside initial pulse; One resets end; Two control ends, it connects and is used to control the external signal that these a plurality of output terminals are periodically exported this a plurality of input end and received.This level shifter comprises a plurality of input ends and a plurality of output terminal that is electrically connected to this offset buffer output terminal.These a plurality of on-off elements comprise a plurality of input ends, a plurality of output terminal, an open and close end and a control end respectively.Wherein, these a plurality of on-off elements are connected successively, except that being connected serially to last on-off element, the control end of each on-off element is connected to the open and close end of the on-off element that is series at thereafter, this control end that is connected serially to last on-off element is connected with the end of reseting of this offset buffer, and first is connected with the initial pulse end of this offset buffer by the open and close end of switch in series; The input end of these a plurality of on-off elements is connected with a plurality of output terminals of this level shifter by a bus, and a plurality of input ends of this level shifter connect respectively at a plurality of output terminals of this offset buffer.
Another shift scratch system, it comprises an offset buffer, and it comprises at least one input end and a plurality of output terminal, and these a plurality of output terminals are used to export the external signal that this input end receives; One level shifter, it comprises a plurality of input ends and a plurality of output terminal, the corresponding a plurality of output terminals that are connected to this offset buffer of these a plurality of input ends; A plurality of on-off elements, each on-off element comprise a plurality of input ends and a plurality of output terminal, and these a plurality of input ends are distinguished corresponding electrical connection with a plurality of output terminals of this level shifter; Wherein, the input end of this offset buffer receives external signal and transmits this external signal to this level shifter, and this level shifter is converted into required level with the external signal that is received, then successively by these a plurality of on-off element outputs.
Another shift register method, come the output of realization data by an individual on-off element of offset buffer, a level shifter and m (m 〉=1) with the individual output terminal of quantity n (n 〉=1) with the shift scratch system that constitutes n * m output terminal, this method comprises: adopt an offset buffer to receive external signal; The signal of the n of this offset buffer output terminal output offers this level shifter, and this level shifter moves to required level with level; This m on-off element is triggered opening successively, and when file one on-off element was triggered opening, remaining on-off element was a closed condition; This level shifter offers this m on-off element successively with this required level, and exports successively by this m on-off element.
Another liquid crystal display drive circuit, it comprises many sweep traces that are arranged in parallel; Many are arranged in parallel and the data line vertical with this sweep trace; A plurality of pixels; The data drive circuit that is connected with many data lines; The scan drive circuit that is connected with the multi-strip scanning line, it comprises a shift scratch system, this shift scratch system comprises an offset buffer, and it comprises at least one input end and a plurality of output terminal, and these a plurality of output terminals are used to export the external signal that this input end receives; One level shifter, it comprises a plurality of input ends and a plurality of output terminal, the corresponding a plurality of output terminals that are connected to this offset buffer of these a plurality of input ends; A plurality of on-off elements, each on-off element comprise a plurality of input ends and a plurality of output terminal, and these a plurality of input ends are distinguished corresponding electrical connection with a plurality of output terminals of this level shifter; Wherein, the input end of this offset buffer receives external signal and transmits this external signal to this level shifter, and this level shifter is converted into required level with the external signal that is received, then successively by these a plurality of on-off element outputs.
Compared to prior art, the shift scratch system that adopts in above-mentioned shift scratch system, method and the liquid crystal display drive circuit is by a plurality of on-off elements, cooperate offset buffer with less output port and the shift scratch system that level shifter constituted with more output port with less output port, have than the offset buffer of multiport and have level shifter compared to tradition than multiport, its shared chip space is less, therefore can reduce cost.
[description of drawings]
Fig. 1 is a kind of synoptic diagram of LCD of prior art.
Fig. 2 is the synoptic diagram of shift scratch system first embodiment of the present invention.
Fig. 3 is the drive waveforms synoptic diagram of shift scratch system shown in Figure 2.
Fig. 4 is the synoptic diagram that the present invention adopts a kind of liquid crystal display drive circuit of shift scratch system shown in Figure 2.
Fig. 5 is the synoptic diagram of shift scratch system second embodiment of the present invention.
[having the body embodiment]
Seeing also Fig. 2, is the synoptic diagram of shift scratch system first embodiment of the present invention.This shift scratch system 200 comprises an offset buffer 210, a counter 270, a level shifter 220, one first on-off element 230, a second switch element 240, one the 3rd on-off element 250 and one the 4th on-off element 260.This offset buffer 210 comprises 64 output terminals being made up of 64 buffer units (figure does not show), and a control end STV2 and is used for the initial pulse end STV1 of received signal.This counter 270 comprises a signal receiving end STV, a pulse output end a and four open and close signal output part b1, b2, b3, b4.This signal receiving end STV is connected with the control end STV2 of this offset buffer 210, and this pulse output end a is connected with the initial pulse end STV1 of this offset buffer 210.This level shifter 220 comprises 64 output terminals and is connected to 64 input ends of 64 output terminals of this offset buffer 210.These four groups of on-off elements 230,240,250,260 comprise respectively: 64 input ends, 64 output terminals and an open and close end on/off.In these four groups of on-off elements 230,240,250,260, the open and close end on/off of first on-off element 230 is connected with the open and close signal output part b1 of this counter 270, the open and close end on/off of second switch element 240 is connected with the open and close signal output part b2 of this counter 270, the open and close end on/off of the 3rd on-off element 250 is connected with the open and close signal output part b3 of this counter 270, and the open and close end on/off of the 4th on-off element 260 is connected with the open and close signal output part b4 of this counter 270.The input end of these four groups of on-off elements 230,240,250,260 is connected with the output terminal of this level shifter 220 by a bus with 64, the output terminal of these four groups of on-off elements 230,240,250,260 is connected with external circuit (figure does not show), in order to outputs level signals.
Seeing also Fig. 3, below is that example is introduced its shift register method with 256 level signals of shift scratch system 200 output.The counter 270 of shift scratch system 200 receives outside initial pulse, the starting end a of this counter 270 transmits the initial pulse end STV1 of 1-64 pulse to offset buffer 210 then, and the output terminal b1 of this counter 270 transmits the open and close end on/off of a pulse to first on-off element 230 simultaneously.This first on-off element 230 is an opening by the trigger action that this counter 270 output terminal b1 transmit, and second switch element 240, the 3rd on-off element 250 and the 4th on-off element 260 are in closed condition owing to not being triggered at this moment.1-64 pulse that the control end STV1 of this offset buffer 210 receives successively that this counter 270 starting end a transmit also is transferred to this level shifter 220 with 1-64 the shift pulse that is received, this level shifter 220 produces 64 required current potentials according to this 1-64 shift pulse, and outputs to first on-off element 230 by bus.The required level that these first on-off element, 230 incoming level shift units 220 produce also is provided to external circuit, i.e. waveform shown in S1.1～S1.64 among Fig. 3.
After 63 clock period, a control end STV2 of this offset buffer 210 end is sent the control end STV end of a pulse to this counter 270.The starting end a of this counter 270 transmits the initial pulse end STV1 of 65-128 pulse to offset buffer 210 then, and the output terminal b2 of this counter 270 transmits the open and close end on/off of a pulse to second switch element 240 simultaneously.This second switch element 240 is an opening by the trigger action that this counter 270 output terminal b2 transmit, and first on-off element 230, the 3rd on-off element 250 and the 4th on-off element 260 are in closed condition owing to not being triggered at this moment.65-128 pulse that the control end STV1 of this offset buffer 210 receives successively that this counter 270 starting end a transmit also is transferred to this level shifter 220 with 65-128 the shift pulse that is received, this level shifter 220 produces 64 required level according to this 65-128 shift pulse, and outputs to second switch element 240 by bus.The required level that these second switch element 240 incoming level shift units 220 produce also is provided to external circuit, i.e. waveform shown in S2.1～S2.64 among Fig. 3.
Through after 63 clock period, a control end STV2 of this offset buffer 210 end is sent the control end STV end of a pulse to this counter 270 again.The starting end a of this counter 270 transmits the initial pulse end STV1 of 129-192 pulse to offset buffer 210 then, and the output terminal b3 of this counter 270 transmits the open and close end on/off of a pulse to the three on-off elements 250 simultaneously.The 3rd on-off element 250 is an opening by the trigger action that this counter 270 output terminal b3 transmit, and first on-off element 230, second switch element 240 and the 4th on-off element 260 are in closed condition owing to not being triggered at this moment.129-192 pulse that the control end STV1 of this offset buffer 210 receives successively that this counter 270 starting end a transmit also is transferred to this level shifter 220 with 129-192 the shift pulse that is received, this level shifter 220 produces 64 required level according to this 129-192 shift pulse, and outputs to the 3rd on-off element 250 by bus.The required level that the 3rd on-off element 230 incoming level shift units 220 produce also is provided to external circuit, i.e. waveform shown in S3.1～S3.64 among Fig. 3.
Through after 63 clock period, a control end STV2 of this offset buffer 210 end is sent the control end STV end of a pulse to this counter 270 again.The starting end a of this counter 270 transmits the initial pulse end STV1 of 193-256 pulse to offset buffer 210 then, and the output terminal b4 of this counter 270 transmits the open and close end on/off of a pulse to the four on-off elements 260 simultaneously.The 4th on-off element 260 is an opening by the trigger action that this counter 270 output terminal b4 transmit, and first on-off element 230, second switch element 240 and the 3rd on-off element 250 are in closed condition owing to not being triggered at this moment.193-256 pulse that the control end STV1 of this offset buffer 210 receives successively that this counter 270 starting end a transmit also is transferred to this level shifter 220 with 193-256 the shift pulse that is received, this level shifter 220 produces 64 required level according to this 193-256 shift pulse, and outputs to the 4th on-off element 260 by bus.The required level that the 4th on-off element 230 incoming level shift units 220 produce also is provided to the outside, i.e. waveform shown in S4.1～S4.64 among Fig. 3.
Through after 63 clock period, a control end STV2 of this offset buffer 210 end is sent the control end STV end of a pulse to this counter 270 again.Behind the 5th received pulse of this counter 270, when if it transmits this offset buffer 210 of trigger action at this moment, this offset buffer 210 produces displacement output again in the manner described above, and these four groups of on-off elements 230,240,250,260 are docile and obedient preface and are exported required level; If it no longer transmits this offset buffer 210 of trigger action, then this offset buffer 210 no longer produces displacement output.In sum, the shift scratch system 200 with offset buffer 210 of 64 output terminals expands to 256 output ports.
Seeing also Fig. 4, is the synoptic diagram that the present invention adopts a LCD of shift scratch system 200.Do not comprise on the glass substrate of this LCD 400 (figure show): n horizontal scanning line 460, m column data line 470, be positioned at a plurality of thin film transistor (TFT)s (figure does not show), a plurality of pixel 410, scan drive circuit 420, data drive circuit 430 and the controller 440 of sweep trace 460 and data line 470 infalls.These a plurality of pixels 410 constitute a viewing area 450.Each pixel 410 comprises a pixel electrode (figure does not show), a public electrode (figure does not show) and is sandwiched in two liquid crystal molecules (figure does not show) between the electrode.Each pixel electrode is connected with a data line 470 with one scan line 460 by a thin film transistor (TFT).Scan drive circuit 420 comprises shift scratch system 200 as shown in Figure 2, and it is used to drive n horizontal scanning line 460.The internal circuit of data drive circuit 430 is identical with tradition, and it is used to drive m column data line 470.Controller 440 produces initial pulse signal and clock signal, and is used for gated sweep driving circuit 420 and data drive circuit 430.This thin film transistor (TFT) is made up of polysilicon.
Shift scratch system 200 of the present invention also can omit counter 270 and reach same effect, and only, its circuit connects slightly different.
Seeing also Fig. 5, is the synoptic diagram of shift scratch system second embodiment of the present invention.This shift scratch system 500 comprises an offset buffer 510, a level shifter 520, one first on-off element 530, one second switch elements 540, the 3rd on-off element 550 and one the 4th on-off element 560 with 64 output terminals.This offset buffer 510 comprises 64 buffer units (figure does not show), initial pulse end STV1, end Reset, control end FB and control end STV2 reset.This level shifter 520 comprises 64 output terminals and is electrically connected to 64 input ends of 51064 output terminals of this offset buffer.These four groups of on-off elements 530,540,550,560 comprise an open and close end, a control end, 64 input ends and 64 output terminals respectively; In these four groups of on-off elements 530,540,550,560, except that the 4th on-off element, each on-off element is connected with the open and close end on/off of on-off element thereafter by its control end STV, the open and close end on/off of this first on-off element 530 is connected with the outside initial pulse end STV1 of this offset buffer 510, and the control end STV of the 4th on-off element 560 is connected with the end Reset that resets of this offset buffer 510; The input end of these four groups of on-off elements 530,540,550,560 is electrically connected by 64 output terminals of one 64 these these level shifters 520 of bus, 64 output terminals of these four groups of on-off elements 530,540,550,560 are connected with external circuit (figure does not show), in order to export required level.
Seeing also Fig. 3, below is the shift register method that example is introduced this shift scratch system 500 with 256 required level of shift scratch system 500 output.
At first, an open and close end on/off of the initial pulse end STV1 of its inner offset buffer 510 and first on-off element 530 receives the initial pulse signal of external circuit.Triggering behind the initial pulse signal of the open and close end on/off reception external circuit of this first on-off element 530 is opening, and this moment, remaining switch 540,550,560 was a closed condition.This offset buffer 510 produces 1-64 shift pulse and is transferred to this level shifter 520 after receiving initial pulse signal, this level shifter 520 produces 64 required level according to this 1-64 shift pulse, and outputs to first on-off element 530 by bus.The required level that these first on-off element, 530 incoming level shift units 520 produce also is provided to external circuit, i.e. waveform shown in S1.1～S1.64 among Fig. 3.
After 63 clock period, the one control end STV2 end of this offset buffer 510 is sent a pulse to its another control end FB, simultaneously, this first on-off element 530 is sent a pulse synchronously to trigger second switch element 540 and to change himself into closed condition.The open and close end on/off of second switch element 540 receives to trigger after the pulse that first on-off element 530 sends and is opening, and this moment, remaining switch 530,550,560 was a closed condition.This offset buffer 510 produces 65-128 shift pulse and is transferred to this level shifter 540, and this level shifter 520 produces 64 required level according to this 65-128 shift pulse, and outputs to second switch element 540 by bus.The required level that these second switch element 540 incoming level shift units 520 produce also is provided to external circuit, i.e. waveform shown in S2.1～S2.64 among Fig. 3.
After 63 clock period, the one control end STV2 end of this offset buffer 510 is sent a pulse to its another control end FB, simultaneously, this second switch element 540 is sent a pulse synchronously to trigger the 3rd on-off element 550 and to change himself into closed condition.Triggering after the pulse that the open and close end on/off reception second switch element 540 of the 3rd on-off element 550 is sent is opening, and this moment, remaining switch 530,540,560 was a closed condition.This offset buffer 510 produces 129-192 shift pulse and is transferred to this level shifter 520, and this level shifter 520 produces 64 required level according to this 129-192 shift pulse, and outputs to the 3rd on-off element 550 by bus.The required level that the 3rd on-off element 5 50 incoming level shift units 520 produce also is provided to external circuit, i.e. waveform shown in S3.1～S3.64 among Fig. 3.
In like manner, again through after 63 clock period, this offset buffer 510 produces 129-192 shift pulse and is transferred to this level shifter 520, this level shifter 520 produces 64 required level according to this 129-192 shift pulse, and outputs to the 4th on-off element 560 by bus.The required level that the 4th on-off element 560 incoming level shift units 520 produce also is provided to external circuit, i.e. waveform shown in S4.1～S4.64 among Fig. 3.When the output of the 4th on-off element 560 finishes, promptly through after 63 clock period, it is sent a pulse and closes self, and thus, the shift scratch system 500 with offset buffer 510 of 64 output ports expands to 256 output ports.
This offset buffer 510 will stop output signal after receiving the pulse that the 4th on-off element 560 sends, and receive the initial pulse signal of external circuit again until an open and close end on/off of the initial pulse end STV1 of offset buffer 510 and first on-off element 530.
The present invention also provides a kind of LCD that adopts shift scratch system 500.This LCD and this LCD 400 differences are: its scan drive circuit comprises shift scratch system 500 as shown in Figure 5.
In addition, the output terminal of the offset buffer 210,510 of shift scratch system of the present invention 200,500 inside is not limited to 64, can enlarge or dwindle the quantity of its output terminal as required, if it is 128 output terminals, then only need two groups of on-off elements can realize 256 outputs equally with respective numbers input and output terminal.
The shift register method of shift scratch system 200 of the present invention is not limited to after through 63 clock period, the control end STV2 end of this offset buffer 210 is sent the control end STV end that this counter 270 is got back in a pulse, also can be after through 62 clock period, perhaps a certain moment in 64 clock period, the control end STV2 end of this offset buffer 210 is sent the control end STV end that this counter 270 is got back in a pulse.
The shift register method of shift scratch system 500 of the present invention is not limited to after through 63 clock period, the one control end STV2 end of this offset buffer 510 is sent a pulse to its another control end FB, also can be after through 62 clock period, perhaps in its time in a certain on-off element is in 64 clock period of opening, the control end STV2 end of this offset buffer 510 is sent a pulse to its another control end FB.
Shift scratch system 200,500 of the present invention is not limited to be applied in the scan drive circuit of liquid crystal display drive circuit, also can be applied in the data drive circuit.
Compared to prior art, above-mentioned shift scratch system, shift register method and liquid crystal display The shift scratch system that adopts in the device drive circuit cooperates to have less failing by a plurality of switch elements The offset buffer of outbound port and having that the level shifter with less output port consists of The shift scratch system of many output ports, compared to tradition have than the offset buffer of multiport and Have the level shifter than multiport, its shared chip space is less, therefore can reduce cost.
Claims (15)
1. shift scratch system, it comprises:
One offset buffer, it comprises an initial pulse end that is used to receive external signal, is used to export a plurality of output terminals of the external signal that this initial pulse end received, and a control end;
One level shifter, it comprises a plurality of output terminals, with a plurality of input ends of the corresponding connection of a plurality of output terminals of this offset buffer;
It is characterized in that: further comprise a counter and a plurality of on-off element, this counter comprises a plurality of output terminals, a signal receiving end that is connected with the control end of this offset buffer, a pulse output end that is connected with the initial pulse end of this offset buffer; Each on-off element comprises a plurality of input ends of distinguishing corresponding electrical connection with a plurality of output terminals of this level shifter, a plurality of output terminals that are connected with external circuit, one of them open and close end that is connected with a plurality of output terminals of this counter.
2. shift scratch system as claimed in claim 1 is characterized in that: the output terminal of this offset buffer is 64, and these a plurality of on-off elements are 4.
3. shift register method, come the output of realization data by an individual on-off element of offset buffer, a counter, a level shifter and m (m 〉=1) with the individual output terminal of quantity n (n 〉=1) with the shift scratch system that constitutes n * m output terminal, this method comprises:
Adopt an offset buffer to receive external signal;
Adopt a counter to receive outside initial pulse, (1≤j≤m) individual on-off element triggers and is opening, and remaining on-off element is a closed condition with an offset buffer and j simultaneously;
The signal of the n of this offset buffer output terminal output offers this level shifter, this level shifter moves to required level with level, this level shifter offers this j on-off element with this required level then, and by this j on-off element output;
(1≤i≤n) is after the individual clock period for i when j on-off element is in opening, this counter produces a pulse and to this j+1 on-off element its triggering is opening, remaining on-off element is a closed condition, the signal of the n of this offset buffer output terminal output offers this j+1 on-off element, and by this j+1 on-off element output;
After m on-off element finished required level output, this counter produced a pulse to this offset buffer, and this offset buffer is output signal again.
4. shift register method as claimed in claim 3 is characterized in that: this n value is 64, and this m value is 4, and this i value is 64.
5. liquid crystal display drive circuit, it comprises:
Many the sweep traces that are arranged in parallel, many are arranged in parallel and the data line vertical with this sweep trace, the data drive circuit that is connected with many data lines, the scan drive circuit that is connected with the multi-strip scanning line, this scan drive circuit comprises a shift scratch system, and this shift scratch system comprises:
One offset buffer, it comprises an initial pulse end that is used to receive external signal, is used to export a plurality of output terminals of the external signal that this initial pulse end received, and a control end;
One level shifter, it comprises a plurality of output terminals, with a plurality of input ends of the corresponding connection of a plurality of output terminals of this offset buffer;
It is characterized in that: this shift scratch system comprises and further comprises a counter and a plurality of on-off element, this counter comprises a plurality of output terminals, a signal receiving end that is connected with the control end of this offset buffer, a pulse output end that is connected with the initial pulse end of this offset buffer;
Each on-off element comprises a plurality of input ends of distinguishing corresponding electrical connection with a plurality of output terminals of this level shifter, a plurality of output terminals that are connected with external circuit, one of them open and close end that is connected with a plurality of output terminals of this counter.
6. shift scratch system, it comprises:
One offset buffer, it comprises a plurality of input ends that are used to receive external signal, be used to export a plurality of output terminals of the external signal that this a plurality of input end receives, be used to receive an initial pulse end of outside initial pulse, one resets end, two control ends, this two control end interconnect and are used to control the external signal that these a plurality of output terminals are periodically exported this a plurality of input end and received;
One level shifter, it comprises a plurality of output terminals, a plurality of input ends corresponding with a plurality of output terminals of this offset buffer and that be electrically connected with it;
A plurality of on-off elements, each on-off element comprise a plurality of input ends of distinguishing corresponding electrical connection with a plurality of output terminals of this level shifter, a plurality of output terminals that are connected with external circuit, an open and close end and a control end;
It is characterized in that: these a plurality of on-off elements are connected successively, except that being connected serially to last on-off element, the control end of each on-off element is connected to the open and close end of the on-off element that is series at thereafter, this control end that is connected serially to last on-off element is connected with the end of reseting of this offset buffer, and first is connected with the initial pulse end of this offset buffer by the open and close end of switch in series; The input end of these a plurality of on-off elements is connected with the output terminal of this level shifter by a bus, and the input end of this level shifter connects respectively at the output terminal of this offset buffer.
7. a shift register method is come the output of realization data by an individual on-off element of offset buffer, a level shifter and m (m 〉=1) with the individual output terminal of quantity n (n 〉=1) with the shift scratch system that constitutes n * m output terminal, and this method comprises:
Receive an external signal and an outside initial pulse;
By this outside initial pulse trigger this offset buffer and j (the individual on-off element of 1≤j≤m), remaining on-off element was a closed condition when this j on-off element was triggered opening;
Be in the i (i 〉=1) of opening after the individual clock period at j on-off element, the signal of the n of this offset buffer output terminal output offers this level shifter, this level shifter moves to required level with level, this level shifter offers j on-off element with this required level then, and by this j on-off element output;
When i clock period that j on-off element is in opening finishes, this j on-off element produces a pulse and to this j+1 on-off element its triggering is opening, remaining on-off element is a closed condition, the signal of the n of this offset buffer output terminal output offers this level shifter, this level shifter moves to required level with level, this level shifter offers this j+1 on-off element with this required level then, and by this j+1 on-off element output; After m on-off element finished signal output, this m on-off element produced a pulse to this offset buffer, and this offset buffer stops to produce displacement output.
8. shift register method as claimed in claim 7 is characterized in that: this n value is 64, and this m value is 4, and this i value is 64.
9. liquid crystal display drive circuit, it comprises:
Many the sweep traces that are arranged in parallel, many are arranged in parallel and the data line vertical with this sweep trace,
A plurality of pixels, the data drive circuit that is connected with many data lines, with the scan drive circuit that the multi-strip scanning line is connected, this scan drive circuit comprises a shift scratch system, this shift scratch system comprises:
One offset buffer, it comprises a plurality of input ends that are used to receive external signal, be used to export a plurality of output terminals of the external signal that this a plurality of input end receives, be used to receive an initial pulse end of outside initial pulse, one resets end, two control ends, this two control end interconnect and are used to control the external signal that these a plurality of output terminals are periodically exported this a plurality of input end and received;
One level shifter, it comprises a plurality of output terminals, a plurality of input ends corresponding with a plurality of output terminals of this offset buffer and that be electrically connected with it;
A plurality of on-off elements, each on-off element comprise a plurality of input ends of distinguishing corresponding electrical connection with a plurality of output terminals of this level shifter, a plurality of output terminals that are connected with external circuit, an open and close end and a control end;
It is characterized in that: these a plurality of on-off elements are connected successively, except that being connected serially to last on-off element, the control end of each on-off element is connected to the open and close end of the on-off element that is series at thereafter, this control end that is connected serially to last on-off element is connected with the end of reseting of this offset buffer, and first is connected with the initial pulse end of this offset buffer by the open and close end of switch in series; The input end of these a plurality of on-off elements is connected with the output terminal of this level shifter by a bus, and the input end of this level shifter connects respectively at the output terminal of this offset buffer.
10. shift scratch system, it comprises:
One offset buffer, it comprises at least one input end and a plurality of output terminal, these a plurality of output terminals are used to export the external signal that this input end receives;
One level shifter, it comprises a plurality of input ends and a plurality of output terminal, the corresponding a plurality of output terminals that are connected to this offset buffer of these a plurality of input ends;
A plurality of on-off elements, each on-off element comprise a plurality of input ends and a plurality of output terminal, and these a plurality of input ends are distinguished corresponding electrical connection with a plurality of output terminals of this level shifter;
It is characterized in that: the input end of this offset buffer receives external signal and transmits this external signal to this level shifter, and this level shifter is converted into required level with the external signal that is received, then successively by these a plurality of on-off element outputs.
11. shift scratch system as claimed in claim 10, it comprises that further a counter is used to control a plurality of on-off elements and this offset buffer.
12. a shift register method is come the output of realization data by an individual on-off element of offset buffer, a level shifter and m (m 〉=1) with the individual output terminal of quantity n (n 〉=1) with the shift scratch system that constitutes n * m output terminal, this method comprises:
Adopt an offset buffer to receive external signal;
The signal of the n of this offset buffer output terminal output offers this level shifter, and this level shifter moves to required level with level;
This m on-off element is triggered opening successively, and when file one on-off element was triggered opening, remaining on-off element was a closed condition;
This level shifter offers this m on-off element successively with this required level, and exports successively by this m on-off element.
13. shift register method as claimed in claim 12, it further comprises a method of counting, is used to control this m on-off element and exports required level successively.
14. a liquid crystal display drive circuit, it comprises:
Many the sweep traces that are arranged in parallel, many are arranged in parallel and the data line vertical with this sweep trace, a plurality of pixels, the data drive circuit that is connected with many data lines, the scan drive circuit that is connected with the multi-strip scanning line, this scan drive circuit comprises a shift scratch system, and this shift scratch system comprises:
One offset buffer, it comprises at least one input end and a plurality of output terminal, these a plurality of output terminals are used to export the external signal that this input end receives,
One level shifter, it comprises a plurality of input ends and a plurality of output terminal, the corresponding a plurality of output terminals that are connected to this offset buffer of these a plurality of input ends,
A plurality of on-off elements, each on-off element comprise a plurality of input ends and a plurality of output terminal, and these a plurality of input ends are distinguished corresponding electrical connection with a plurality of output terminals of this level shifter,
It is characterized in that: the input end of this offset buffer receives external signal and transmits this external signal to this level shifter, and this level shifter is converted into required level with the external signal that is received, then successively by these a plurality of on-off element outputs.
15. liquid crystal display drive circuit as claimed in claim 14, it comprises that further a counter is used to control a plurality of on-off elements and this offset buffer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200510100768 CN1956046A (en) | 2005-10-25 | 2005-10-25 | Shift scratch system, method and liquid crystal display driving circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200510100768 CN1956046A (en) | 2005-10-25 | 2005-10-25 | Shift scratch system, method and liquid crystal display driving circuit |
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| CN1956046A true CN1956046A (en) | 2007-05-02 |
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| CN 200510100768 Pending CN1956046A (en) | 2005-10-25 | 2005-10-25 | Shift scratch system, method and liquid crystal display driving circuit |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103000121A (en) * | 2012-12-14 | 2013-03-27 | 京东方科技集团股份有限公司 | Gate driving circuit, array substrate and display device |
| TWI566141B (en) * | 2015-06-09 | 2017-01-11 | 宏碁股份有限公司 | Touch device and operating method thereof |
| WO2019015167A1 (en) * | 2017-07-19 | 2019-01-24 | 深圳市华星光电半导体显示技术有限公司 | Display panel and control method for gate signal thereof |
-
2005
- 2005-10-25 CN CN 200510100768 patent/CN1956046A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103000121A (en) * | 2012-12-14 | 2013-03-27 | 京东方科技集团股份有限公司 | Gate driving circuit, array substrate and display device |
| CN103000121B (en) * | 2012-12-14 | 2015-07-08 | 京东方科技集团股份有限公司 | Gate driving circuit, array substrate and display device |
| TWI566141B (en) * | 2015-06-09 | 2017-01-11 | 宏碁股份有限公司 | Touch device and operating method thereof |
| WO2019015167A1 (en) * | 2017-07-19 | 2019-01-24 | 深圳市华星光电半导体显示技术有限公司 | Display panel and control method for gate signal thereof |
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