CN111951711B - Data selector, display substrate, display device, and data writing method - Google Patents
Data selector, display substrate, display device, and data writing method Download PDFInfo
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- CN111951711B CN111951711B CN202010849025.4A CN202010849025A CN111951711B CN 111951711 B CN111951711 B CN 111951711B CN 202010849025 A CN202010849025 A CN 202010849025A CN 111951711 B CN111951711 B CN 111951711B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
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Abstract
The present disclosure provides a data selector, comprising: the first gating circuit, the second gating circuit and the inverting circuit are respectively provided with a first control signal input end and a second control signal input end, the first control signal input end and the signal input end of the inverting circuit are electrically connected with the gating control signal line, the signal output end of the inverting circuit is electrically connected with the second control signal input end, and the gating control signal line can provide a first level signal/a second level signal; the inverting circuit configuration performs inverting processing on the level signal supplied from the gate control signal line; the first/second gating circuit is configured to turn on the data signal input terminal and the first/second data signal output terminal when the first/second control signal input terminal receives the first level signal, and to turn off the data signal input terminal and the first/second data signal output terminal when the first/second control signal input terminal receives the second level signal.
Description
Technical Field
The present invention relates to the field of display, and in particular, to a data selector, a display substrate, a display device, and a data writing method.
Background
With the rapid development of display technology, there is a higher demand for the aesthetic appearance of display products, and particularly for small-sized and high-resolution products, the width of the frame is one of aesthetic factors, and is highly valued by various manufacturers. Among them, the width of the non-display wiring area is one of important factors affecting the width of the frame.
A data signal supply line is arranged in the non-display wiring region; one end of the data signal supply line is electrically connected with the data line in the display area, and the other end of the data signal supply line is electrically connected with the source driver, and the data signal supply line is used for transmitting the data signal output by the source driver to the data line so as to display pictures.
In the related art, the number of data signal supply lines arranged in the non-display wiring region is equal to the number of data lines in the display region, and the data signal supply lines are in one-to-one correspondence with the data lines. For example, the number of data lines in the display area is 2n, and the number of data signal supply lines arranged in the non-display wiring area is also 2n. As the resolution of the display product increases, the number of data lines increases, and the number of data signal supply lines arranged in the non-display wiring area increases, so that the width of the non-display wiring area increases, which is not beneficial to the narrow frame design of the product.
Disclosure of Invention
The invention aims to at least solve one of the technical problems in the prior art, and provides a data selector, a display substrate, a display device and a data writing method.
In a first aspect, embodiments of the present disclosure provide a data selector, comprising: the first gating circuit, the second gating circuit and the inverting circuit are respectively provided with a first control signal input end and a second control signal input end, the first control signal input end and the signal input end of the inverting circuit are electrically connected with a gating control signal line, the signal output end of the inverting circuit is electrically connected with the second control signal input end, the gating control signal line can provide a first level signal and a second level signal, and the first level signal and the second level signal are mutually inverted level signals;
the inverting circuit is configured to perform inversion processing on the level signal provided by the gating control signal line and output the level signal to the second control signal input end;
the first gating circuit is electrically connected with a data signal input end and a first data signal output end, and is configured to conduct the data signal input end and the first data signal output end when the first control signal input end receives the first level signal, and disconnect the data signal input end and the first data signal output end when the first control signal input end receives the second level signal;
the second gating circuit is electrically connected to the data signal input terminal and the second data signal output terminal, and is configured to turn on the data signal input terminal and the second data signal output terminal when the second control signal input terminal receives the first level signal, and to turn off the data signal input terminal and the second data signal output terminal when the second control signal input terminal receives the second level signal.
In some embodiments, the first gating circuit includes: a first transistor, the second gating circuit comprising: a second transistor;
the control electrode of the first transistor is electrically connected with the first control signal input end, the first electrode of the first transistor is electrically connected with the data signal input end, and the second electrode of the first transistor is electrically connected with the first data signal output end;
the control electrode of the second transistor is electrically connected with the first control signal input end, the first electrode of the second transistor is electrically connected with the data signal input end, and the second electrode of the second transistor is electrically connected with the first data signal output end;
the first transistor and the second transistor are simultaneously N-type transistors or simultaneously P-type transistors.
In some embodiments, the inverting circuit comprises: a third transistor and a fourth transistor;
the control electrode and the first electrode of the third transistor are electrically connected with the first level supply end, and the second electrode of the third transistor is electrically connected with the signal output end of the inverting circuit;
the control electrode of the fourth transistor is electrically connected with the signal input end of the inverting circuit, the first electrode of the fourth transistor is electrically connected with the signal output end of the inverting circuit, and the second electrode of the fourth transistor is electrically connected with the first level supply end.
In some embodiments, further comprising: a first adjustable load circuit and/or a second adjustable load circuit;
the first gating circuit is electrically connected with the first data signal output end through a first adjustable load circuit, and the second gating circuit is electrically connected with the second data signal output end through a second adjustable load circuit;
the first adjustable load circuit is electrically connected with a first adjustment signal end and is configured to respond to the control of a first adjustment signal provided by the first adjustment signal end to adjust the load size connected between the first adjustable load circuit and the first data signal output end;
the second adjustable load circuit is electrically connected with the second adjustment signal end and is configured to respond to the control of a second adjustment signal provided by the second adjustment signal end to adjust the load size connected between the second adjustable load circuit and the second data signal output end.
In some embodiments, the first adjustable load circuit includes a fifth transistor and the second adjustable load circuit includes a sixth transistor;
the control electrode of the fifth transistor is electrically connected with the first adjustment signal end, the first electrode of the fifth transistor is electrically connected with the first data signal output end, and the second electrode of the fifth transistor is electrically connected with the first gating circuit;
the control electrode of the sixth transistor is electrically connected with the second adjustment signal end, the first electrode of the sixth transistor is electrically connected with the second data signal output end, and the second electrode of the sixth transistor is electrically connected with the second gating circuit.
In some embodiments, the first adjustment signal terminal and the second adjustment signal terminal are the same signal terminal.
In a second aspect, embodiments of the present disclosure further provide a display substrate, including: the data selector as provided in the first aspect above.
In some embodiments, the display substrate further comprises: a plurality of data lines, wherein the number of the data selectors is plural, and each data selector corresponds to 1 data signal supply line and 2 data lines;
for any one of the data selectors, a data signal input terminal of the data selector is electrically connected to the corresponding data signal supply line, and a first data signal output terminal and a second data signal output terminal of the data selector are respectively electrically connected to the corresponding 2 data lines.
In some embodiments, the gate control signal lines to which all the data selectors are electrically connected are the same clock signal line for outputting a clock signal including: a first level signal and a second level signal alternately appear, the duration of the first level signal being equal to the duration of the second level signal.
In a third aspect, an embodiment of the present disclosure further provides a display apparatus, including: the display substrate as provided in the second aspect above.
In a fourth aspect, an embodiment of the present disclosure further provides a data writing method, based on the data selector provided in the first aspect, the data writing method includes: a first writing phase and a second writing phase alternately performed;
in the first writing stage, the gating control signal line provides a first level signal, the first control signal input end receives the first level signal, and the first gating circuit conducts the data signal input end and the first data signal output end so as to write the data signal provided by the data signal input end into the first data signal output end; the inverting circuit performs inverting processing on the first level signal and outputs a second level signal to the second control signal input end, and the second gating circuit disconnects the data signal input end from the second data signal output end;
in the second writing stage, the gating control signal line provides a second level signal, the first control signal input end receives the second level signal, and the second gating circuit disconnects the data signal input end from the first data signal output end; the inverting circuit performs inversion processing on the second level signal and outputs a first level signal to the second control signal input end, and the second gating circuit conducts the data signal input end and the second data signal output end so as to write the data signal provided by the data signal input end into the second data signal output end.
Drawings
Fig. 1 is a schematic circuit diagram of a data selector according to an embodiment of the disclosure;
FIG. 2 is a schematic circuit diagram of another data selector according to an embodiment of the disclosure;
FIG. 3 is a schematic circuit diagram of a data selector according to another embodiment of the present disclosure;
FIG. 4 is a timing diagram illustrating operation of the data selector of FIG. 3 in accordance with one embodiment of the present disclosure;
FIG. 5 is a flowchart of a data writing method according to an embodiment of the present disclosure;
fig. 6 is a schematic structural diagram of a display substrate according to an embodiment of the disclosure;
FIG. 7 is a driving timing diagram of the display substrate shown in FIG. 6.
Detailed Description
In order to enable those skilled in the art to better understand the technical solutions of the present invention, a data selector, a display substrate, a display device and a data writing method provided by the present invention are described in detail below with reference to the accompanying drawings.
Fig. 1 is a schematic circuit diagram of a data selector according to an embodiment of the disclosure, as shown in fig. 1, where the data selector includes: the first gating circuit 1, the second gating circuit 2 and the inverting circuit 3 are respectively configured with a first control signal input end and a second control signal input end, the first control signal input end and the signal input end of the inverting circuit 3 are electrically connected with the gating control signal line CS, and the signal output end of the inverting circuit 3 is electrically connected with the second control signal input end.
The gate control signal line CS can provide a first level signal and a second level signal, which are opposite-phase signals. In the embodiments of the present disclosure, one of the first level signal and the second level signal is a high level signal, and the other is a low level signal, and detailed description will be given in connection with specific examples later.
The inverting circuit 3 is configured to invert the level signal supplied from the gate control signal line CS and output it to the second control signal input terminal. Specifically, when the on control signal line CS supplies the first level signal, the inverter circuit 3 may invert the first level signal to generate and output the second level signal; when the gate control signal line CS supplies the second level signal, the inverter circuit 3 may invert the second level signal to generate and output the first level signal. The technical scheme of the present disclosure does not limit the specific circuit structure of the inverter circuit 3, but any circuit having an inverter processing function can be used as the inverter circuit 3 in the technical scheme of the present disclosure.
The first gating circuit 1 is electrically connected to the data signal input terminal IN and the first data signal output terminal OUT1, and the first gating circuit 1 is configured to turn on the data signal input terminal IN and the first data signal output terminal OUT1 when the first control signal input terminal receives the first level signal, and to turn off the data signal input terminal IN and the first data signal output terminal OUT1 when the first control signal input terminal receives the second level signal.
The second gating circuit 2 is electrically connected to the data signal input terminal IN and the second data signal output terminal OUT2, and the second gating circuit 2 is configured to turn on the data signal input terminal IN and the second data signal output terminal OUT2 when the second control signal input terminal receives the first level signal, and to turn off the data signal input terminal IN and the second data signal output terminal OUT2 when the second control signal input terminal receives the second level signal.
It should be noted that, the circuit structures of the first gating circuit 1 and the second gating circuit 2 are not limited in the technical scheme of the present disclosure, and the circuit structures of the first gating circuit 1 and the second gating circuit 2 may be the same or different, and any circuit having a "switch" function may be applied as the first/second gating circuit 2 to the technical scheme of the present disclosure.
In the disclosed embodiments, the data selector may operate in two different phases: a first write phase and a second write phase.
IN the first writing stage, the gate control signal line CS provides a first level signal, the first control signal input terminal receives the first level signal, and the first gate circuit 1 conducts the data signal input terminal IN with the first data signal output terminal OUT1 to write the data signal provided by the data signal input terminal IN to the first data signal output terminal OUT1; the inverting circuit 3 inverts the first level signal and outputs a second level signal to the second control signal input terminal, and the second gating circuit 2 disconnects the data signal input terminal IN from the second data signal output terminal OUT2. That is, the first gating circuit 1 is gated on, and the second gating circuit 2 is turned off.
IN the second writing stage, the strobe control signal line CS provides a second level signal, the first control signal input terminal receives the second level signal, and the second strobe circuit 2 disconnects the data signal input terminal IN from the first data signal output terminal OUT1; the inverting circuit 3 inverts the second level signal and outputs the first level signal to the second control signal input terminal, and the second gating circuit 2 turns on the data signal input terminal IN and the second data signal output terminal OUT2 to write the data signal supplied from the data signal input terminal IN to the second data signal output terminal OUT2. That is, the second gating circuit 2 is gated, and the first gating circuit 1 is turned off.
When the data selector provided by the embodiment of the present disclosure is applied to a display substrate, the data signal input terminal IN of the data selector may be electrically connected to 1 data signal supply line, and the first data signal output terminal OUT1 and the second data signal output terminal OUT2 of the data selector may be electrically connected to 2 different data lines, respectively. In the data writing, the data signal supplied from the data signal supply line may be written to 1 data line through the first data signal output terminal OUT1 in the first writing stage, and the data signal supplied from the data signal supply line may be written to the other 1 data line through the second data signal output terminal OUT2 in the second writing stage. That is, by adding the data selector provided by the embodiments of the present disclosure, 1 data signal supply line can supply data signals to 2 different data lines, respectively.
Taking the data of the data lines of the display area as 2n as an example, by configuring n data selectors, the first data signal output terminal OUT1 and the second data signal output terminal OUT2 of each data selector are electrically connected with different data lines, at this time, the data signal supply lines required to be arranged IN the non-display wiring area are n, the n data signal supply lines are IN one-to-one correspondence with the n data selectors, and each data selector is electrically connected with the data signal input terminal IN of the corresponding data selector.
Compared with the prior art, the technical scheme of the display device has the advantages that the data signal lines required to be arranged in the non-display wiring area can be halved, the width of the non-display wiring area can be correspondingly reduced, and the narrow frame of the display device is facilitated; in addition, in the embodiment of the disclosure, the data selector can be controlled only by 1 strobe control signal line CS, so that the number of control signal lines configured by the data selector can be effectively reduced, and the structural complexity and the control complexity of the display device can be reduced.
IN practice, it is found that as the accumulation of the usage time increases, the electrical characteristics of the electrical structures IN the first gating circuit 1 and the second gating circuit 2 deviate, resulting IN an increase IN the impedance (resistance) coupled into the circuit, and IN the case of a certain voltage level of the transmitted data signal, the voltage Drop (IR Drop) generated from the data signal input terminal IN to the first/second data signal output terminals OUT1, OUT2 increases, resulting IN a distortion of the data signal during transmission. To solve the above technical problems, embodiments of the present disclosure provide another data selector.
Fig. 2 is a schematic circuit diagram of another data selector according to an embodiment of the present disclosure, where, as shown in fig. 2, the data selector includes a first gating circuit 1, a second gating circuit 2, and an inverting circuit 3, and may further include: a first adjustable load circuit 4 and a second adjustable load circuit 5; the first gating circuit 1 is electrically connected with the first data signal output end OUT1 through a first adjustable load circuit 4, and the second gating circuit 2 is electrically connected with the second data signal output end OUT2 through a second adjustable load circuit 5; the first adjustable load circuit 4 is electrically connected with the first adjustment signal terminal C1 and configured to adjust the load connected between the first adjustable load circuit 4 and the first data signal output terminal OUT1 in response to the control of the first adjustment signal provided by the first adjustment signal terminal C1; the second adjustable load circuit 5 is electrically connected to the second adjustment signal terminal C2, and is configured to adjust a load connected between the second adjustable load circuit 5 and the second data signal output terminal OUT2 in response to control of the second adjustment signal provided by the second adjustment signal terminal C2.
Taking the first adjustable load circuit 4 as an example, the impedance between the data signal input terminal IN and the first data signal output terminal OUT1 is adjusted. In the initial stage of product use, the first adjustable load circuit 4 is controlled by the first adjustment signal terminal C1 to be connected to the circuit with the impedance R0, the impedance in the circuit connected to the first gating circuit 1 is R1, r0+r1=r2, and R2 is a preset impedance. With the increase of the product accumulated usage time, the impedance of the first gating circuit 1 IN the access circuit is increased and denoted as R1' (R1 ' > R1), and at this time, the access impedance of the first adjustable load circuit 4 can be adjusted down by the first adjustment signal terminal C1, and the adjusted down resistance is R0', so that the value of R0' +r1' is equal to or close to R2, i.e. the impedance between the data signal input terminal IN and the first data signal output terminal OUT1 is kept unchanged.
In practical applications, the impedance change Δr of the first gating circuit 1 can be determined by detecting the voltage drop (the voltage difference between the node N1 and the node N2) change generated by the first gating circuit 1, so as to obtain r1 '=r1+ [ Δr ] and r0' =r0- [ Δr ].
The principle of adjusting the impedance between the data signal input terminal IN and the second data signal output terminal OUT2 by using the second adjustable load circuit 5 is similar, and will not be described herein.
In some embodiments, the circuit structures of the first gating circuit 1 and the second gating circuit 2 are identical, and the circuit structures of the first adjustable load circuit 4 and the second adjustable load circuit 5 are identical. In the use process, because the environments and the accumulated working time of the first gating circuit 1 and the second gating circuit 2 are basically the same, the electrical characteristics (impedance) offset of the first gating circuit 1 and the second gating circuit 2 in the use process are basically the same, and the access impedance of the required first adjustable load circuit 4 and the access impedance of the required second adjustable load circuit 5 are basically the same, so that the same adjustment signal terminal can be adopted for controlling the adjustment signal terminals of the first adjustable load circuit 4 and the second adjustable load circuit 5, the number of signal terminals required to be configured by the data selector is effectively reduced, and the structural complexity and the control complexity of the display device are reduced.
It should be understood by those skilled IN the art that the first adjustable load circuit 4 is configured only between the first gate circuit 1 and the first data signal output terminal OUT1 to control only the overall impedance between the data signal input terminal IN to the first data signal output terminal OUT1; alternatively, the second adjustable load circuit 5 is configured only between the second gate circuit 2 and the second data signal output terminal OUT2 to control only the overall impedance between the data signal input terminal IN to the second data signal output terminal OUT 2; both of these approaches should also fall within the scope of the present disclosure.
Fig. 3 is a schematic circuit diagram of another data selector according to an embodiment of the disclosure, where, as shown in fig. 3, the data selector shown in fig. 3 is a specific implementation scheme based on the data selector shown in fig. 1 and 2.
Each of the transistors referred to in the embodiments of the present disclosure may be independently selected from one of a polycrystalline silicon thin film transistor, an amorphous silicon thin film transistor, an oxide thin film transistor, and an organic thin film transistor, respectively. In this disclosure, reference to a "control electrode" specifically refers to the gate of a transistor, a "first electrode" specifically refers to the source of a transistor, and a corresponding "second electrode" specifically refers to the drain of a transistor. Of course, those skilled in the art will appreciate that the "first pole" and "second pole" may be interchanged.
In some embodiments, the first gating circuit 1 comprises: the first transistor M1, the second gate circuit 2 includes: a second transistor M2; the control electrode of the first transistor M1 is electrically connected with the first control signal input end, the first electrode of the first transistor M1 is electrically connected with the data signal input end IN, and the second electrode of the first transistor M1 is electrically connected with the first data signal output end OUT1; the control electrode of the second transistor M2 is electrically connected with the first control signal input end, the first electrode of the second transistor M2 is electrically connected with the data signal input end IN, and the second electrode of the second transistor M2 is electrically connected with the first data signal output end OUT1; the first transistor M1 and the second transistor M2 are both N-type transistors or P-type transistors.
In some embodiments, the inverting circuit 3 comprises: a third transistor M3 and a fourth transistor M4; the control electrode and the first electrode of the third transistor M3 are electrically connected with the first level supply end, and the second electrode of the third transistor M3 is electrically connected with the signal output end of the inverting circuit 3; the control electrode of the fourth transistor M4 is electrically connected to the signal input terminal of the inverter circuit 3, the first electrode of the fourth transistor M4 is electrically connected to the signal output terminal of the inverter circuit 3, and the second electrode of the fourth transistor M4 is electrically connected to the first level supply terminal.
When the first adjustable load circuit 4 and the second adjustable load circuit 5 are included in the data selector, the first adjustable load circuit 4 includes a fifth transistor M5, and the second adjustable load circuit 5 includes a sixth transistor M6. The control electrode of the fifth transistor M5 is electrically connected to the first adjustment signal terminal C1, the first electrode of the fifth transistor M5 is electrically connected to the first data signal output terminal OUT1, and the second electrode of the fifth transistor M5 is electrically connected to the first gate circuit 1; the control electrode of the sixth transistor M6 is electrically connected to the second adjustment signal terminal C2, the first electrode of the sixth transistor M6 is electrically connected to the second data signal output terminal OUT2, and the second electrode of the sixth transistor M6 is electrically connected to the second gate circuit 2. In some embodiments, the first adjustment signal terminal C1 and the second adjustment signal terminal C2 are the same signal terminal.
The fifth transistor M5 and the sixth transistor M6 are used as variable resistors, and the voltage of the control electrodes of the fifth transistor M5 and the sixth transistor M6 is controlled to control the turn-on degree of the fifth transistor M5 and the sixth transistor M6, so that the equivalent resistors of the fifth transistor M5 and the sixth transistor M6 connected to the circuit are controlled. Specifically, the fifth transistor M5 and the sixth transistor M6 are controlled to both operate and the variable resistance region, and the equivalent resistance of the fifth transistor M5 and the sixth transistor M6 connected to the circuit is reduced by increasing the gate voltages applied to the fifth transistor M5 and the sixth transistor M6 to increase the turn-on degrees of the fifth transistor M5 and the sixth transistor M6.
Transistors may be divided into N-type transistors and P-type transistors, each of which may be independently selected from N-type transistors or P-type transistors, respectively, in the present disclosure; in the following description, an example will be described in which all transistors are N-type transistors, and the transistors in the data selector can be simultaneously manufactured using the same manufacturing process. Accordingly, the first level refers to a high level in particular, and the second level refers to a low level in particular. The first level supply terminal provides a high level voltage VGH, and the second level supply terminal provides a low level voltage VGL. The first adjusting signal terminal C1 and the second adjusting signal terminal C2 both provide a high level signal VGH' to control the fifth transistor M5 and the sixth transistor M6 to be in a conducting state, and the specific voltage level of the high level signal can be preset according to actual needs.
FIG. 4 is a timing diagram illustrating operation of the data selector shown in FIG. 3 according to an embodiment of the present disclosure, where the data selector shown in FIG. 4 includes: a first write phase t1 and a second write phase t2.
In the first writing stage t1, the gate control signal line CS provides a high level signal, the first transistor M1 and the fourth transistor M4 are turned on, the third transistor M3 is equivalent to a large resistance, the low level voltage VGL is written to the control electrode of the second transistor M2 through the fourth transistor M4, and the second transistor M2 is turned off. At this time, the data signal input terminal IN is turned on with the first data signal output terminal OUT1, and the data signal Vdata1 provided by the data signal input terminal IN is written into the first data signal output terminal OUT1 for output.
In the second writing stage t2, the gate control signal line CS provides a low level signal, the first transistor M1 and the fourth transistor M4 are turned off, the third transistor M3 is turned on, the high level voltage VGH is written to the control electrode of the second transistor M2 through the third transistor M3, and the second transistor M2 is turned on. At this time, the data signal input terminal IN is conducted with the second data signal output terminal OUT2, and the data signal Vdata2 provided by the data signal input terminal IN is written into the second data signal output terminal OUT2 for output.
In practical application, the first writing phase t1 and the second writing phase t2 are alternately performed; the execution time of the first writing stage t1 and the second writing stage t2 can be set according to actual needs. In some embodiments, the execution times of the first write phase t1 and the second write phase t2 are equal.
The embodiment of the disclosure provides a data selector, which can halve data signal lines required to be arranged in a non-display wiring area when the data selector is applied to a display device, and the width of the non-display wiring area can be correspondingly reduced, so that the narrow frame of the display device is facilitated; in addition, in the embodiment of the disclosure, the data selector can be controlled only by 1 strobe control signal line CS, so that the number of control signal lines configured by the data selector can be effectively reduced, and the structural complexity and the control complexity of the display device can be reduced.
Fig. 5 is a flowchart of a data writing method according to an embodiment of the present disclosure, as shown in fig. 5, where the data writing method is based on the data selector provided in the previous embodiment, and the data writing method includes:
step S1, in a first writing stage, a gating control signal line provides a first level signal, a first control signal input end receives the first level signal, and a first gating circuit conducts a data signal input end and a first data signal output end so as to write a data signal provided by the data signal input end into the first data signal output end; the inverting circuit inverts the first level signal and outputs a second level signal to the second control signal input terminal, and the second strobe circuit disconnects the data signal input terminal from the second data signal output terminal.
Step S2, in a second writing stage, the gating control signal line provides a second level signal, the first control signal input end receives the second level signal, and the second gating circuit disconnects the data signal input end from the first data signal output end; the inverting circuit performs inversion processing on the second level signal and outputs the first level signal to the second control signal input end, and the second gating circuit conducts the data signal input end and the second data signal output end so as to write the data signal provided by the data signal input end into the second data signal output end.
The technical scheme of the present disclosure does not limit the sequence of step S1 and step S2; in some embodiments, steps S1 and S2 alternate.
For a specific description of step S1 and step S2, reference may be made to the corresponding content in the previous embodiments, and the description is omitted here.
Fig. 6 is a schematic structural diagram of a display substrate according to an embodiment of the disclosure, as shown in fig. 6, where the display substrate includes: the data selector provided in the previous embodiment.
In some embodiments, the display substrate further includes a plurality of data lines D1 to D2n, the number of the data selectors M1 to Mn is plural, each data selector M1/M2/. The data signal supply line DL1/DL 2./DLn and 2 data lines D1, D2/D3, D4/. The data signal supply line DL 1/D2 n-1/D2n; for any one of the data selectors M1/M2/./ Mn, the data signal input terminal IN of the data selector M1/M2/./ Mn is electrically connected to the corresponding data signal supply line DL1/DL 2./ DLn, and the first data signal output terminal OUT1 and the second data signal output terminal OUT2 of the data selector are electrically connected to the corresponding 2 data lines, respectively.
IN some embodiments, the number of the data lines D1 to D2n is 2n, the number of the data selectors M1 to Mn is n, wherein the data signal input terminal IN of the ith data selector Mi is electrically connected to the ith data signal supply line DLi, the first data signal output terminal OUT1 of the ith data selector Mi is electrically connected to the 2i-1 th data line, the second data signal output terminal OUT2 of the ith data selector Mi is electrically connected to the 2i data line, 1.ltoreq.i.ltoreq.n, and i is an integer.
In some embodiments, the strobe control signal lines configured by all of the data selectors M1-Mn are the same strobe control signal line CS. That is, all of the data selectors M1 to Mn operate simultaneously in the first writing stage or simultaneously in the second writing stage.
In some embodiments, all of the data selectors M1-Mn share the same inverting circuit, i.e., the 1 inverting circuit is electrically connected to the second control signal input of the second strobe circuit in each data selector.
In some embodiments, the gating control signal line CS is a clock signal line for outputting a clock signal including: the first level signal and the second level signal are alternately present, and the duration of the first level signal is equal to the duration of the second level signal, i.e. the time of the first writing phase and the second writing phase is equal.
Fig. 7 is a driving timing diagram of the display substrate shown in fig. 6, and as shown in fig. 7, in practical application, the display substrate further includes a plurality of gate lines G1 to Gm, and a gate driver (not shown) sequentially scans and drives the plurality of gate lines G1 to Gm. In one frame, the driving time corresponding to each gate line G1/G2./Gm is recorded as t, and the duration of each of the first writing phase and the second writing phase may be set to t/2, i.e., the period of the clock signal is t, and the duty ratio is 50%. The data lines in the odd columns are written with data voltages in the first writing stage; the data lines in even columns are written with data voltages in the second writing phase.
The embodiment of the disclosure also provides a display device, including: the display substrate provided by the above embodiment is used as a display substrate, and for a specific description of the display substrate, reference may be made to the corresponding content in the foregoing embodiment, which is not repeated herein.
The display device provided by the embodiment of the disclosure can be any product or component with a display function, such as electronic paper, a liquid crystal display panel, an organic light emitting display panel, a mobile phone, a tablet personal computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like.
According to the technical scheme, the data signal wires required to be arranged in the non-display wiring area in the display device can be halved, the width of the non-display wiring area can be correspondingly reduced, and the narrow frame of the display device is facilitated; in addition, in the embodiment of the disclosure, the data selector can be controlled only by 1 strobe control signal line, so that the number of control signal lines configured by the data selector can be effectively reduced, and the structural complexity and the control complexity of the display device can be reduced.
It is to be understood that the above embodiments are merely illustrative of the application of the principles of the present invention, but not in limitation thereof. Various modifications and improvements may be made by those skilled in the art without departing from the spirit and substance of the invention, and are also considered to be within the scope of the invention.
Claims (4)
1. A display substrate, comprising: a data selector, the data selector comprising: the first gating circuit, the second gating circuit and the inverting circuit are respectively provided with a first control signal input end and a second control signal input end, the first control signal input end and the signal input end of the inverting circuit are electrically connected with a gating control signal line, the signal output end of the inverting circuit is electrically connected with the second control signal input end, the gating control signal line can provide a first level signal and a second level signal, and the first level signal and the second level signal are mutually inverted level signals;
the inverting circuit is configured to perform inversion processing on the level signal provided by the gating control signal line and output the level signal to the second control signal input end;
the first gating circuit is electrically connected with a data signal input end and a first data signal output end, and is configured to conduct the data signal input end and the first data signal output end when the first control signal input end receives the first level signal, and disconnect the data signal input end and the first data signal output end when the first control signal input end receives the second level signal;
the second gating circuit is electrically connected with a data signal input end and a second data signal output end, and is configured to conduct the data signal input end and the second data signal output end when the second control signal input end receives the first level signal, and disconnect the data signal input end and the second data signal output end when the second control signal input end receives the second level signal;
the first gating circuit includes: a first transistor, the second gating circuit comprising: a second transistor;
the control electrode of the first transistor is electrically connected with the first control signal input end, the first electrode of the first transistor is electrically connected with the data signal input end, and the second electrode of the first transistor is electrically connected with the first data signal output end;
the control electrode of the second transistor is electrically connected with the first control signal input end, the first electrode of the second transistor is electrically connected with the data signal input end, and the second electrode of the second transistor is electrically connected with the first data signal output end;
the inverter circuit includes: a third transistor and a fourth transistor;
the control electrode and the first electrode of the third transistor are electrically connected with the first level supply end, and the second electrode of the third transistor is electrically connected with the signal output end of the inverting circuit;
the control electrode of the fourth transistor is electrically connected with the signal input end of the inverting circuit, the first electrode of the fourth transistor is electrically connected with the signal output end of the inverting circuit, and the second electrode of the fourth transistor is electrically connected with the first level supply end;
further comprises: a first adjustable load circuit and a second adjustable load circuit;
the first gating circuit is electrically connected with the first data signal output end through a first adjustable load circuit, and the second gating circuit is electrically connected with the second data signal output end through a second adjustable load circuit;
the first adjustable load circuit is electrically connected with a first adjustment signal end and is configured to respond to the control of a first adjustment signal provided by the first adjustment signal end to adjust the load size connected between the first adjustable load circuit and the first data signal output end;
the second adjustable load circuit is electrically connected with a second adjustment signal end and is configured to respond to the control of a second adjustment signal provided by the second adjustment signal end to adjust the load size connected between the second adjustable load circuit and the second data signal output end;
the first adjustable load circuit includes a fifth transistor, and the second adjustable load circuit includes a sixth transistor;
the control electrode of the fifth transistor is electrically connected with the first adjustment signal end, the first electrode of the fifth transistor is electrically connected with the first data signal output end, and the second electrode of the fifth transistor is electrically connected with the first gating circuit;
the control electrode of the sixth transistor is electrically connected with the second adjustment signal end, the first electrode of the sixth transistor is electrically connected with the second data signal output end, and the second electrode of the sixth transistor is electrically connected with the second gating circuit;
the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor and the sixth transistor are simultaneously N-type transistors or simultaneously P-type transistors;
the first adjusting signal end and the second adjusting signal end are the same signal end;
the number of the data selectors is plural, and all the data selectors share the same inverting circuit.
2. The display substrate of claim 1, wherein the display substrate further comprises: a plurality of data lines, each of the data selectors corresponding to 1 data signal supply line and 2 data lines;
for any one of the data selectors, a data signal input terminal of the data selector is electrically connected to the corresponding data signal supply line, and a first data signal output terminal and a second data signal output terminal of the data selector are respectively electrically connected to the corresponding 2 data lines.
3. The display substrate according to claim 2, wherein the gate control signal lines to which all the data selectors are electrically connected are the same clock signal line for outputting a clock signal including: a first level signal and a second level signal alternately appear, the duration of the first level signal being equal to the duration of the second level signal.
4. A display device, comprising: a display substrate according to any one of claims 1 to 3.
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| WO2015149492A1 (en) * | 2014-04-02 | 2015-10-08 | 京东方科技集团股份有限公司 | Pixel circuit and display device |
| CN109272927A (en) * | 2018-10-26 | 2019-01-25 | 京东方科技集团股份有限公司 | Display control unit and control method, display device |
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| JP2009103794A (en) * | 2007-10-22 | 2009-05-14 | Nec Electronics Corp | Driving circuit for display apparatus |
| KR101065405B1 (en) * | 2010-04-14 | 2011-09-16 | 삼성모바일디스플레이주식회사 | Display and operating method for the same |
| CN206516324U (en) * | 2016-12-28 | 2017-09-22 | 厦门天马微电子有限公司 | Array base palte, display panel and display device |
| CN107742502B (en) * | 2017-11-30 | 2019-10-15 | 武汉天马微电子有限公司 | A kind of display panel, display methods and display device |
| CN110503910B (en) * | 2018-05-17 | 2023-03-10 | 京东方科技集团股份有限公司 | Multi-channel distributor, control method thereof and display device |
| CN110060621B (en) * | 2019-05-31 | 2022-06-07 | 武汉天马微电子有限公司 | Display panel and display device |
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| WO2015149492A1 (en) * | 2014-04-02 | 2015-10-08 | 京东方科技集团股份有限公司 | Pixel circuit and display device |
| CN109272927A (en) * | 2018-10-26 | 2019-01-25 | 京东方科技集团股份有限公司 | Display control unit and control method, display device |
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