CN1952875A - A fixed-point divider and operational method thereof - Google Patents
A fixed-point divider and operational method thereof Download PDFInfo
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- CN1952875A CN1952875A CN 200610139702 CN200610139702A CN1952875A CN 1952875 A CN1952875 A CN 1952875A CN 200610139702 CN200610139702 CN 200610139702 CN 200610139702 A CN200610139702 A CN 200610139702A CN 1952875 A CN1952875 A CN 1952875A
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Abstract
This invention discloses a fix point divider, which comprises character generator, absolute generator, judger, difference generator and product generator. This invention also discloses one method of the fix point computation, which comprises the following steps: getting divider and divided absolute value to get product character for memory according to divider and divided; judging whether the divided value is larger or equal to divider absolute; if yes, then computing divided value highest valid bit and that of divider to get the different; getting the divided and divider product according to product bit, absolute value, otherwise output as zero.
Description
Technical field
The present invention relates to digital circuit technique, refer to the method for a kind of fixed-point divider and realization computing thereof especially.
Background technology
In digital signal processing, relate to the division arithmetic circuit through regular meeting.But in the advanced hardware descriptive language, do not have can be comprehensive divide statement, all do not provide division relevant statement as VHDL with Verilog HDL.At present, in wherein a kind of fixed point division circuit arrangement, include the multiplying unit, circuit structure is very complicated, and the logic gates of consumption is more, postpones bigger; The redundanat code that another division circuit has then adopted the secondary computing to constitute is mixed the redundanat code adder unit that uses and is formed the division array with scale-of-two, and adopt the selector switch of alternative to constitute the array change-over circuit that the merchant of redundanat code is directly changed into binary mode, the same more complicated of its circuit structure, it is more to take resource; Also having a kind of is to be calculate platform with the microprocessor, and by the division arithmetic that instruction realizes, the skill that adopts binary displacement and addition to be simplifying the calculating process of division, but the related operation circuit arrangement is not provided.
In addition, the correlation module of realizing division is provided in the logic circuit development instrument of the Handel of Celoxica company C language, but its resource consumption is bigger, with one 32 dividers divided by 32 is example, need about 44000 of equivalent electrical circuit door number, the greatest combined logical path time delay need 333ns.
Summary of the invention
In view of this, fundamental purpose of the present invention is to provide a kind of fixed-point divider, and this fixed-point divider circuit structure is simple.
Another object of the present invention is to provide a kind of fixed-point divider to realize the method for computing, can reduce operating delay, economize on resources.
For achieving the above object, technical scheme of the present invention specifically is achieved in that
A kind of fixed-point divider, this fixed-point divider comprises:
Merchant's generator 104 receives merchant's sign bit, the absolute value of divisor, the absolute value of dividend, and potential difference, and output has the merchant result of symbol; Perhaps receive triggering, output zero from arbiter (102).
Described fixed-point divider also comprises divisor absolute value register and dividend absolute value register; Described absolute value generator 101 comprises divisor absolute value generator and dividend absolute value generator;
Described divisor absolute value generator is used to receive divisor, obtains the divisor absolute value, and described divisor absolute value is outputed to divisor absolute value register;
Described dividend absolute value generator is used to receive dividend, obtains the dividend absolute value, and described dividend absolute value is outputed in the dividend absolute value register.
Described potential difference generator 103 comprises that highest significant position counts generation circuit and potential difference generation circuit;
Described highest significant position is counted the generation circuit, is used to receive divisor absolute value or dividend absolute value, obtains the highest significant position number and the output of divisor or dividend respectively;
Described potential difference generation circuit, be used to receive the highest significant position number of divisor and the highest significant position number of dividend, calculate numerical digit poor of the highest significant position of the highest significant position of dividend and divisor, obtain the potential difference of dividend absolute value and divisor absolute value, and described potential difference is outputed in the potential difference register.
Described fixed-point divider also comprises first register and second register; Described highest significant position generation circuit comprises that the divisor highest significant position is counted the generation circuit and the dividend highest significant position is counted the generation circuit;
Described divisor highest significant position is counted the generation circuit, is used to receive the divisor absolute value, obtains the highest significant position number of divisor, and the highest significant position number of described divisor is outputed in first register;
Described dividend highest significant position is counted the generation circuit, is used to receive the dividend absolute value, obtains the highest significant position number of dividend, and the highest significant position number of described dividend is outputed in second register.
Described merchant's generator 104 comprises: circuit takes place difference and circuit takes place the merchant;
Described difference generation circuit comprises totalizer, determining device at least, the device sum counter moves to left;
Wherein, the described device that moves to left is used to receive divisor absolute value, dividend absolute value and potential difference, with the dividend absolute value potential difference position that moves to left, and exports to totalizer; Perhaps receive first notice from determining device, the minuend absolute value of self exporting moves to left 1, and the result is exported to totalizer; Perhaps receive difference, difference is moved to left 1 and add 1, and the result is exported to totalizer, send the counting notice to counter simultaneously from totalizer;
Described totalizer is used to receive the divisor absolute value and from the value of the device output that moves to left, calculates the value of the difference of the two, and the result is exported to determining device; Perhaps receive second notice, difference is exported to the device that moves to left from determining device;
Described determining device is used to receive the difference from totalizer, whether judges this difference less than 0, if, to device output first notice that moves to left, otherwise, to totalizer output second notice;
Described counter is used to receive the counting notice from the device that moves to left, and begins counting, and at calculated value during greater than the potential difference value, and the potential difference value of the low level of output minuend absolute value adds 1 and to the merchant circuit takes place;
Circuit takes place in described merchant, the potential difference value that receives the low level of merchant's sign bit and the minuend that circuit output takes place difference adds 1, the potential difference value of the low level of this minuend is added 1 as the merchant, and according to the sign bit of sign bit generator output, output there is the merchant result of symbol; Or reception exports zero from the triggering of described arbiter.
Described fixed-point divider also comprises: the dividend register that removes number register and storage dividend of storage divisor.
A kind of fixed-point divider is realized the method for computing, may further comprise the steps:
A. obtain the absolute value of divisor and dividend; According to the sign bit of divisor and dividend, obtain merchant's sign bit and storage;
B. whether judge the dividend absolute value more than or equal to the divisor absolute value, if, then calculate highest significant position poor of the highest significant position of dividend and divisor, obtain potential difference, enter step C; Otherwise output zero also finishes;
C. according to merchant's sign bit, divisor or dividend absolute value, and potential difference is obtained the quotient of dividend and divisor.
The method of obtaining divisor and dividend absolute value described in the steps A is:
Judge the value of the most significant digit of described divisor or dividend, if the most significant digit of described divisor or dividend is 0, then the absolute value of divisor or dividend equals self, otherwise the absolute value of divisor or dividend equals the complement code of divisor or dividend.
The method of obtaining merchant's sign bit described in the steps A is:
Whether the most significant digit of judging described divisor and dividend equate, if equate, then Shang sign bit is being for just, otherwise merchant's symbol is to bear.
Described step C specifically comprises:
C1. the potential difference position moves to left described dividend absolute value, and calculate the divisor absolute value as subtrahend with move to left after dividend absolute value poor as minuend, judge that whether this difference is less than 0, if, then minuend is moved to left 1, as the minuend of subtraction next time, otherwise, this difference is moved to left 1 and add 1, as the minuend of subtraction next time;
C2. begin to count to increase progressively 1 mode, carry out the subtraction of step C1 repeatedly, till the count value of counter was greater than the potential difference value, the potential difference value of the low level of output minuend absolute value added 1;
C3. the potential difference value with the low level of this minuend absolute value adds 1 as the merchant, and according to described sign bit, output has the merchant result of symbol.
Described step C3 specifically comprises:
Whether the absolute value of judging dividend is less than the absolute value of divisor, if then the merchant is zero;
Otherwise, judge further whether described sign bit is 1, if, then discuss to subtracting 1 behind the potential difference position that numerical value 1 is moved to left, income value and minuend are carried out the negative value of logic and operation, otherwise, discuss to subtracting 1 behind the potential difference position that numerical value 1 is moved to left, income value and minuend are carried out the value of logic and operation.
As seen from the above technical solution, fixed-point divider of the present invention changes into shift operation and subtraction to division arithmetic, compared with prior art, be convenient to the realization of hardware circuit, less used device door number has shortened operation time, improve operation efficiency, obtained effect preferably.
Description of drawings
Fig. 1 is that fixed-point divider of the present invention is formed synoptic diagram;
Fig. 2 is that symbol generator of the present invention is formed synoptic diagram;
Fig. 3 is that dividend absolute value generation circuit of the present invention is formed synoptic diagram;
Fig. 4 a is that the highest significant position of the dividend in the potential difference generator of the present invention is counted generation circuit composition synoptic diagram;
Fig. 4 b is that the potential difference generation circuit in the potential difference generator of the present invention is formed synoptic diagram;
Fig. 5 a is that the difference generation circuit of divisor in merchant's generator of the present invention and dividend is formed synoptic diagram;
Fig. 5 b is that circuit composition synoptic diagram takes place the merchant in merchant's generator of the present invention.
Embodiment
Core concept of the present invention is: obtain the absolute value of divisor and dividend, according to the sign bit of divisor and dividend, obtain merchant's sign bit and storage; Whether judge the dividend absolute value more than or equal to the divisor absolute value, if then calculate numerical digit poor of the highest significant position of the highest significant position of dividend and divisor, obtain potential difference, and according to merchant's sign bit, divisor or dividend absolute value, and potential difference is obtained the quotient of dividend and divisor; Otherwise output zero.
For making purpose of the present invention, technical scheme and advantage clearer, below with reference to the accompanying drawing preferred embodiment that develops simultaneously, the present invention is described in more detail.
Fig. 1 is that fixed-point divider of the present invention is formed synoptic diagram, fixed-point divider of the present invention comprises: the register of sign bit generator 100, absolute value generator 101, arbiter 102, potential difference generator 103, merchant's generator 104 and storage data, the not shown register that is used to store the operational data result among Fig. 1.
Wherein, symbol generator 100 receives divisor and dividend, by judging the sign bit of divisor and dividend, obtain merchant's sign bit, and output is preserved respectively.
The method of described judgement can be: whether the most significant digit of judging divisor and dividend equate, if equate, then Shang most significant digit be 0 promptly merchant's symbol for just, otherwise, merchant's most significant digit be 1 promptly merchant's symbol be to bear.
The method of computing can be: if the most significant digit of divisor/dividend is 0, then the absolute value of divisor/dividend equals self, otherwise the absolute value of divisor/dividend equals the complement code of divisor/dividend.
Being output as 1 such as arbiter is high level, and then the trigger bit difference generator 103; Otherwise, trigger merchant's generator 104.
Merchant's generator 104, receive merchant's sign bit, divisor/dividend absolute value, and potential difference, with the dividend potential difference position that moves to left, and with divisor as subtrahend, dividend after moving to left as minuend, is calculated the poor of the two, judge that whether difference is less than 0, if, then minuend is moved to left 1, as the minuend of subtraction next time, otherwise, difference is moved to left 1 and add 1, as the minuend of subtraction next time, begin counting simultaneously, carry out above-mentioned subtraction repeatedly, till counter is greater than the potential difference value; get low (potential difference value+1) position conduct merchant of minuend, and, export the merchant result that symbol is arranged according to the sign bit that the sign bit generator is exported; Or reception exports 0 from the triggering of arbiter 102.
Merchant's generator 104 comprises that circuit takes place difference and circuit takes place the merchant, wherein, circuit takes place and receives divisor/dividend absolute value in difference, and potential difference, with the dividend absolute value potential difference position that moves to left, and calculate the divisor absolute value as subtrahend with move to left after dividend absolute value poor as minuend, whether judge difference less than 0, if then minuend is moved to left 1, as the minuend of subtraction next time, otherwise, difference is moved to left 1 and add 1, as the minuend of subtraction next time, begin counting simultaneously, carry out above subtraction repeatedly, till counter is greater than the potential difference value, low (potential difference value+1) position of output minuend absolute value.Specifically, difference generation circuit comprises totalizer, determining device at least, the device sum counter that moves to left, wherein,
The device that moves to left is used to receive divisor absolute value, dividend absolute value and potential difference, with the dividend absolute value potential difference position that moves to left, and exports to totalizer; Perhaps receive first notice from determining device, the minuend absolute value of self exporting moves to left 1, and the result is exported to totalizer; Perhaps receive difference, difference is moved to left 1 and add 1, and the result is exported to totalizer, send the counting notice to counter simultaneously from totalizer;
Described totalizer is used to receive the divisor absolute value and from the value of the device output that moves to left, calculates the value of the difference of the two, and the result is exported to determining device; Perhaps receive second notice, difference is exported to the device that moves to left from determining device;
Determining device is used to receive the difference from totalizer, whether judges this difference less than 0, if, to device output first notice that moves to left, otherwise, to totalizer output second notice;
Counter is used to receive the counting notice from the device that moves to left, and begins counting, and at calculated value during greater than the potential difference value, and the potential difference value of the low level of output minuend absolute value adds 1 and to the merchant circuit takes place.
Circuit takes place and receives the sign bit and poor low (potential difference value+1) position that the minuend absolute value of circuit output takes place of exporting from the sign bit generator in the merchant, with low (potential difference value+1) of this minuend position as discussing, and, export the merchant result that symbol is arranged according to the sign bit that the sign bit generator is exported; Or reception exports 0 from the triggering of arbiter.
In conjunction with Fig. 1, fixed-point divider of the present invention realizes that the method for computing comprises: the absolute value that obtains divisor and dividend; According to the sign bit of divisor and dividend, obtain merchant's sign bit and storage; Whether judge the dividend absolute value more than or equal to the divisor absolute value, if then calculate highest significant position poor of the highest significant position of dividend and divisor, obtain potential difference, according to merchant's sign bit, divisor or dividend absolute value, and potential difference is obtained the quotient of dividend and divisor; Otherwise, output zero.
Wherein, the method of obtaining divisor and dividend absolute value is: judge the value of the most significant digit of described divisor/dividend, if the most significant digit of described divisor/dividend is 0, then the absolute value of divisor/dividend equals self, otherwise the absolute value of divisor/dividend equals the complement code of divisor/dividend.
Wherein, the method for obtaining merchant's sign bit is: whether the most significant digit of judging described divisor and dividend equate, if equate, then Shang sign bit is being for just, otherwise merchant's symbol is to bear.
Wherein, according to merchant's sign bit, divisor absolute value or dividend absolute value, and potential difference, the method position that obtains the quotient of dividend and divisor:
At first, with the described dividend absolute value potential difference position that moves to left, and calculate the divisor absolute value as subtrahend with move to left after dividend absolute value poor as minuend, whether judge this difference less than 0, if then the minuend absolute value is moved to left 1, as the minuend of subtraction next time, otherwise, this difference is moved to left 1 and add 1, as the minuend of subtraction next time;
Afterwards, beginning is counted to increase progressively 1 mode, carries out the subtraction of step C1 repeatedly, and till the count value of counter was greater than the potential difference value, the potential difference value of the low level of output minuend absolute value added 1;
At last, the potential difference value of the low level of this minuend absolute value is added 1 as the merchant, and according to described sign bit, output has the merchant result of symbol, specific implementation comprises: whether the absolute value of judging dividend is less than the absolute value of divisor, if then the merchant is zero; Otherwise, judge further whether described sign bit is 1, if, then discuss to subtracting 1 behind the potential difference position that numerical value 1 is moved to left, income value and minuend are carried out the negative value of logic and operation, otherwise, discuss to subtracting 1 behind the potential difference position that numerical value 1 is moved to left, income value and minuend are carried out the value of logic and operation.
Introduce the realization of each ingredient of divider of the present invention below respectively in detail for embodiment.
Fig. 2 is that symbol generator of the present invention is formed synoptic diagram, as shown in Figure 2, sign bit generator 100 mainly comprises recombiner (MUX) 21, MUX22 and XOR gate XOR, wherein, for MUX21, when enable signal Call0_RE is 0, be output as except that number register Divisor_2[31:1] sign bit, otherwise, be output as divisor Call0 divisor[31:0] sign bit; For MUX22, when enable signal Call0 RE is 0, be output as dividend Dividend_2[31:1] sign bit, otherwise, be output as dividend register Call0_dividend[31:0] sign bit, promptly under the control of enable signal Call0_RE, the most significant digit of exporting divisor and dividend respectively is a sign bit, and XOR gate XOR receives respectively from the divisor of MUX21 and MUX22 and the sign bit of dividend, and after carrying out XOR, obtain merchant's sign bit, and output is kept in the sign bit register.
Need to prove that enable signal Call0_RE belongs to system control information, by system logic sequential control under the divider, the supposing the system signal pre-sets here.
Fig. 3 is that dividend absolute value generation circuit of the present invention is formed synoptic diagram, as shown in Figure 3, dividend absolute value generator mainly comprises MUX31, MUX32, not gate NOR and totalizer ADD, wherein, for MUX31, when enable signal Call0_RE is 0, be output as and remove number register Dividend_2[31:1], otherwise, be output as dividend Call0_dividend[31:1], promptly under the control of enable signal Call0_RE, output is from the 1st～31 input end to MUX32 of the dividend of dividend register, simultaneously with the first input end of the 1st～31 input summer ADD after input terminal drives synchronously; The lowest order that not gate NOR receives dividend is the 0th, the first input end of negate output adder ADD, and with the 1st～31 merging of dividend after as the input signal of totalizer first input end, input signal 1 addition of second input end of this input signal and totalizer ADD, and export another input end of MUX32 to; The control end signal of MUX32 is the 31st signal of dividend, if the 31st be 0, then MUX32 output is from the 1st to 31 of the dividend of dividend register, and with the 0th merging through not gate NOR negate after be kept in the dividend absolute value register; If the 31st be 1, then MUX32 output is from the 1st to 31 of the dividend of totalizer ADD output, and with the 0th merging through not gate NOR negate after be kept in the dividend absolute value register.
Fig. 3 only is wherein a kind of implementation, and the purpose of absolute value generator 101 is exactly to calculate the complement code of dividend.Realization and Fig. 3 of divisor absolute value generator are in full accord, just divisor are calculated complement code.
Fig. 4 a is that the highest significant position of the dividend in the potential difference generator of the present invention is counted generation circuit composition synoptic diagram, shown in Fig. 4 a, the highest significant position of dividend is counted the generation circuit and is mainly comprised some and a door AND, MUX41, MUX42 reaches or door OR, processing procedure is as follows: dividend temporary register temp Dividend is used to preserve intermediate result, with the input of door AND41 be that the negate of 32 signals of dividend temporary register temp Dividend output is an inverse, promptly when dividend temporary register temp Dividend exports everybody and is 0, AND41 is output as 1, otherwise it is output as 0.AND42 first input signal is from system logic sequential (not shown among Fig. 4 a), second input signal is the inverse of the output signal of AND41, the signal of AND42 output give respectively AND43 and or door OR, the output of AND43 is as the gating signal of MUX41, when this gating signal was 0, MUX41 was output as 0, otherwise, MUX41 is output as the output signal of ADD41, and the output of each MUX41 all is saved among the register m.The input of totalizer ADD41 is respectively from the output of register m and the output of AND42, and the output of ADD41 sends to one of them input end of MUX41, when the gating signal of MUX41 is 1, the signal of this input end is sent to register m.Realize the statistics of the highest significant position number of dividend by this circuit, and the result is kept among the register m.
Fig. 4 b is that the potential difference generation circuit in the potential difference generator of the present invention is formed synoptic diagram, shown in Fig. 4 b, potential difference generation circuit mainly comprises some totalizer ADD, MUX43 and MUX44, processing procedure is as follows: first input of ADD42 is from the output of register n, second input is from the output of register m, promptly realize the operation of the difference of n and m, and result's output is stored among the potential difference register M_N.Effect and the ADD41 of ADD43 among Fig. 4 b are similar, and same, the effect of MUX43 is also similar with MUX44, is used to obtain the highest significant position number of divisor, repeats no more here.
Fig. 5 a is that the difference generation circuit of divisor in merchant's generator of the present invention and dividend is formed synoptic diagram, shown in Fig. 5 a, processing procedure is as follows: recombiner MUX[31:0] the data of first input end from divisor absolute value register, about divisor absolute value generation circuit, similar with the dividend absolute value generation circuit that Fig. 3 describes, repeat no more here.Recombiner MUX[31:0] the data of second input end from the device LSH that moves to left, as recombiner MUX[31:0] gating signal when being 0, recombiner MUX[31:0] export the divisor absolute value to subtrahend register subtrahend[31:0] in, otherwise, the output data output of the device LSH that moves to left is stored in the subtrahend register, and first input of the device LSH that moves to left is from the subtrahend register, second input is from the M_N register, therefore, the purpose of this part circuit is: at first the absolute value with divisor deposits the subtrahend register in, then, to the M_N position that moves to left of the data in the subtrahend register, and deposit the result in the subtrahend register once more by LSH;
Totalizer ADD[31:0] be used to carry out minuend minuend[31:0] with subtrahend subtrahend[31:0] the computing of difference, the output result is kept at poor register difference register alu[31:0] in.Comparer LT is used for judging the M_N[5:0 of potential difference register] whether greater than the i[5:0 in the counter register], if greater than, then by with door AND[0] the output control signal, notice alu[31:0] receive ADD[31:0] output data.Two purposes with door AND are to judge alu[31:0] most significant digit whether be 1, if, then by multichannel recombiner MUX[30:0] export alu[31:0] move to left 1 data and be stored in the minuend register; Otherwise, output alu[31:0] and moving to left adds 1 after 1, and the result is passed through MUX[30:0] send and be stored in the minuend register.
Fig. 5 b is that circuit composition synoptic diagram takes place the merchant in merchant's generator of the present invention, shown in Fig. 5 b, processing procedure is as follows: be used to judge sign bit register Sign[0 with door AND2 and AND3] output whether be 0, if, then control multichannel recombiner MUX1[31:0] gating exports from AND4[31:0] data, otherwise, MUX1[31:0] gating exports from ADD3[31:0] data.ADD1[5:0], device LSH, ADD2[31:0 move to left] and AND4[31:0] purpose be to realize dividend minuend﹠amp; ((1＜＜(M_N+1))-1) computing, Qi Zhong ﹠amp; Presentation logic with.And not gate NOR[0], input terminal IN[31:1] and ADD3[31:0] purpose be in order to obtain-(minuend﹠amp; ((1＜＜(M_N+1))-1)) be ADD3[31:0] send to MUX1[31:0] data be-(minuend﹠amp; ((1＜＜(M_N+1))-1)).MUX1[31:0] the gating signal of the 3rd group of input end from a comparer, not shown among Fig. 5 b, this comparer judges that whether the absolute value of divisor is less than dividend, if, then this comparer is output as 0, get non-back as MUX1[31:0] the gating signal of the 3rd group of input terminal, and the data of the 3rd group of input terminal output are 0.
Therefore merchant shown in Fig. 5 b the processing procedure of circuit takes place is: whether the absolute value of judging dividend less than divisor, if, MUX1[31:0 then] merchant that exports is 0;
Otherwise, further judge Sign[0] whether be 1, if, MUX1[31:0 then] merchant of output is-minuend﹠amp; ((1＜＜(M_N+1))-1), promptly described 32 bit value 1 of will presetting move to left and subtract one behind the potential difference position, and income value and minuend are carried out the negative value of logic and operation; Otherwise, Sign[0] and be 0, MUX1[31:0 then] merchant of output is minuend﹠amp; ((1＜＜(M_N+1))-1).Be that described 32 bit value 1 of will presetting move to left and subtract one behind the potential difference position, income value and minuend are carried out the value of logic and operation.MUX2 among Fig. 5 b is actual to be exactly MUX among Fig. 5 a.Below just provide the wherein circuit diagram implementation of a kind of embodiment, and be not used in qualification divider of the present invention.What the present invention emphasized is that divider of the present invention changes into shift operation and subtraction to division arithmetic, compared with prior art, be convenient to the realization of hardware circuit, less used device door number has shortened operation time, improve operation efficiency, obtained effect preferably.
The division module that provides in the logic circuit development instrument of divider of the present invention and the Handel C of Celoxica company its result that compares is as shown in table 1.For being 32 division arithmetics equally, the hardware resource that the present invention consumed has only 14% of above-mentioned division module, and the needed largest logical time in path delay is its 3.8%.
| The division module of Celoxica | The present invention | |
| The gate equivalent circuit number | 44,019 | 6,268 |
| Greatest combined logical path time delay | 333.098ns | 12.665ns |
Table 1
The above is preferred embodiment of the present invention only, is not to be used to limit protection scope of the present invention, all any modifications of being made within the spirit and principles in the present invention, is equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (11)
1. a fixed-point divider is characterized in that, this fixed-point divider comprises:
Symbol generator (100) receives divisor and dividend, obtains merchant's sign bit and output according to the sign bit of divisor and dividend;
Absolute value generator (101) receives divisor and dividend, obtains the absolute value of divisor and dividend, and output;
Arbiter (102) receives divisor absolute value and dividend absolute value respectively, whether judges the dividend absolute value more than or equal to the divisor absolute value, if, trigger bit difference generator (103) then; Otherwise, trigger merchant's generator (104);
Potential difference generator (103) receives divisor and dividend absolute value respectively, and the highest significant position that calculates dividend is poor with the highest significant position of divisor, obtains the dividend absolute value and also exports with the potential difference of divisor absolute value;
Merchant's generator (104) receives merchant's sign bit, the absolute value of divisor, the absolute value of dividend, and potential difference, and output has the merchant result of symbol; Perhaps receive triggering, output zero from arbiter (102).
2. fixed-point divider according to claim 1 is characterized in that, described fixed-point divider also comprises divisor absolute value register and dividend absolute value register; Described absolute value generator (101) comprises divisor absolute value generator and dividend absolute value generator;
Described divisor absolute value generator is used to receive divisor, obtains the divisor absolute value, and described divisor absolute value is outputed to divisor absolute value register;
Described dividend absolute value generator is used to receive dividend, obtains the dividend absolute value, and described dividend absolute value is outputed in the dividend absolute value register.
3. fixed-point divider according to claim 1 and 2 is characterized in that, described potential difference generator (103) comprises that highest significant position counts generation circuit and potential difference generation circuit;
Described highest significant position is counted the generation circuit, is used to receive divisor absolute value or dividend absolute value, obtains the highest significant position number and the output of divisor or dividend respectively;
Described potential difference generation circuit, be used to receive the highest significant position number of divisor and the highest significant position number of dividend, calculate numerical digit poor of the highest significant position of the highest significant position of dividend and divisor, obtain the potential difference of dividend absolute value and divisor absolute value, and described potential difference is outputed in the potential difference register.
4. fixed-point divider according to claim 3 is characterized in that, described fixed-point divider also comprises first register and second register; Described highest significant position generation circuit comprises that the divisor highest significant position is counted the generation circuit and the dividend highest significant position is counted the generation circuit;
Described divisor highest significant position is counted the generation circuit, is used to receive the divisor absolute value, obtains the highest significant position number of divisor, and the highest significant position number of described divisor is outputed in first register;
Described dividend highest significant position is counted the generation circuit, is used to receive the dividend absolute value, obtains the highest significant position number of dividend, and the highest significant position number of described dividend is outputed in second register.
5. fixed-point divider according to claim 1 and 2 is characterized in that, described merchant's generator (104) comprising: circuit takes place difference and circuit takes place the merchant;
Described difference generation circuit comprises totalizer, determining device at least, the device sum counter moves to left;
Wherein, the described device that moves to left is used to receive divisor absolute value, dividend absolute value and potential difference, with the dividend absolute value potential difference position that moves to left, and exports to totalizer; Perhaps receive first notice from determining device, the minuend absolute value of self exporting moves to left 1, and the result is exported to totalizer; Perhaps receive difference, difference is moved to left 1 and add 1, and the result is exported to totalizer, send the counting notice to counter simultaneously from totalizer;
Described totalizer is used to receive the divisor absolute value and from the value of the device output that moves to left, calculates the value of the difference of the two, and the result is exported to determining device; Perhaps receive second notice, difference is exported to the device that moves to left from determining device;
Described determining device is used to receive the difference from totalizer, whether judges this difference less than 0, if, to device output first notice that moves to left, otherwise, to totalizer output second notice;
Described counter is used to receive the counting notice from the device that moves to left, and begins counting, and at calculated value during greater than the potential difference value, and the potential difference value of the low level of output minuend absolute value adds 1 and to the merchant circuit takes place;
Circuit takes place in described merchant, the potential difference value that receives the low level of merchant's sign bit and the minuend that circuit output takes place difference adds 1, the potential difference value of the low level of this minuend is added 1 as the merchant, and according to the sign bit of sign bit generator output, output there is the merchant result of symbol; Or reception exports zero from the triggering of described arbiter.
6. fixed-point divider according to claim 1 is characterized in that, described fixed-point divider also comprises: the dividend register that removes number register and storage dividend of storage divisor.
7. the method for a fixed-point divider realization computing is characterized in that, may further comprise the steps:
A. obtain the absolute value of divisor and dividend; According to the sign bit of divisor and dividend, obtain merchant's sign bit and storage;
B. whether judge the dividend absolute value more than or equal to the divisor absolute value, if, then calculate highest significant position poor of the highest significant position of dividend and divisor, obtain potential difference, enter step C; Otherwise output zero also finishes;
C. according to merchant's sign bit, divisor or dividend absolute value, and potential difference is obtained the quotient of dividend and divisor.
8. method according to claim 7 is characterized in that, the method for obtaining divisor and dividend absolute value described in the steps A is:
Judge the value of the most significant digit of described divisor or dividend, if the most significant digit of described divisor or dividend is 0, then the absolute value of divisor or dividend equals self, otherwise the absolute value of divisor or dividend equals the complement code of divisor or dividend.
9. method according to claim 7 is characterized in that, the method for obtaining merchant's sign bit described in the steps A is:
Whether the most significant digit of judging described divisor and dividend equate, if equate, then Shang sign bit is being for just, otherwise merchant's symbol is to bear.
10. method according to claim 7 is characterized in that, described step C specifically comprises:
C1. the potential difference position moves to left described dividend absolute value, and calculate the divisor absolute value as subtrahend with move to left after dividend absolute value poor as minuend, judge that whether this difference is less than 0, if, then minuend is moved to left 1, as the minuend of subtraction next time, otherwise, this difference is moved to left 1 and add 1, as the minuend of subtraction next time;
C2. begin to count to increase progressively 1 mode, carry out the subtraction of step C1 repeatedly, till the count value of counter was greater than the potential difference value, the potential difference value of the low level of output minuend absolute value added 1;
C3. the potential difference value with the low level of this minuend absolute value adds 1 as the merchant, and according to described sign bit, output has the merchant result of symbol.
11. method according to claim 10 is characterized in that, described step C3 specifically comprises:
Whether the absolute value of judging dividend is less than the absolute value of divisor, if then the merchant is zero;
Otherwise, judge further whether described sign bit is 1, if, then discuss to subtracting 1 behind the potential difference position that numerical value 1 is moved to left, income value and minuend are carried out the negative value of logic and operation, otherwise, discuss to subtracting 1 behind the potential difference position that numerical value 1 is moved to left, income value and minuend are carried out the value of logic and operation.
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