CN111104092A

CN111104092A - Fast divider and division operation method

Info

Publication number: CN111104092A
Application number: CN201911242077.9A
Authority: CN
Inventors: 马贵霞; 柳会鹏
Original assignee: Beijing Duosi Security Chip Technology Co Ltd
Current assignee: Beijing Duosi Security Chip Technology Co Ltd
Priority date: 2019-12-06
Filing date: 2019-12-06
Publication date: 2020-05-05
Anticipated expiration: 2039-12-06
Also published as: CN111104092B

Abstract

The invention discloses a fast divider and a division operation method, wherein the fast divider comprises an effective bit scanning module and an operation module, and the operation module comprises a divisor multiple prejudging unit, a subtraction unit, a quotient generating unit and a remainder generating unit; the effective bit scanning module is used for scanning and determining effective bits of the divisor and the dividend, and determining an initial remainder and the times of iterative subtraction; the divisor multiple prejudging unit is used for determining the divisor multiple used for each iteration operation; the subtraction unit is used for realizing subtraction iterative operation of the initial remainder or the new remainder and N times of the divisor; the remainder generation unit is used for complementing the unprocessed highest i-bit binary number of the dividend to the difference value to generate a new remainder; and the quotient generation unit is used for determining the quotient of each iteration, and the final quotient is generated by combining the quotient of each iteration according to the iteration sequence. According to the scheme, the number of times of iterative subtraction operation can be reduced by determining the effective bit, and the iterative quotient is pre-judged by selecting and comparing the number with a reasonable divisor multiple, so that the number of subtracters is reduced, the operation scale is reduced, and the operation speed is improved.

Description

Fast divider and division operation method

Technical Field

The invention relates to the technical field of chips, in particular to a fast divider and a division operation method.

Background

At present, most of the conventional chip integer division methods adopt a mode of recovering a remainder from a complementary bit in a dividend, and the method is a method for realizing division calculation by simulating manual work. The above algorithm determines the operation speed by the number of bits per quotient, but as the number of quotient bits increases, the hardware resources used for division operation also increase by a multiple. In the current big data cloud computing era, the requirements on the operation specification and the operation speed are improved, so that how to improve the speed of integer division operation and reduce the occupation of hardware resources is a problem which needs to be solved urgently at present.

Disclosure of Invention

In view of the above, the present invention has been developed to provide a fast divider and a division operation method that overcome or at least partially solve the above-mentioned problems.

According to one aspect of the present invention, a fast divider is provided, which includes an effective bit scanning module and an operation module, where the operation module includes a divisor multiple prejudging unit, a subtraction unit, a remainder generating unit, and a quotient generating unit;

the effective bit scanning module is used for scanning and determining effective bits of the divisor and the dividend, and determining an initial remainder and the times of iterative subtraction;

the divisor multiple prejudging unit is used for determining the divisor multiple used for each iteration operation through comparison operation of a remainder and the divisor multiple according to the effective bit scanning result;

the subtraction unit is used for realizing subtraction iterative operation of the initial remainder or the new remainder and N times of the divisor;

the remainder generation unit is used for acquiring a difference value of the subtraction iterative operation, complementing the unprocessed highest i-bit binary number of the dividend on the difference value to generate a new remainder, and the maximum value of the new remainder is not more than an i-th power divisor of 2;

and the quotient generation unit is used for determining an i-bit binary number of N times of the divisor as a quotient of each iteration, and the final quotient is generated by combining the quotient of each iteration according to an iteration sequence.

Optionally, the valid bit scanning module performs packet scanning on the dividend and the divisor according to an integer multiple of i, and the obtained number of valid bits of the dividend and the divisor is an integer multiple of i.

Optionally, the subtraction unit includes k subtractors, each of which implements a block subtraction iterative operation, where k is determined according to a maximum integer value of an i-bit binary system.

Optionally, the value of i is 4, and the value of k is 5.

Optionally, the subtraction unit includes k memories, and each memory is used for storing an operation result of the iterative subtraction operation.

In accordance with another aspect of the present invention, there is provided a method of dividing, the method comprising:

scanning and determining the effective bits of the divisor and the dividend, and determining the initial remainder and the times of iterative subtraction;

determining divisor multiples used for each iterative operation through comparison operation of a remainder and the divisor multiples according to the effective bit scanning result;

performing subtraction iteration operation on the initial remainder or the new remainder and N times of the divisor;

obtaining a difference value of the subtraction iterative operation, and carrying out bit complement on the difference value by using the unprocessed highest i-bit binary number of the dividend to generate a new remainder, wherein the maximum value of the new remainder is not more than an i-th power divisor of 2;

and determining an i-bit binary number of N times of the divisor as a quotient of each iteration, and finally combining the quotient of each iteration according to an iteration sequence to generate the quotient.

Optionally, the scanning and determining the significant bits of the divisor and the dividend, and determining the initial remainder and the number of iterative subtractions includes:

scanning a dividend and a divisor according to a group of i bits, and determining effective bits of the dividend and the divisor, wherein the number of the effective bits is an integral multiple of i.

Optionally, the performing subtraction iteration operation on the implementation remainder and the N times of the divisor includes:

and setting k subtracters to realize the iterative operation of the grouped subtraction, wherein k is i or i + 1.

Optionally, the value of i is 4, and the value of k is 5.

Optionally, the setting k subtractors to implement the iterative operation of the block subtraction further includes:

and setting k memories corresponding to the subtractors and storing the operation result of the iterative subtraction operation.

In accordance with still another aspect of the present invention, there is provided an electronic apparatus including: a processor; and a memory arranged to store computer executable instructions that, when executed, cause the processor to perform a method as any one of the above.

According to a further aspect of the invention, there is provided a computer readable storage medium, wherein the computer readable storage medium stores one or more programs which, when executed by a processor, implement a method as any one of the above.

The fast divider disclosed by the invention comprises an effective bit scanning module and an operation module, wherein the operation module comprises a divisor multiple pre-judging unit, a subtraction unit, a quotient generating unit and a remainder generating unit; the effective bit scanning module is used for scanning and determining effective bits of the divisor and the dividend, and determining an initial remainder and the times of iterative subtraction; the divisor multiple pre-judging unit combines the effective bit scanning result to add a new remainder and a divisor multiple comparison operation to determine the divisor multiple used for each iteration operation; carrying out subtraction iterative operation on N times of divisor of the subtraction unit; the remainder generation unit is used for acquiring the difference value of the subtraction iterative operation and the unprocessed highest i-bit binary complement of the dividend to form a remainder; the quotient generation unit is used for acquiring an i-bit binary number which is N times of the divisor as a quotient of the j iteration, and the final quotient is formed by combining the quotient of each iteration according to an iteration sequence. The division multiple pre-judging unit selects the division from N times to M times according to the scanning result of the effective digits of the division to perform subtraction iterative operation, and selects reasonable pre-comparison division multiple values to achieve the number of subtractors, so that the operation scale is reduced, and the operation speed is improved.

The foregoing description is only an overview of the technical solutions of the present invention, and the embodiments of the present invention are described below in order to make the technical means of the present invention more clearly understood and to make the above and other objects, features, and advantages of the present invention more clearly understandable.

Drawings

Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the invention. Also, like reference numerals are used to refer to like parts throughout the drawings. In the drawings:

FIG. 1 is a block diagram illustrating a fast divider according to an embodiment of the present invention;

FIG. 2 is a flow diagram illustrating a method of trigger operations according to an embodiment of the invention;

FIG. 3 shows a schematic structural diagram of an electronic device according to one embodiment of the invention;

fig. 4 shows a schematic structural diagram of a computer-readable storage medium according to an embodiment of the present invention.

Detailed Description

Exemplary embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the invention are shown in the drawings, it should be understood that the invention can be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.

FIG. 1 is a block diagram illustrating a fast divider according to an embodiment of the present invention; wherein the fast divider 100 comprises:

the device comprises an effective digit scanning module 110 and an operation module 120, wherein the operation module comprises a divisor multiple prejudging unit, a subtraction unit 122, a remainder generating unit 123 and a quotient generating unit 124.

The significant bit scanning module 110 is used to scan and determine the significant bits of the divisor and dividend, and to determine the initial remainder and the number of iterative subtractions.

The 110 module of this embodiment is used to determine the significant bits of the divisor and dividend. In a typical division operation, the division algorithm does not know the size of the divisor and dividend, and therefore, it needs to scan from the highest order bits of the storage device and start an iterative operation when performing the operation. If the memory device is a 64-bit or 128-bit memory, however, the divisor or dividend may occupy only a small portion of the memory bits, such as a divisor of 11 and a dividend of 100, the scanning method will waste a lot of computation time.

Therefore, by arranging the effective bit scanning module, the highest bit group participating in the operation is determined at the calculation position, and the initial remainder and the iterative subtraction times are determined, so that the time occupied by the operation is greatly reduced.

The divisor multiple prejudging unit 121 is configured to determine a divisor multiple of each iteration operation through a remainder and divisor multiple comparison operation according to an effective bit scanning result.

When iterative subtraction is performed each time, particularly when the value i of the complement bit of each iteration is large, the relationship between the new remainder and the divisor needs to be judged, and the number of times that the new remainder is the divisor needs to be calculated specifically, so that the subsequent subtraction operation is facilitated.

The subtraction unit 122 is configured to determine whether the significant bit of the dividend is greater than the significant bit of the divisor, and if so, obtain the unprocessed highest i-bit binary number of the dividend to complement the remainder, and then perform subtraction iteration operation with N times of the divisor.

The operation of the invention mainly aims at integer operation of which dividend is larger than divisor to obtain final quotient and remainder. The initial value of the quotient and remainder is generally set to 0 during operation, and then a complementary bit loop subtraction iteration is performed according to the set value of i, so as to obtain a final result, where i may be a positive integer such as 1,2,3,4, etc., and may be referred to as 1-bit 1 division, 2-bit 1 division, 3-bit 1 division, 4-bit 1 division, etc., respectively. Example of division with dividend a of 1101, divisor B of 0010, and remainder each complement bit of 1 (1-bit 1 division):

number of iterations	Remainder (R)	Quotient (Q)	Division formula (R/B)
				0	0000	0000
1	0001	0000	0001/0010
				2	0011	0001	0011/0010
3	0010	0011	0010/0010
				4	0001	0110	0001/0010

According to the final result, the dividend is 13, the divisor is 2, the remainder is 1, and the quotient is 6.

In actual operation, the dividend and the divisor are simultaneously scanned from the highest-order group according to the operation specification, scanning quits when the first group which is not 0 is found respectively, and initial quotient, remainder and subtraction specification are set according to the scanning result. When the divisor is larger than the dividend, the dividend is directly output as the remainder without performing circular subtraction operation, and the quotient is 0. When the dividend is greater than or equal to the divisor, it needs to be set: if the dividend is divided into i 0 groups, the divisor has j 0 groups, and the operation specification is COUNT groups, then:

the effective packet length of the subtraction specification is equal to the divisor COUNT-j;

grouping 0 initial remainder of the 0 th non-0 grouping dividend … … th non-0 grouping of the 1 st non-0 grouping dividend, where m is COUNT-j-1;

initial quotient n 0 groups i + (COUNT-j-1) 0 groups;

and (3) cycle reduction times: { (COUNT-i-j +1) × packet length }/2 (two-bit one divided design); { (COUNT-i-j +1) × packet length }/4 (four bits by one divided design).

The remainder generating unit 123 is configured to obtain a remainder formed by the difference value of the iterative subtraction operation and the unprocessed highest i-bit binary complement bits of the dividend, where the number of bits of the remainder is the same as the number of binary bits of the divisor.

As shown in the table above, the remainder is initialized to zero, the number of bits is the same as that of the divisor, and each iteration reads a set of i-bit binary numbers of the most significant bit of the dividend and subtracts the i-bit binary numbers from the integer N times the divisor.

The quotient generation unit 124 is configured to determine an i-bit binary number of N times of the divisor as a quotient of the j-th iteration, and a final quotient is formed by combining the quotients of the iterations in an iteration order.

After the dividend and the effective digits of the divisor are determined, the multiple relation of the new remainder relative to the divisor can be pre-determined according to the effective digits of the divisor, so that the number of subtractors used and the number of adders used for calculating the multiple of the divisor can be reduced. If i-bit (positive integers such as 1,2,3,4, etc.) binary numbers are converted into integers, the maximum values are 1, 3, 7, 15, 31, etc., and 2, 4, 8, 16, 32 subtractors are generally needed to realize subtraction operation.

In order to obtain the balance between the number of subtraction iterations and the number of subtractors, i may be preferably 4, and the number of subtractors may be preferably 16.

In summary, in the technical solution disclosed in this embodiment of the present invention, the significant bits are scanned and the i value with a proper number of bits is selected for bit compensation, so that hardware resources occupied by division operation are reduced, and the operation occupation time is increased, thereby improving the overall benefit.

In one embodiment, the number of significant bits of the dividend and divisor is an integer multiple of i.

For subsequent division and subtraction operations, the initial remainder and the iterative subtraction times are set by using the obtained significant digits by scanning the significant digits of the dividend and the divisor, the digits of the significant digits of the dividend and the divisor are integer multiples of i, the significant digits of the dividend and the divisor are determined to be equal to integer multiples of the value of i, namely, the scanning of the first i-digit binary group which is not all 0 is finished as the significant digits of the divisor or the dividend from the top end of the memory.

In one embodiment, the subtraction unit 121 includes k subtractors, each of which implements a block subtraction iterative operation, where k is a positive integer and is determined according to the maximum value of an i-bit binary number plus a 1 integer division.

As described above, if the binary number of i (1,2,3,4, etc. positive integer) bits is converted into an integer, the maximum values are 1, 3, 7, 15, 31, etc., respectively, in order to realize the subtraction operation, it is generally necessary to provide 2, 4, 8, 16, 32 subtractors respectively for realizing the subtraction of 0 times divisor, 1 times divisor, … 31 times divisor, etc., of 2 times divisor. Thus, the number of subtractors is large, and hardware resources are excessively occupied, and for this reason, in this embodiment, the subtraction operations are grouped according to the integer division of the maximum value of the i-bit binary number plus 1, thereby reducing the number of subtractors.

In a preferred embodiment, i is 4, and k is 5.

Taking the divider of four bits and one division as an example, the number of the subtractors is 15 and the storage specification is 32 bits. If the new remainder is found according to the effective bit scanning result, the first address of the new remainder is compared to read four-digit binary data and is compared with 4 times of divisor, 8 times of divisor and 12 times of divisor, so that the dividend multiple for circular subtraction is judged, five subtractors are divided according to a certain rule to realize the operations of subtraction and storage, and the specific rule is shown in the following table:

subtractor 1	Subtractor 2	Subtractor 3	Subtractor 4	Subtractor 5
					0	1 time divisor	2 times divisor	3 times divisor	4 times divisor
4 times divisor	Divisor 5 times	6 times divisor	7 times divisor	Divisor 8 times
					Divisor 8 times	Divisor 9 times	Divisor of 10 times	Divisor of 11 times	12 times divisor
12 times divisor	Divisor 13 times	14 times divisor	Divisor 15 times	16 times divisor

The four groups of subtraction operation results are stored by the RAM (random access memory) such as 5 memories and the like until the subtraction specification is finished to store the borrow marks of the four groups of subtraction operation, and then the cyclic subtraction operation is carried out until the specification of the dividend is completely shifted out.

When the four subtractors of the four-bit one-division are grouped and stored, if four subtractors are selected, the operation of each subtracter can be, for example, the operation of the subtracter 1 for performing the operations of 0-time divisor, 4-time divisor, 8-time divisor and 12-time divisor, the operation of the subtracter 2 for performing the operations of 1-time divisor, 5-time divisor, 9-time divisor and 13-time divisor, and so on. For checking, 5 subtractors may be provided, wherein subtracter 1 performs 0-4 times, subtracter 2 performs 4-8 times, subtracter 3 performs 8-12 times, subtracter 4 performs 12-16 times of divisor, etc.

In one embodiment, the subtraction unit 121 includes k registers corresponding to each of the subtractors, and is configured to store an operation result of the iterative subtraction operation.

FIG. 2 is a flow diagram illustrating a method of trigger operations according to an embodiment of the invention; the method comprises the following steps:

in step S210, the significant bits of the divisor and dividend are scanned and determined, and the initial remainder and the number of iterative subtractions are determined.

Step S220, according to the valid bit scanning result, a divisor multiple for each iteration operation is determined through a remainder and divisor multiple comparison operation.

In step S230, subtraction iteration is performed on the initial remainder or the new remainder and N times of the divisor.

Step S240, obtaining the difference value of the iterative subtraction operation, and performing bit complement on the difference value by using the unprocessed highest i-bit binary number of the dividend to generate a new remainder, where the maximum value of the new remainder is not greater than the i-th divisor multiplied by 2.

And step S250, determining an i-bit binary number of N times of the divisor as a quotient of each iteration, and combining and generating the final quotient by the quotient of each iteration according to an iteration sequence.

In summary, in the method scheme disclosed in this embodiment, the bit is complemented by scanning the valid bit and selecting the i value with a proper number of bits, so as to reduce hardware resources occupied by the division operation, and improve the occupied time of the operation, thereby improving the overall benefit of the division operation.

In one embodiment, the iterating the subtraction with N times the divisor comprises: k subtractors are arranged to realize the grouping subtraction iterative operation, wherein k is a positive integer and is determined according to the maximum value of the i-bit binary number plus 1 integer division.

In one embodiment, i is 4 and k is 5.

In one embodiment, the setting k subtractors to implement a block subtraction iterative operation further includes: and setting k registers corresponding to the subtractors and storing the operation result of the iterative subtraction operation.

In summary, the fast divider disclosed in the present invention includes an effective bit scanning module and an operation module, where the operation module includes a divisor multiple pre-determining unit, a subtraction unit, a quotient generating unit, and a remainder generating unit; the effective bit scanning module is used for scanning and determining the effective bits of the divisor and the dividend; the subtraction unit is used for judging whether the effective digit of the dividend is greater than the effective digit of the divisor, if so, the unprocessed highest i-bit binary number of the dividend is obtained to complement the remainder, and then subtraction iteration operation is carried out on the remainder and N times of the divisor; the remainder generation unit is used for acquiring the difference value of the subtraction iterative operation and the unprocessed highest i-bit binary complement bit of the dividend to form a remainder, and the number of bits of the remainder is the same as the number of binary bits of the divisor; the quotient generation unit is used for acquiring an i-bit binary number which is N times of the divisor as a quotient of the j iteration, and the final quotient is formed by combining the quotient of each iteration according to an iteration sequence. According to the scheme, the number of times of iterative operation of subtraction can be reduced by determining the effective bit, the operation scale is reduced by selecting a reasonable i value and the number of subtracters, and the operation speed is improved.

It should be noted that:

the algorithms and displays presented herein are not inherently related to any particular computer, virtual machine, or other apparatus. Various general purpose devices may be used with the teachings herein. The required structure for constructing such a device will be apparent from the description above. Moreover, the present invention is not directed to any particular programming language. It is appreciated that a variety of programming languages may be used to implement the teachings of the present invention as described herein, and any descriptions of specific languages are provided above to disclose the best mode of the invention.

In the description provided herein, numerous specific details are set forth. It is understood, however, that embodiments of the invention may be practiced without these specific details. In some instances, well-known methods, structures and techniques have not been shown in detail in order not to obscure an understanding of this description.

Similarly, it should be appreciated that in the foregoing description of exemplary embodiments of the invention, various features of the invention are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the invention and aiding in the understanding of one or more of the various inventive aspects. However, the disclosed method should not be interpreted as reflecting an intention that: that the invention as claimed requires more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive aspects lie in less than all features of a single foregoing disclosed embodiment. Thus, the claims following the detailed description are hereby expressly incorporated into this detailed description, with each claim standing on its own as a separate embodiment of this invention.

Those skilled in the art will appreciate that the modules in the device in an embodiment may be adaptively changed and disposed in one or more devices different from the embodiment. The modules or units or components of the embodiments may be combined into one module or unit or component, and furthermore they may be divided into a plurality of sub-modules or sub-units or sub-components. All of the features disclosed in this specification (including any accompanying claims, abstract and drawings), and all of the processes or elements of any method or apparatus so disclosed, may be combined in any combination, except combinations where at least some of such features and/or processes or elements are mutually exclusive. Each feature disclosed in this specification (including any accompanying claims, abstract and drawings) may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise.

Furthermore, those skilled in the art will appreciate that while some embodiments described herein include some features included in other embodiments, rather than other features, combinations of features of different embodiments are meant to be within the scope of the invention and form different embodiments. For example, in the following claims, any of the claimed embodiments may be used in any combination.

The various component embodiments of the invention may be implemented in hardware, or in software modules running on one or more processors, or in a combination thereof. It will be appreciated by those skilled in the art that a microprocessor or Digital Signal Processor (DSP) may be used in practice to implement some or all of the functions of some or all of the components of the fast divider according to embodiments of the present invention. The present invention may also be embodied as apparatus or device programs (e.g., computer programs and computer program products) for performing a portion or all of the methods described herein. Such programs implementing the present invention may be stored on computer-readable media or may be in the form of one or more signals. Such a signal may be downloaded from an internet website or provided on a carrier signal or in any other form.

For example, fig. 3 shows a schematic structural diagram of an electronic device according to an embodiment of the invention. The electronic device 300 comprises a processor 310 and a memory 320 arranged to store computer executable instructions (computer readable program code). The memory 320 may be an electronic memory such as a flash memory, an EEPROM (electrically erasable programmable read only memory), an EPROM, a hard disk, or a ROM. The memory 320 has a storage space 330 storing computer readable program code 331 for performing any of the method steps described above. For example, the storage space 330 for storing the computer readable program code may comprise respective computer readable program codes 331 for respectively implementing various steps in the above method. The computer readable program code 331 may be read from or written to one or more computer program products. These computer program products comprise a program code carrier such as a hard disk, a Compact Disc (CD), a memory card or a floppy disk. Such a computer program product is typically a computer readable storage medium such as described in fig. 4. Fig. 4 shows a schematic structural diagram of a computer-readable storage medium according to an embodiment of the present invention. The computer readable storage medium 400 has stored thereon a computer readable program code 331 for performing the steps of the method according to the invention, readable by a processor 310 of the electronic device 300, which computer readable program code 331, when executed by the electronic device 300, causes the electronic device 300 to perform the steps of the method described above, in particular the computer readable program code 331 stored on the computer readable storage medium may perform the method shown in any of the embodiments described above. The computer readable program code 331 may be compressed in a suitable form.

It should be noted that the above-mentioned embodiments illustrate rather than limit the invention, and that those skilled in the art will be able to design alternative embodiments without departing from the scope of the appended claims. In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The word "comprising" does not exclude the presence of elements or steps not listed in a claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The invention may be implemented by means of hardware comprising several distinct elements, and by means of a suitably programmed computer. In the unit claims enumerating several means, several of these means may be embodied by one and the same item of hardware. The usage of the words first, second and third, etcetera do not indicate any ordering. These words may be interpreted as names.

Claims

1. A fast divider is characterized by comprising an effective bit scanning module and an operation module, wherein the operation module comprises a divisor multiple prejudging unit, a subtraction unit, a remainder generating unit and a quotient generating unit;

2. The fast divider of claim 1, wherein the valid bit scanning module scans dividends and divisors in groups according to integer multiples of i, and the number of valid bits of the dividends and divisors is obtained as an integer multiple of i.

3. A fast divider as defined in claim 1, wherein the subtraction unit comprises k subtractors, each of which implements an iterative operation of block subtraction, where k is determined according to the largest integer value of the i-bit binary.

4. The fast divider of claim 3, wherein i is 4 and k is 5.

5. A fast divider method as claimed in claim 3 or 4, wherein the subtraction unit comprises k memories, each memory for storing the result of an iterative subtraction operation.

6. A method of division, the method comprising:

7. The method of claim 6, wherein scanning and determining the significands of the divisor and dividend and determining the initial remainder and the number of iterative subtractions comprises:

8. The method of claim 6, wherein said performing iterative subtraction of the remainder and the N times the divisor comprises:

9. The method of claim 8, wherein i has a value of 4 and k has a value of 5.

10. The method of claim 8 or 9, wherein said setting k subtractors to implement a block subtraction iterative operation further comprises: