CN100489766C - Device and method for high order root extraction suitable for hardware - Google Patents

Abstract

The invention discloses a device and a method, which is highly efficient in higher power extraction suitable for hardware, and is a technology to practically extract root through method of logical operational circuit or search table or the combination thereof. The technology takes advantages in reducing hardware circuit signal delay and compromising circuit delay and consumption of circuit resource. Operational time predicting and hardware consumption have been achieved. Extraction of random power to different data has been realized. The search table takes far less hardware resource than traditional search table. Therefore, the device has achieved good result in getting fast operational speed while taking small memory.

Description

A kind of device and method that is suitable for the extraction of higher root of hardware

Technical field

The invention belongs to the Digital Electronic Technique field, relate to a kind of hardware unit and method, be specifically related to a kind of device and method of hardware extraction of higher root.

Background technology

Realize on the hardware circuit that extracting operation is pretty troublesome, following certain methods is arranged now more: look-up table, promptly, expend a large amount of storage spaces radicand and table of row as a result, radicand is big more, and used table is also big more, and the speed of tabling look-up is also slow more.The cyclic search method is promptly sought since 0 search, progressively approaches the evolution result.It is not high to do precision like this, and radicand is big more, and cycle index is many more, and elapsed time is many more, can not estimate computing time.The Newton-Raphson algorithm will choose the initial value of iteration, and the Newton iteration of high order nonlinear equation is understood in its concrete grammar utilization, and the same with the cyclic search method, also can not estimate computing time.Above-mentioned several method all has certain difficulty when being generalized to extraction of higher root, it is not high all to exist reusability, expends time in or the shortcoming of storage space.

Summary of the invention

The invention provides hardware circuit device and the computing method of the opening any power that are suitable for hardware, adopted logical operation circuit (data selector) or look-up table or the two, carry out the technology of actual numerical value computing evolution in conjunction with the mode of getting.This technology has the advantage that reduces hardware circuit signal delay, compromised circuit delay and circuit resource consumption.Obtain measurable operation time, reduced the effect of hardware consumption.

Hardware computing circuit device and method among the present invention can realize different pieces of information is carried out the extracting operation of any power.And when using look-up table, the hardware store resource that this look-up table is shared, be far smaller than the shared hardware store resource of look-up table in traditional look-up table, so this device is obtaining and has obtained effect preferably above the very fast arithmetic speed with consuming very little storage space.

A kind of method that is suitable for the extraction of higher root of hardware is characterized in that, this method comprises following several steps:

Step 1: data input initialization: radicand is input among the register Reg of circuit.Register Reg is n * k bit altogether, and k is stored among the counter Counter, and k is the register total length and the ratio of the frequency n value of evolution.Initialization is provided with register x _Forward, s _Try, multiple, x _Lsb, x _NewWith sub be zero.Wherein, register x _ForwardBe used to store the current evolution result who has calculated, register s _TryBe used to store tested merchant's numerical value, register multiple is used for storage examination merchant process and passes through x _ForwardThe tested quotient that calculates, register sub are used to store the input data of subtracter Substrator, register x _LsbBe used to store current evolution data that calculate, register x _NewBe used to store Data Update evolution result later.With n the highest among register Reg bit Reg[(n * k-1): (n * k-n)], promptly the of Reg ((n * k-n) data of position are input to register s to the position of n * k-1) to the _TryIn.

Step 2: pass through x _ForwardObtain multiple, realize with three kinds of methods:

The first, with x _ForwardBe input to data selector SelectorA, be output as multiple, data selector is equivalent to a logical circuit, the calculating of finishing, shown in the following formula:

$\mathrm{multiple}=C_n^{n-1}\·2^{n-1}\·x_{\mathrm{forward}}^{n-1}+...+C_n^{n-i}\·2^{n-i}\·x_{\mathrm{forward}}^{n-i}+..+1$

This logical circuit is to be combined by some multipliers and totalizer, wherein the input value of multiplier Calculated and solidified in the register of circuit.

The second, adopt look-up table, this look-up table LUT1 has been cured among the ROM in advance, x _ForwardAddress wire input as LUT1 is output as multiple.Among the look-up table LUT1, with x _ForwardAs the address, and with different x in the following formula _ForwardThe multiple that calculates as the content of corresponding address.

The 3rd, the mode of employing look-up table and logical circuit computing combination is with x _ForwardAddress wire input as look-up table LUT2 is output as x _ForwardThe numerical value of i power, i is a positive integer, 2≤i≤n, n represent the evolution number of times.LUT2 has been cured in the middle of the ROM in advance, brings the output of LUT2 into formula then $\mathrm{multiple}=C_n^{n-1}\·2^{n-1}\·x_{\mathrm{forward}}^{n-1}+...+C_n^{n-i}\·2^{n-i}\·x_{\mathrm{forward}}^{n-i}+..+1,$ Remaining used addition of calculating and multiplication are realized by general totalizer and multiplier, are drawn the value of multiple.

Step 3: with s _TryWith multiple input data comparator Compare, if s _TryBe greater than or equal to multiple, then Compare output x _LsbBe 1, otherwise be 0.Counter k subtracts one.

Step 4: with x _LsbBe input to register x _NewLowest order in, x _NewRemaining bit is by x _ForwardFill, that is:

x _new＝x _forward<<1+x _lsb

Realize with multiplier and totalizer, with x _LsbIf input data selector SelectorB is x _LsbBe 1, then the numerical value with register multiple is input among the register sub, otherwise the value that register sub is set is 0.

Step 5: with s _TryBe input among the subtracter Subtracter with sub, promptly use s _TryDeduct sub, the result data of subtraction is placed on register S _SubIn the middle of.

Step 6: with Reg[(n among the register Reg * k-1): (n * k-n)] this n Bit data is input to register S _NewLow n bit in, S _NewRemaining bit is by S _SubFill, available multiplier and totalizer realization, that is:

S _new＝S _sub<<n+Reg[(n×k-1):(n×k-n)]

Step 7: if counter k is not equal to 0, then with S _NewIn data input to s _Try, with x _NewInput to x _Forward, and get back to step 2, otherwise the output data result.By the setting of k in the step 1, can calculate the result of different accuracy.

Data comparator Compare adopts the output terminal of conventional data comparer to add a simple adjunct circuit in the described step 3, and this data comparator Compare makes s _TryCan compare with multiple, work as s _TryComparer is output as 1 in the time of more than or equal to multiple, otherwise is output as 0, and the logical expression of adjunct circuit is as follows:

Wherein

Expression Y _(A＜B)Negate.

A kind ofly be applied to described a kind of device that is suitable for the extraction of higher root method of hardware, comprise counter module, it is characterized in that, also comprise: examination is discussed and is calculated module and data update module; The calculation module is discussed in examination, for input s _TryAnd x _Forward, and in cyclic process each time, calculate the one digit number value of n root of radicand; Data update module upgrades the computational data that examination is discussed to be needed in the calculation module, comprises s _TryAnd x _ForwardCounter module judges whether to stop circulation, output result of calculation.

The register s that calculates module is discussed in described examination _TryWith register x _ForwardIn data obtain the register s of multiple, two input data after handling through examination merchant respectively _TryData comparator gained fiducial value x with multiple _LsbWith register s _TryThe signal value of itself; These three signals are input to data update module, obtain upgrading evolution result later after handling through renewal and be stored into register x _NewWith register S _NewIn; Data update module is by the parameter k control that is input in the counter module, and when the k value was non-vanishing, the k value subtracted one, is zero until the k value, update module output evolution result.

The calculation module is discussed in described examination, comprise the combination of a data computing circuit (data selector SelectorA) or LUT1 or data operation circuit and LUT2, a data comparator C ompare, and the input data register x of data selector SelectorA _Forward, x _ForwardProcess data selector SelectorA or LUT1 or data operation circuit and LUT2 obtain tested merchant's signal storage in register multiple after handling; The register s of two input data of data comparator _TryAnd multiple, relatively income value is current evolution data that calculate, and is stored in register x _LsbIn; The data update module branch is clipped to register multiple, x _LsbAnd s _TryGet corresponding signal value.

Described data update module comprises a subtracter Subtracter, the register sub and the s of two input data of data selector SelectorB, refresh circuit A and refresh circuit B and this subtracter _Try, with output data register S _SubS _SubDisplacement obtains upgrading signal later and depositing data register S in middle signal through refresh circuit A _New, x _LsbSignal after middle signal process refresh circuit B displacement obtains upgrading also deposits evolution result register x in _Bew, refresh circuit A and refresh circuit B are by the signal k control of counter module; With x _LsbIf input data selector SelectorB is x _LsbBe 1, then the numerical value with register multiple is input among the register sub, otherwise the value that register sub is set is 0.If signal k is not 0, then with register S _NewIn data input to register s _Try, with register x _NewInput to register x _Forward, discuss the calculation module invokes for examination; Otherwise output result data.

The invention has the advantages that:

(1) discusses in the calculation module method of application circuit logical operation and look-up table combination in the examination of this device.Because the look-up table that is adopted is all identical for different evolution number of times, can obtain the result who well reuses, and has saved storage space; Adopt the logical operation of circuit, make the time measurable, guaranteed the speed of handling, saved operation time.

(2) the present invention has taken into account time and two factors of hardware resource in the hardware evolution calculates, a compromise can got aspect time and the space two, so just under the not really abundant environment of or hardware resource less demanding, fully use, reduced cost computing time.

(3) hardware unit provided by the invention can be realized the extracting operation of arbitrary number of times on circuit, and is issued to degree of precision and speed in the prerequisite that takies less storage space.

Description of drawings

Fig. 1 is a kind of method flow diagram that is suitable for the extraction of higher root of hardware of the present invention;

Fig. 2 is the circuit theory diagrams that a kind of device that is suitable for the extraction of higher root of hardware of the present invention tries data comparator in the quotient module piece;

X in the device data update module of the extraction of higher root that Fig. 3 is suitable for hardware for the present invention is a kind of _NewThe counting circuit schematic diagram;

S in the device data update module of the extraction of higher root that Fig. 4 is suitable for hardware for the present invention is a kind of _NewThe counting circuit schematic diagram;

Fig. 5 is suitable for the device examination of the extraction of higher root of hardware and discusses calculation modular structure figure for the present invention is a kind of;

Fig. 6 is a kind of device data update module structural drawing that is suitable for the extraction of higher root of hardware of the present invention;

Fig. 7 is a kind of each modular structure figure of device that is suitable for the extraction of higher root of hardware of the present invention;

Fig. 8 is suitable for the device extraction of square root examination of the extraction of higher root of hardware and discusses multiple computing realization circuit in the calculation module for the present invention is a kind of;

Fig. 9 opens the cube examination for a kind of device that is suitable for the extraction of higher root of hardware of the present invention and discusses the calculation module, is solidificated in the LUT1 among the ROM;

Figure 10 opens the biquadratic examination for a kind of device that is suitable for the extraction of higher root of hardware of the present invention and discusses the calculation module, is solidificated in the LUT2 among the ROM;

Figure 11 opens the biquadratic examination for a kind of device that is suitable for the extraction of higher root of hardware of the present invention and discusses the calculation module, by the circuit theory diagrams of LUT2 numerical evaluation multiple.

Embodiment

The present invention is described in further detail below in conjunction with drawings and Examples.

A kind of method that is suitable for the extraction of higher root of hardware, this method comprises following several steps, process flow diagram as shown in Figure 1:

(1) data input initialization: radicand is input among the register Reg of circuit.Register Reg is n * k bit altogether, and with k=k _z+ k _pStore among the counter Counter, wherein k represents cycle index, k _zThe expression evolution is the figure place of integral part as a result, k _pThe expression evolution is the figure place of fraction part as a result.If only need draw the whole-number result of evolution, then need with register Reg the 0th of the lowest order of radicand alignd, high-order deficiency then is 0, otherwise with the lowest order of radicand and the n * k of register Reg _pThe position alignment, n represents the number of times of evolution, the n * k of low level _pIndividual bit is filled with 0.The initial value k of Counter is the register total length and the ratio of n value.Initialization is provided with register x _Forward, s _Try, multiple, x _Lsb, x _NewWith sub be zero.Wherein, register x _ForwardBe used to store the current evolution result who has calculated, register s _TryBe used to store tested merchant's numerical value, register multiple is used for storage examination merchant process and passes through x _ForwardThe tested quotient that calculates, register sub are used to store the input data of subtracter Substrator, register x _LsbBe used to store current evolution data that calculate, register x _NewBe used to store Data Update evolution result later.With n the highest among register Reg bit Reg[(n * k-1): (n * k-n)] data be input to register s _TryIn.

(2) pass through x _ForwardObtain multiple, can realize with three kinds of methods:

The first, with x _ForwardBe input to data selector SelectorA, be output as multiple, data selector is equivalent to a logical circuit, the calculating of finishing, shown in the following formula:

$\mathrm{multiple}=C_n^{n-1}\&CenterDot;2^{n-1}\&CenterDot;x_{\mathrm{forward}}^{n-1}+...+C_n^{n-i}\&CenterDot;2^{n-i}\&CenterDot;x_{\mathrm{forward}}^{n-i}+..+1---\left(1\right)$

This logical circuit is to be combined by some multipliers and totalizer, wherein the input value of multiplier

Calculated and solidified in the register of circuit.

The second, adopt look-up table, this look-up table LUT1 has been cured among the ROM in advance, x _ForwardAddress wire input as LUT1 is output as multiple.Among the look-up table LUT1, with x _ForwardAs the address, and with different x in (1) formula _ForwardThe multiple that calculates as the content of corresponding address.

The 3rd, the mode of employing look-up table and logical circuit computing combination, specific practice is, with x _ForwardAddress wire input as look-up table LUT2 is output as x _ForwardThe numerical value of i power (i is a positive integer, 2≤i≤n).Same, LUT2 is cured in the middle of the ROM in advance.Result with LUT2 inputs to computing circuit then, calculates the value of multiple, balance circuit time cost and take storage space.

(3) with s _TryWith multiple input data comparator Compare, if s _TryBe greater than or equal to multiple, then Compare output x _LsbBe 1, otherwise be 0.Counter k subtracts one.

Described data comparator Compare adopts the output terminal of conventional data comparer to add a ball bearing made using and gets final product, general on the market data comparator, and the magnitude relationship of two number A and B has greater than (Y _A〉B), equal (Y _A=B) and less than (Y _A＜B) three kinds of results.This data comparator Compare makes s _TryCan compare with multiple, when and s _TryComparer is output as 1 in the time of more than or equal to multiple, otherwise is output as 0, and the logical expression of adjunct circuit is as follows:

Wherein

Expression Y _(A＜B)Negate.Logical circuitry as shown in Figure 2.

(4) with x _LsbBe input to register x _NewLowest order in, x _NewRemaining bit is by x _ForwardFill, that is:

x _new＝x _forward<<1+x _lsb (3)

Can realize with the multiplier totalizer on the specific implementation, also circuit can be deteriorated to several connecting lines, the bit of input and output correspondence is coupled together.Simultaneously, with x _LsbIf input data selector SelectorB is x _Lsb Be 1, then the numerical value with register multiple is input among the register sub, otherwise the value that register sub is set is 0.Logical circuit as shown in Figure 3.

(5) with s _TryBe input among the subtracter Subtracter with sub, promptly use s _TryDeduct sub, the result data of subtraction is placed on S in the register _SubIn the middle of.

(6) with Reg[(n among the register Reg * k-1): (n * k-n)] this n Bit data is input to register S _NewLow n bit in, S _NewRemaining bit is by S _SubFill, that is:

S _new＝S _sub<<n+Reg[(n×k-1):(n×k-n)](4)

Reg[(n * k-1) wherein: (n * k-n)] expression Reg the (position of n * k-1) is (position of n * k-n) to the.Can realize with the multiplier totalizer on the specific implementation, also circuit can be deteriorated to several connecting lines, the bit of input and output correspondence is coupled together.Logical circuitry as shown in Figure 4.

(7) if counter k is not equal to 0, then with S _NewIn data input to s _Try, with x _NewInput to x _Forward, and get back to step 2, otherwise output data.By k in (1) _pSetting, can calculate the result of different accuracy.

Can realize with the multiplier totalizer on described (4) and step (6) specific implementation, also circuit can be deteriorated to several connecting lines, the bit of input and output correspondence is coupled together.

A kind ofly be applied to described a kind of device that is suitable for the extraction of higher root method of hardware, this device comprises with lower module: the calculation module is discussed in examination, imports x for the user _Lsb, s _TryAnd multiple, for cycle calculations each time goes out the one digit number value of n root of radicand; Data update module for upgrading the computational data that examination is discussed to be needed in the calculation module, comprises s _TryAnd x _ForwardCounter module judges whether to stop circulation, output result of calculation.

The calculation module is discussed in described examination, comprises the combination of a data computing circuit (data selector SelectorA) or LUT1 or data operation circuit and LUT2, a data comparator C ompare, and the input data register x of data selector _Forward, multiple is the output of data selector Selector, the register s of two input data of data comparator _TryAnd multiple, relatively income value is x _Lsb, system chart as shown in Figure 5.

Described data update module comprises a subtracter Subtracter, and the register sub and the s of two input data of this subtracter _Try, with output data register S _SubS _SubMiddle signal obtains upgrading signal later and depositing data register S in through refresh circuit A displacement shown in Figure 4 excessively _New, x _LsbSignal after middle signal obtains upgrading through refresh circuit B displacement shown in Figure 3 also deposits evolution result register x in _New, refresh circuit A and refresh circuit B are by the signal k control of counter module; x _LsbObtain signal storage in register sub through data selector SelectorB, system chart as shown in Figure 6.

Described counter module comprises a counter Counter.Its initial value k is a register Reg total length and the ratio of n value, as shown in step (1).

The comprehensive block diagram of total system as shown in Figure 7.

Examination is discussed in the calculation module, passes through x _ForwardObtain multiple, adopt three kinds of different modes to realize.Wherein LUT1 that is adopted and LUT2 will be cured in the middle of the ROM in advance:

To first method, realize examination merchant's process with pure logical circuit, do not need to use ROM, totalizer of using in the logical circuit and multiplier are general totalizer multiplier.

To second method, replace combinational logic circuit fully with LUT1, LUT1 is cured in the middle of the ROM in advance, and the Input Address line is x _Forward, be output as x _ForwardThe multiple that substitution (1) formula is calculated.

To the third method, with the method for LUT2 and combinational logic circuit combination, LUT2 is cured in the middle of the ROM in advance, and the Input Address line is x _Forward, be output as x _ForwardI power (i is the positive integer between 2 to n, and n represents the evolution number of times).The result of output is brought in (1) formula, and remaining used addition of calculating and multiplication are realized by general totalizer and multiplier.Core concept is to replace complicated power logical operation with searching LUT2.

In the data update module, register S _SubExpression calculates after the evolution result of a bit s _TryWith the difference of sub, as follows:

S _sub＝S _try-Sub (5)

After finishing this step, need logical operation by (4) formula, the renewal process of whole tested quotient is just finished fully.Because the radicand of every n bit can calculate an evolution result, so try the data that the renewal of quotient data need replenish n bit of radicand each time.

Same, after calculating a result, needing to upgrade the result, renewal process is as the formula (3).Register in the formula of above-mentioned (3)～(5) may be degenerated to the circuit signal line in side circuit.

Embodiment 1:

This embodiment is with extraction of square root, and promptly n=2 is an example, and discusses the mode that adopts logical circuit (data selector) in the calculation module in examination, and application of the present invention is described

When discussing the specific implementation of calculating data selector in the module, owing to n=2 this moment, then by (1) Shi Kede with examination:

multiple＝4·x _forward+1 (6)

Corresponding logical operation circuit (data selector) mainly is because at this moment as shown in Figure 8, multiple and x _ForwardRelation is simple between the signal, 4x _ForwardBe equivalent to x _ForwardBe moved to the left two.

Secondly the specific implementation method of calculating data comparator in the module is discussed in the narration examination.General on the market data comparator, the magnitude relationship of two number A and B has greater than (Y _A〉B), equal (Y _A=B) and less than (Y _A＜B) three kinds of results, among the present invention used data comparator only need obtain more than or equal to less than two kinds of results, therefore add a ball bearing made using and get final product at the output terminal of conventional data comparer, make s _TryCan compare with multiple, when and s _TryComparer is output as 1 in the time of more than or equal to multiple, otherwise is output as 0, and the logical expression of adjunct circuit is shown in (2).

Secondly, in the middle of data update module, used subtracter Substractor can adopt general subtracter, and S _NewAnd x _NewCounting circuit and the counting circuit of front multiple similar.Respectively as shown in Figure 3 and Figure 4.

At last, the counter in the counter module is general down counter, and initial value is a positive integer k, has determined the precision of calculating.

Embodiment 2:

This embodiment is to open cube, and promptly n=3 is an example, and discusses the mode of calculating employing look-up table LUT in the module in examination, and the application that we are bright is described.

At first, the formation of whole device and extraction of square root have only place's difference, and examination is discussed the specific implementation method of calculating multiple in the module of calculating, this time exactly:

$\mathrm{multiple}=12\&CenterDot;x_{\mathrm{forward}}^2+6\&CenterDot;x_{\mathrm{forward}}+1---\left(7\right)$

Because this moment, this counting circuit more complicated can adopt the method for look-up table to replace actual computing circuit.The look-up table in this time is input as x _Forward, be output as multiple.Whole LUT1 is cured in the middle of the ROM in advance, and Fig. 9 has illustrated x _ForwardWhen being 6 Bit datas, complete look-up table.Use this look-up table and can open the cube computing the data of one 18 bit.

Remainder is identical with the extraction of square root example.

Embodiment 3:

This embodiment is to open biquadratic, and promptly n=4 is an example, and discusses the mode that adopts logical operation circuit and look-up table LUT2 combination in the calculation module in examination, and application of the present invention is described.

Open quadruplicate the time:

$\mathrm{multiple}=32\&CenterDot;x_{\mathrm{forward}}^3+24\&CenterDot;x_{\mathrm{forward}}^2+8\&CenterDot;x_{\mathrm{forward}}+1---\left(8\right)$

The data that be solidificated among the ROM this moment are

Numerical value, the Input Address line of ROM is x _Forward, and output comprises above-mentioned two values.Therefore this moment, data can be cured among two different ROM, but the two has identical address wire, i.e. x _ForwardSignal.Figure 10 has illustrated x _ForwardWhen being 6 bits, corresponding

With

Numerical value, these numerical value constitute complete LUT2, and are solidificated among the ROM.

When importing x by address wire _Forward, from ROM, read

With

Value, the applied logic computing circuit is finished the function of (8) formula, totalizer of wherein using and multiplier are general totalizer multiplier, the structure as shown in figure 11.

Remainder is identical with the extraction of square root example.

Claims (5)

1, a kind of method that is suitable for the extraction of higher root of hardware is characterized in that, this method comprises following several steps:

Step 1: data input initialization: radicand is input among the register Reg of circuit; Register Reg is n * k bit altogether, and k is stored among the counter Counter, and k is the register total length and the ratio of evolution frequency n value; Register x is set during initialization _Forward, s _Try, multiple, x _Lsb, x _NewWith sub be zero; Wherein, register x _ForwardBe used to store the current evolution result who has calculated, register s _TryBe used to store tested merchant's numerical value, register multiple is used for storage examination merchant process and passes through x _ForwardThe tested quotient that calculates, register sub are used to store the input data of subtracter Substrator, register x _LsbBe used to store current evolution data that calculate, register x _NewBe used to store Data Update evolution result later; With n the highest among register Reg bit Reg[(n * k-1): (n * k-n)], promptly the of Reg ((n * k-n) data of position are input to register s to the position of n * k-1) to the _TryIn;

Step 2: pass through x _ForwardObtain multiple;

Specifically realize by following three kinds of methods:

The first, with x _ForwardBe input to data selector SelectorA, be output as multiple, data selector is equivalent to a logical circuit, the calculating of finishing, shown in the following formula:

$\mathrm{multiple}=C_n^{n-1}\&CenterDot;2^{n-1}\&CenterDot;x_{\mathrm{forward}}^{n-1}+...+C_n^{n-i}\&CenterDot;2^{n-i}\&CenterDot;x_{\mathrm{forward}}^{n-i}+...+1$

This logical circuit is to be combined by some multipliers and totalizer, wherein the input value of multiplier

Calculated and solidified in the register of circuit;

The second, adopt look-up table, this look-up table LUT1 has been cured among the ROM in advance, x _ForwardAddress wire input as LUT1 is output as multiple; Among the look-up table LUT1, with x _ForwardAs the address, and with different x in the following formula _ForwardThe multiple that calculates as the content of corresponding address;

The 3rd, the mode of employing look-up table and logical circuit computing combination is with x _ForwardAddress wire input as look-up table LUT2 is output as x _ForwardThe numerical value of i power, i is a positive integer, 2≤i≤n, n represent the evolution number of times; LUT2 has been cured in the middle of the ROM in advance, brings the output of LUT2 into formula then $\mathrm{multiple}=C_n^{n-1}\&CenterDot;2^{n-1}\&CenterDot;x_{\mathrm{forward}}^{n-1}+...+C_n^{n-i}\&CenterDot;2^{n-i}\&CenterDot;x_{\mathrm{forward}}^{n-i}+...+1,$ Remaining used addition of calculating and multiplication are realized by general totalizer and multiplier, are drawn the value of multiple;

Step 3: with s _TryWith multiple input data comparator Compare, if s _TryBe greater than or equal to multiple, then Compare output x _LsbBe 1, otherwise be 0; Counter k subtracts one;

Step 4: with x _LsbBe input to register x _NewLowest order in, x _NewRemaining bit is by x _ForwardFill, that is:

x _new＝x _forward<<1+x _lsb

Realize with multiplier and totalizer during specific implementation, with x _LsbIf input data selector SelectorB is x _LsbBe 1, then the numerical value with register multiple is input among the register sub, otherwise the value that register sub is set is 0;

Step 5: with s _TryBe input among the subtracter Subtracter with sub, promptly use s _TryDeduct sub, the result data of subtraction is placed on register S _SubIn the middle of;

Step 6: with Reg[(n among the register Reg * k-1): (n * k-n)] this n Bit data is input to register S _NewLow n bit in, S _NewRemaining bit is by S _SubFill, available multiplier and totalizer realization, that is:

S _new＝S _sub<<n+Reg[(n×k-1):(n×k-n)]

Step 7: if counter k is not equal to 0, then with S _NewIn data input to s _Try, with x _NewInput to x _Forward, and get back to step 2, otherwise the output data result; By the setting of k in the step 1, can calculate the result of different accuracy.

2, according to the described a kind of method that is suitable for the extraction of higher root of hardware of claim 1, it is characterized in that: data comparator Compare adopts the output terminal of conventional data comparer to add a simple adjunct circuit in the described step 3, and this data comparator Compare makes s _TryCan compare with multiple; Work as s _TryComparer is output as 1 in the time of more than or equal to multiple, otherwise is output as 0, and the logical expression of adjunct circuit is as follows:

Wherein

Expression Y _(A＜B)Negate.

3, a kind of device that is applied to the method for the described a kind of extraction of higher root that is suitable for hardware of claim 1 comprises counter module, it is characterized in that, also comprises: examination is discussed and is calculated module and data update module; The calculation module is discussed in examination, for input s _TryAnd x _Forward, and in cyclic process each time, calculate the one digit number value of n root of radicand; Data update module upgrades the computational data that examination is discussed to be needed in the calculation module, comprises s _TryAnd x _ForwardCounter module judges whether to stop circulation, output result of calculation;

The register s that calculates module is discussed in described examination _TryWith register x _ForwardIn data obtain the register s of multiple, two input data after handling through examination merchant respectively _TryWith multiple process data comparator gained fiducial value x _LsbWith register s _TryThe signal value of itself; These three signals are input to data update module, obtain upgrading evolution result later after handling through renewal and be stored into register x _NewWith register S _NewIn; Data update module is by the parameter k control that is input in the counter module, and when the k value was non-vanishing, the k value subtracted one, is zero until the k value, update module output evolution result.

4, device according to claim 3, it is characterized in that: the calculation module is discussed in described examination, comprise the combination of a data selector switch SelectorA or LUT1 or data operation circuit and LUT2, a data comparator C ompare, and the input data register x of data selector SelectorA _Forward, x _ForwardProcess data selector SelectorA or LUT1 or data operation circuit and LUT2 obtain tested merchant's signal storage in register multiple after handling; The register s of two input data of data comparator _TryAnd multiple, relatively income value is current evolution data that calculate, and is stored in register x _LsbIn; The data update module branch is clipped to register multiple, x _LsbAnd s _TryGet corresponding signal value.

5, device according to claim 3, it is characterized in that: described data update module, comprise a subtracter Subtracter, the register sub and the s of two input data of data selector SelectorB, refresh circuit A and refresh circuit B and this subtracter _Try, with output data register S _SubS _SubDisplacement obtains upgrading signal later and depositing data register S in middle signal through refresh circuit A _New, x _LsbSignal after middle signal process refresh circuit B displacement obtains upgrading also deposits evolution result register x in _New, refresh circuit Λ and refresh circuit B are by the signal k control of counter module; With x _LsbIf input data selector SelectorB is x _LsbBe 1, then the numerical value with register multiple is input among the register sub, otherwise the value that register sub is set is 0; If signal k is non-vanishing, then with register S _NewIn data input to register s _Try, with register x _NewInput to register x _Forward, discuss the calculation module invokes for examination; Otherwise output result data.

Images