TWI442315B - Low-error compensation method for fixed-width modified booth multipliers - Google Patents

Description

Compensation method for fixed Buith multiplier with fixed error width with low error rate

The invention relates to a compensation method with a low error rate fixed width modified Booth multiplier, which is applied to hardware multiplication operations required in various digital signal processing, and can be adjusted according to a formula according to a required number of operation bits. Used in conjunction with.

Digital signal processing applications, such as filter circuits, Fourier transforms, multipliers are the most commonly used arithmetic units; in real-time, often in terms of cost considerations and practical feasibility, they will generally be multiplied. The product output is limited to a fixed bit width, and the remaining bits are directly rounded off to achieve a large amount of hardware cost savings. For this reason, it is common practice to directly eliminate the phase that is clearly discarded. Corresponding partial product operation, however, this may bring a large output error value; although there are many compensation methods to solve the above problems, some of the hardware architectures are more complicated compensation circuits, not only computationally time-consuming. And the average error of the common final output product value is still relatively large; therefore, the lack of a simple compensation circuit can significantly reduce the product average error value of the fixed width multiplication.

Furthermore, the implementation of the hardware multiplier is divided into many types, such as the common conventional array and Booth coding methods; as shown in FIG. 2A, the improved Booth code table with a base of 4, wherein y _j is the multiplicative value of the jth bit, pp _i is the i-th multiplicative partial product, and X is the multiplier. According to the corresponding conversion and the final summation of this table, the final product can be obtained. The last product bit p _i can be divided into two parts, a main part (Mary Part; MP) and a sub part (Minor Part; LP). According to the above, only the main part is retained, and the auxiliary part is directly discarded, wherein the above The vice department can be divided into LP _major and LP _minor in "row" as shown in Figure 2C, where LP _major is included. , , , With n ₃ , the number of rows of LP _major is variable. At present, most of the compensation methods are based on LP _major , which only selects one vertical line number. Further, various error compensation methods are proposed, but LP _{minor is} generally completed. Neglected, although this method can save a lot of circuit, it is obviously a serious error for the operation of a large number of bits.

It can be seen that there are still many shortcomings in the above-mentioned conventional methods, which is not a good design and therefore needs to be improved.

In view of the shortcomings derived from the above-mentioned conventional systems and methods, the inventor of the present invention has improved and innovated, and after years of painstaking research, finally succeeded in research and development of this piece of simple and low error rate fixed width improved Booth. The compensation method of the multiplier.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a multiplier compensation method that achieves less error at a fixed bit output width, balancing the reduction in hardware cost and achieving lower output errors.

A method for compensating a fixed-width modified Booth multiplier with a low error rate for achieving the above object, comprising an encoding module using a modified Booth multiplication coding table having a base of 4 (Radix-4). After the input multiplier (X) and the multiplicand (Y) are encoded, the product result (P) is calculated by the processing module, and the obtained product result (P) can be divided into a main part (MP) and a sub-part (LP). ), wherein the secondary part (LP) uses a primary secondary selection module, and divides the LP into a primary sub-part (LP _major ) and a secondary deputy (LP _minor ), and in order to further reduce the error, the pair is successively calculated. The best part of the part (LP) is the vertical line value (K), which is based on the multiplier or the minimum of the multiplicand. After using a logarithmic formula to determine the number of rows of LP _major , The LP _minor is temporarily omitted, and P is MP+LP _major ; in order to reduce the error, the expected value (E) is estimated by the previously ignored LP _minor , and the final P is rewritten into MP+LP _major + E. In addition, in order to reduce the hardware cost, another embodiment is also provided, in which the K value is fixedly set to 1, and the expected value of LP _minor is also successively estimated to further provide lower hardware cost, but the accuracy requirement is relatively low. When used.

Referring to FIG. 1 , an architecture diagram of a fixed-width modified Booth multiplier with a low error rate according to the present invention includes: an encoding module 11 that utilizes a modified Buss multiplication table of Radix-4. After being multiplied (Y), the result is output to the processing module 12; a processing module 12, after multiplying the multiplier (X) and the encoded multiplicand (Y), the result is Product (P), which can be divided into main part (MP) and sub-part (LP); a main deputy selection module 13, which divides the sub-part (LP) into main sub-parts (LP _major ) and times After the sub-part (LP _minor ), the optimum partial product vertical line value (K) of the sub-portion (LP) is calculated, which is based on the multiplier bit number (m) or the minimum number of multiplicand bits (n). The value is determined by a one-to-one formula to determine the number of rows of its LP _major ; the primary sub-estimation module 14 estimates the expected value (E[ LP _minor ]) of the remaining LP _minor of the primary secondary selection module 13 And rewrite the last product (P) into .

Please refer to FIG. 2 ^to FIG. 4 , which is a compensation method for a fixed width and improved Booth multiplication with low error rate according to the present invention: Where X is a multiplier, is m number of bits and is represented by 2's complement; Y is a multiplicand, is n number of bits and is represented by 2's complement; Step 1: Y coded mode The group is encoded by the modified Buss multiplication table of Radix-4 (see Figure 2A) and output to the processing module; therefore, Y can be rewritten as:

Where e _j (Bus coefficient) = -2y _2j+1 + y _2j + y _2j-1 ;

Step 2: The product (P) of the X and Y coded modules for encoding conversion and processing module summation can be divided into a main part (MP) and a sub-part (LP); (see Figure 2B)

w =min{ m , n };

Step 3: Using the main deputy selection module, divide the sub-part (LP) into the main sub-part (LP _major ) and the secondary deputy (LP _minor ), ie LP=LP _major +LP _minor (see Figure _2C ). As shown), where LP _major is included Further, the number of rows of LP _major is variable; and the optimum partial line vertical value (K) of the sub-portion (LP) is successively calculated, which is determined by a pair-number formula according to the minimum value of the X or Y-bit number. After the number of LP _major lines, the remaining LP _minors need to be sent to the next unit for processing. The K value calculation method and basis are as follows: Perform a simulation for the multiplication of four commonly used bit widths (as shown in the figure). The second D), where the hit rate or the coincidence rate is defined as:

The post-truncation value here means that the sub-product is truncated but the main product is retained after all the parts have been calculated; in addition, the horizontal axis is expressed as the number of partial vertical lines remaining in the sub-part, where A value of 1 indicates that all the sub-sections are completely truncated, a value of 2 indicates that only one line is left (from left to right), and other values are deduced by analogy. Note that since the 32×32 multiplication calculation is too large and time consuming, we only use 1000. The group random number is the test sample; from the simulation results, it can be observed that the coincidence rate is more than 70%. For the multiplication of four different bit widths, the number of vertical lines (K) of the partial product to be retained is different, but Both meet the following formula:

Where K is called the best partial vertical line value of the main sub-portion (from left to right), and w is the smallest bit between the multiplier (X) bit number and the multiplicand (Y) bit number. Yuan, The table takes the smallest integer greater than or equal to x; taking the multiplication of 12×12 bits as an example, w is 12, so K is 3, and the corresponding coincidence rate is about 82%; in fact, this result shows Although the LP _minor table is the least possible partial product of the carry, ignoring too many vertical lines in this portion will cause excessive errors. Figure 2E is a calculus diagram of an 8×8 Booth multiplier with the best K value (K=2). The partial vertical line number included in LP _minor will be temporarily excluded and sent to the next module. Make an estimate.

Step 4: The secondary sub-section (LP _minor ) obtained in step 3 is estimated by the secondary sub-estimation module, and the expected product (E[ LP _minor ]) is estimated, and the last product (P) is rewritten into .

Note that the above steps 3 and 4 can be calculated before the final hardware design, and then the results are integrated into the actual circuit design, which becomes part of the hardware, so it does not need to be implemented in the completed circuit to save Considerable hardware costs.

First embodiment:

After getting the best partial product vertical row value (K), although LP _major is obtained, in order to further reduce the average error of the multiplier, that is, to increase the coincidence rate, we obviously cannot complete the exclusion of LP _minor in the last product (P). The carry effect generated at the time, but can not completely retain it, adding unnecessary hardware cost, so the present invention proposes a compromise error compensation method, also known as Type-I multiplier, this embodiment needs to estimate LP _minor The Expect Value is used as the error compensation and is sent to the main part and the partial product to which the LP _major belongs. The expected value is calculated as shown in the following equation:

E [ LP _minor ]= a ₀ 2 ^{- w -1} + a ₁ 2 ^{- w -2} +...+ a _K-1 2 ^{- w - K}

among them In addition, we can also add or subtract 1 from the above formula to fine-tune, so that the overall error compensation effect can be improved, and the final multiplication product can be rewritten as:

The simulation is carried out according to the multiplication of the above four commonly used bit widths. The result is shown in Fig. 3A. After using this compensation method, the coincidence rate can be improved by about 10% ^to 21%. FIG. 3B is an architectural diagram of the 8×8 Type-I fixed-width Booth multiplier in this embodiment; FIG. 3C is a detailed circuit diagram used in the module of FIG.

Second embodiment:

To further reduce the hardware cost, this embodiment may be used, which is also called a Type-II multiplier hardware architecture. The compensation method used in this architecture is substantially the same as the Type-I described above, and the difference is only in step 3. The best partial product vertical line number (K) value is fixed to 1, and the last product LP _major (K=1)+E[LP _minor ]. The advantage of this method is that the circuit is more compact than Type-I, but its coincidence rate is much worse than Type-I, that is, the overall average error is reduced. Figure 4 is a block diagram of an 8 x 8 Type-I fixed width Booth multiplier in this embodiment.

data analysis:

The error comparison of the three different bit widths is summarized in the following Tables 1 ^to 3, in which all the data in the table are post-truncation fixed-width modified Booth multipliers (common techniques) as a standard for comparison, And the data in all the tables are enlarged to 2 ⁿ times, and n is the number of multiplicative bits. In addition, the truncation method I (Truncation Method I) is only a partial product of the number of vertical lines belonging to the main part, and the partial product of the number of vertical lines of other sub-parts is negligible, and the Truncation Method II is reserved. The main part is partially redundant, and only the first line of the sub-partial product is retained, and the remaining sub-partial product is discarded. In addition, the Average Error is defined as the "post-cutting fixed width modified Buss product value" minus Go to the sum of the error values of the "sample measurements" and divide by the total number of samples. All the error measurement values can be observed from Table 1. The Type-I and Type-II multiplication architectures proposed by the present invention are excellent, especially the Type-I has an coincidence rate of 88% in the output value, and both positive and negative errors are in Between ±1, this makes the overall average error much lower than other architectures; in addition, since the simulation of large bit numbers is very time consuming, 16×16 and 32×32 bits fixed width multiplication, we only use 10 ^Six random test samples were simulated, and the results are shown in Table 2 and Table 3. Similarly, the performance of Type-I and Type-II of the present invention is still superior to other existing architectures.

In order to observe the hardware performance of the proposed architecture, we use TSMC's 0.18μm CMOS process technology to synthesize according to the above-mentioned architecture. The hardware cost and execution speed are shown in Tables 4 ^to 6. thus our results clearly observed hardware costs than Type-I reference [6] from about 3% ^to 11% higher than the reference, and [4] - [5] and [7] height of about 15 ^~ 11% %, but the coincidence rate is higher than about 24% of them. In addition, the hardware cost of Type-II is slightly different from other architectures, but the coincidence rate is relatively high, that is, it has a lower average error value. In addition, the execution speed is observed, and the gap between all architectures is not Big.

Based on the above data performance, the two types of architectures we propose are better than the existing ones. If a lower average error value is required, the Type-I architecture can be used; if lower cost or lower power consumption is required Time, but does not require a lower average error value, optional Type-II architecture.

The invention provides a compensation method with a low error rate fixed width modified Booth multiplier, which has the following advantages when compared with other conventional techniques:

The present invention provides two embodiments for selecting one of the multipliers for use based on low error rate or low hardware cost requirements.

The detailed description of the preferred embodiments of the present invention is intended to be limited to the scope of the invention, and is not intended to limit the scope of the invention. The patent scope of this case.

In summary, this case is not only innovative in terms of technical thinking, but also able to enhance the above-mentioned multiple functions compared with conventional circuits. It should fully comply with the statutory invention patent requirements of novelty and progressiveness, and apply in accordance with the law. You are requested to approve this document. Invention patent application, in order to invent invention, to the sense of virtue.

11‧‧‧Code Module

12‧‧‧Processing module

13‧‧‧Main Deputy Selection Module

14‧‧‧Sub-Deputy Estimation Module

1 is a structural diagram of a modified Buss multiplier with a low error rate fixed width; FIG. 2A is a "compensation method for a fixed width modified Buith multiplication with a low error rate" used in FIG. Bottom-improved Booth multiplication table; FIG. 2B is a partial product calculus diagram of 8×8 Booth multiplication of a method for compensating a fixed-width modified Booth multiplication with low error rate; FIG. "A kind of compensation scheme for 8×8 Buss multiplication with low error rate fixed width modified Booth multiplication" with LP _major and LP _minor ; Figure 2D is a fixed error width with low error rate. Simulation of the coincidence rate value of the different partial line numbers of the modified method of the modified Booth multiplication method; Fig. 2E is the best vertical application of the "compensation method of the improved double-error rate fixed-width modified Booth multiplication method" The partial product calculus of 8×8 Buss multiplication of the number of rows; Figure 3A is a comparison graph of the coincidence rate under different vertical rows; Figure 3B is a modified Buss multiplication with a fixed error width with low error rate. The method of compensation FIG. 3C is a detailed circuit diagram of each module in the first embodiment of the present invention, a method for compensating a fixed-width modified Booth multiplication with low error rate; FIG. 4 is a schematic diagram of the present invention. A second embodiment architecture diagram of a method for compensating for an error rate fixed width modified Booth multiplication.

11. . . Coding module

12. . . Processing module

13. . . Main auxiliary selection module

14. . . Secondary deputy estimation module

Claims (3)

A compensation method with a low error rate fixed width modified Booth multiplier, wherein the operation method comprises: Step 1: The multiplicand (Y) is coded and multiplied by a modified Booth multiplication table using a base of 4 ( X) is a multiplication operation in which the multiplicand (Y) is rewritten as: ; e _j (Bus coefficient) = -2y _{2j + 1} + y _2j + y _2j-1 ; Step 2: The multiplicand (Y) and multiplier (X) are encoded and converted by the coding module and processed by the module. The total calculated product (P) can be divided into a main part (MP) and a sub-part (LP), and the product (P): The main part (MP) and the sub-part (LP): , w =min{m,n}, w is the minimum number of bits between the number of multipliers (X) and the number of multiplicands (Y); Step 3: Divide the secondary (LP) into primary The LPmajor and the LPminor, LP=LPmajor+LPminor; successively calculate the optimum partial vertical line value (K) of the sub-part (LP), which is based on the multiplier (X) or The minimum value of the multiplicand (Y) bit, after determining the number of LPmajor lines by the one-to-one formula, the remaining LPminor is sent to step four for processing; step four: the secondary sub-part of the third step ( LPminor), estimate its expected value (E[LPminor]), and rewrite the last product (P) to P=X×Y MP+LPmajor+E[LPminor]. A compensation method for a fixed-width modified Booth multiplier with a low error rate, as described in claim 1, wherein the expected value of the step 4 ([LPminor]): A method for compensating a Buick multiplier with a low error rate and a fixed width as described in claim 1, wherein the logarithmic formula of the step 3 is K = Log ₂ w /2 Where w is the minimum number of bits between the number of multipliers (X) and the number of multiplicands (Y).