TW202115560A - Multiplier and method for floating-point arithmetic, integrated circuit chip, and computing device - Google Patents

Abstract

The present invention relates to a multiplier and a method for floating-point arithmetic, an integrated circuit chip, and a computing device. The computing device can be included in a combination processing device. The combination processing device may also include a universal interconnection interface and other processing device(s). The computing device interacts with the other processing device(s) to together accomplish an arithmetic operation prescribed by a user. The combination processing device may also include a storage device. The storage device is connected to the computing device and the other processing device(s) and used for data of the computing device and the other processing device(s). Schemes of the present invention can be widely applied to various floating-point data arithmetic operations.

Description

Multiplier, method, integrated circuit chip and computing device for floating-point operation

This disclosure relates to the technical field of floating-point operations, in particular to a method for floating-point operations, multipliers, integrated circuit chips and computing devices.

In current various signal processing algorithms, such as inner product operations between vectors and matrix convolution operations, a large number of multiplication and addition operations are used, and the efficiency of these multiplication and addition operations often depends on the execution speed of the multiplier. Although current multipliers have achieved significant improvements in execution efficiency, there is still room for improvement in processing floating-point data. Therefore, how to obtain a multiplier with high efficiency, low power consumption and low cost to perform the multiplication operation of floating-point data has become a problem that needs to be solved in the prior art.

In order to at least partially solve the technical problems mentioned in the prior art, the solution of the present disclosure provides a multiplier and method for floating-point operations, an integrated circuit chip including the multiplier, and a computing device.

In one aspect, the present disclosure provides a multiplier for performing multiplication operations of floating-point numbers, wherein the multiplier includes: a mantissa processing unit for obtaining the multiplication operation according to the mantissa of the floating-point number After the mantissa, the mantissa processing unit includes a control circuit for multiple times when the bit width of at least one of the two floating-point numbers is greater than the data bit width that can be processed by the mantissa processing unit at one time Call the mantissa processing unit.

In another aspect, the present disclosure provides a method for performing floating-point number multiplication using a multiplier, wherein the mantissa processing unit of the multiplier is used to obtain the mantissa after the multiplication operation according to the mantissa of the floating-point number The mantissa processing unit includes a control circuit configured to call the mantissa multiple times when the bit width of at least one of the two floating-point numbers is greater than the data bit width that can be processed by the mantissa processing unit at one time. Mantissa processing unit.

In yet another aspect, the present disclosure provides an integrated circuit chip including the multiplier described above. In one or more embodiments, the multiplier of the present disclosure can constitute an independent integrated circuit chip or be arranged on an integrated circuit chip or a computing device to realize the operation of floating-point numbers in a variety of different data formats.

By using the multiplier, corresponding operation method, integrated circuit chip and computing device of the present disclosure, it is possible to support operations on multiple floating-point data without providing multiple separate multipliers for different floating-point data. Therefore, the multiplier of the present disclosure is flexible and can be widely used in various floating-point data operations. In addition, when processing input data with a larger bit width, the multiplier of the present disclosure supports loop multiplexing operation, so that there is no need to arrange more processing chips, thereby also reducing the layout area of the integrated circuit.

The technical solution of the present disclosure provides a multiplier, method, integrated circuit chip and computing device for floating-point number arithmetic as a whole. Different from the conventional floating-point arithmetic multiplier, the present disclosure provides a multiplier that supports multiple operation modes, thereby overcoming the defect that the conventional multiplier can only support one type of floating-point arithmetic. In particular, the present disclosure uses multiple operation modes to indicate different floating-point data types, and in the multiplication calculation process of floating-point numbers, various operations of data are performed based on one of the operation modes, including, for example, encoding, compression, and summation. , Normalization and rounding operations to achieve operations associated with one of multiple floating-point data types. As a result, the multiplier of the present disclosure can support operations in multiple modes, further improving the flexibility of floating-point operations and reducing the cost of operations.

The technical solution of the present disclosure and its multiple embodiments will be described in detail below with reference to the accompanying drawings. It should be understood that many specific details will be elaborated on floating-point operations in order to provide a thorough understanding of the various embodiments of the present disclosure. However, those with ordinary knowledge in the art can practice multiple embodiments described in this disclosure without these specific details under the teaching of the disclosure of this disclosure. In other cases, the content disclosed in the present disclosure does not describe well-known methods, processes, and elements in detail, so as to avoid unnecessarily obscuring the embodiments described in the present disclosure. In addition, this description should not be regarded as limiting the scope of the various embodiments of the present disclosure.

Figure 1 is a schematic diagram showing a floating point data format 100 according to an embodiment of the present disclosure. As shown in Figure 1, the floating-point number to which the technical solution of the present disclosure can be applied can include three parts, such as sign (or sign bit 102), exponent (or exponent bit 104), and mantissa (or mantissa bit 106), where For unsigned floating-point numbers, there may be no sign or sign bit. In some embodiments, the floating-point numbers suitable for the multiplier of the present disclosure may include at least half-precision floating-point numbers, single-precision floating-point numbers, brain floating-point numbers, double-precision floating-point numbers, and custom floating-point numbers. One kind. Specifically, in some embodiments, the floating-point number format to which the technical solution of the disclosure can be applied may be a floating-point format that conforms to the IEEE754 standard, such as double-precision floating-point number (float64, abbreviated as "FP64"), single-precision Floating point number (float32, abbreviated "FP32") or half-precision floating point number (float16, abbreviated "FP16"). In other embodiments, the floating-point number format can also be an existing 16-bit brain floating-point number (bfloat16, abbreviated as "BF16"), or a custom floating-point number format, such as an 8-bit brain floating-point number ( bfloat8, abbreviated as "BF8"), unsigned half-precision floating-point number (unsigned float16, abbreviated as "UFP16"), unsigned 16-bit brain floating-point number (unsigned bfloat16, abbreviated as "UBF16"). For ease of understanding, the following Table 1 shows some of the above-mentioned data formats, in which the sign bit width, exponent bit width, and mantissa bit width are only used for illustrative purposes. Table 1 Data type Sign bit width Exponent bit width Mantissa bit width FP16 1 5 10 BF16 1 8 7 FP32 1 8 twenty three BF8 1 5 3 UFP16 0 5 (or 6) 11 (or 10) UBF16 0 8 8

For the various floating-point number formats mentioned above, the multiplier of the present disclosure can at least support the multiplication operation between two floating-point numbers with any of the above-mentioned formats in operation, wherein the two floating-point numbers can have the same or Different floating-point data formats. For example, the multiplication operation between two floating-point numbers can be FP16*FP16, BF16*BF16, FP32*FP32, FP32*BF16, FP16*BF16, FP32*FP16, BF8*BF16, UBF16*UFP16, or UBF16*FP16 Wait for the multiplication operation between two floating-point numbers.

Figure 2 is a schematic structural block diagram of a multiplier 200 according to an embodiment of the present disclosure. As mentioned above, the multiplier of the present disclosure supports the multiplication operation of floating-point numbers in various data formats, and these data formats can be indicated by the operation mode of the present disclosure, so that the multiplier works in one of a variety of operation modes.

As shown in Figure 2, the multiplier of the present disclosure may generally include an exponent processing unit 202 and a mantissa processing unit 204, where the exponent processing unit is used to process the exponent bits of floating-point numbers, and the mantissa processing unit is used to process floating-point numbers. The mantissa of the number. Alternatively or additionally, in some embodiments, when the floating-point number processed by the multiplier has a sign bit, the multiplier may further include a sign processing unit 206, which may be used to process a floating point number including a sign bit. number.

In operation, the multiplier can perform floating-point operations on the received, input, or buffered first floating-point number and second floating-point number according to one of the operating modes, the first floating-point number and the second floating-point number having One of the floating-point data formats discussed earlier. For example, when the multiplier is in the first operation mode, it can support the multiplication of two floating-point numbers FP16*FP16, and when the multiplier is in the second operation mode, it can support two floating-point numbers BF16*BF16. Multiplication operation. Similarly, when the multiplier is in the third operation mode, it can support the multiplication of two floating-point numbers FP32*FP32, and when the multiplier is in the fourth operation mode, it can support two floating-point numbers FP32*BF16 The multiplication operation. Here, the corresponding relationship between the sample operation mode and the floating-point number is shown in Table 2 below. Table 2 Operation mode number Arithmetic floating point number type 1 FP16*FP16 2 BF16*BF16 3 FP32*FP32 4 FP32*BF16

In an embodiment, the above-mentioned table 2 may be stored in a memory of the multiplier, and the multiplier selects one of the operation modes in the table according to the instruction received from the external device, and the external device may be the 10th The external device 1012 shown in the figure. In another embodiment, the input of the operation mode can also be realized automatically via the mode selection unit 308 as shown in FIG. 3. For example, when two FP16 floating-point numbers are input to the multiplier of the present disclosure, the mode selection unit can select the multiplier to work in the first operation mode according to the data format of the two floating-point numbers. For another example, when a FP32 type floating point number and a BF16 type floating point number are input to the multiplier of the present disclosure, the mode selection unit may select the multiplier to work in the fourth operation mode according to the data format of the two floating point numbers in.

It can be seen that the different operation modes of the present disclosure are associated with corresponding floating-point data. In other words, the operation mode of the present disclosure can be used to indicate the data format of the first floating-point number and the data format of the second floating-point number. In another embodiment, the operation mode of the present disclosure can not only indicate the data format of the first floating-point number and the data format of the second floating-point number, but can also be used to indicate the data format after the multiplication operation. The operation mode extended in conjunction with Table 2 is shown in Table 3 below. table 3 Operation mode number Arithmetic floating point number type Output result type 11 FP16*FP16 FP16 12 BF16 13 FP32 twenty one BF16*BF16 FP16 twenty two BF16 twenty three FP32 31 FP32*FP32 FP16 32 BF16 33 FP32 41 FP32*BF16 FP16 42 BF16 43 FP32

Different from the operation mode numbers shown in Table 2, the operation modes in Table 3 are extended by one bit to indicate the data format after floating-point multiplication. For example, when the multiplier works in operation mode 21, it performs floating-point operations on the input BF16*BF16 two floating-point numbers, and outputs the floating-point multiplication in the FP16 data format.

The above operation mode in number form to indicate the floating point data format is only exemplary and not restrictive. According to the teaching of the present disclosure, it is also conceivable to establish an index according to the operation mode to determine the format of the multiplier and the multiplicand. For example, the operation mode includes two indexes. The first index is used to indicate the type of the first floating-point number, and the second index is used to indicate the type of the second floating-point number. For example, the first index in operation mode 13 is "1". "Indicates that the first floating-point number (or multiplicand) is in the first floating-point format, that is, FP16, and the second index "3" indicates that the second floating-point number (or multiplier) is in the second floating-point format, That is FP32. Further, a third index can also be added to the operation mode, which indicates the data format of the output result. For example, for the third index "1" in the operation mode 131, it can indicate that the data format of the output result is the first floating point. The format is FP16. When the number of operation modes increases, the corresponding index or index level can be increased as needed to facilitate the establishment of the relationship between the operation mode and the data format.

In addition, although numerical numbers are exemplified here to refer to the operation mode, in other examples, other symbols or codes can also be used to refer to the operation mode according to application needs, such as letters, symbols, or numbers and their Combination, etc., and through the expression of such letters, numbers, symbols, or their combination to refer to the operation mode and identify the first floating-point number, the second floating-point number, and the data format of the output result. In addition, when these expressions are formed in the form of instructions, the instructions can include three fields or fields. The first field is used to indicate the data format of the first floating-point number, and the second field is used to indicate the data of the second floating-point number. Format, and the third field is used to indicate the data format of the output result. Of course, these fields can also be combined into one field, or new fields can be added to indicate more content related to the floating-point data format. It can be seen that the operation mode of the present disclosure can not only be associated with the input floating-point number data format, but also can be used to normalize the output result to obtain the product result of the desired data format.

FIG. 3 is a block diagram showing a more detailed structure of the multiplier 300 according to an embodiment of the present disclosure. As can be seen from the content shown in Figure 3, it not only includes the exponent processing unit 202, mantissa processing unit 204, and optional symbol processing unit 206 shown in Figure 2, but also shows the internal components that these units can include. As well as the units related to the operations of these units, the exemplary operations of these units will be described in detail below in conjunction with Figure 3.

In order to perform the multiplication operation of the floating-point number, the exponent processing unit may be used to obtain the multiplied exponent according to the aforementioned operation mode, the exponent of the first floating-point number, and the exponent of the second floating-point number. In an embodiment, the exponent processing unit may be implemented by an addition and subtraction circuit. For example, the exponent processing unit here can be used to add the exponent of the first floating-point number, the exponent of the second floating-point number, and the corresponding offset value of the input floating-point data format, and then subtract the output floating-point The offset value of the data format to obtain the exponent after the multiplication of the first floating-point number and the second floating-point number.

Further, the mantissa processing unit of the multiplier can be used to obtain the mantissa after the multiplication operation according to the foregoing operation mode, the first floating-point number, and the second floating-point number. In one embodiment, the mantissa processing unit may include a partial product arithmetic unit 312 and a partial product summation unit 314, wherein the partial product arithmetic unit is used to obtain the mantissa of the first floating-point number and the mantissa of the second floating-point number. Intermediate results. In some embodiments, the intermediate result may be multiple partial products obtained during the multiplication operation of the first floating-point number and the second floating-point number (as shown schematically in Figures 5 and 6) of). The partial product summation unit is configured to perform an addition operation on the intermediate result to obtain an addition result, and use the addition result as the mantissa after the multiplication operation.

In order to obtain intermediate results, in one embodiment, the present disclosure uses a Booth ("Booth") encoding circuit to complement the high and low bits of the mantissa of the second floating-point number (such as serving as a multiplier in floating-point operations) with 0 (where the Complementing the high bit with zero is to convert the mantissa as an unsigned number to a signed number) in order to obtain the intermediate result. It should be understood that, depending on the encoding method, the mantissa of the first floating-point number (such as the multiplicand in floating-point operations) can also be encoded (such as high and low digits filled with 0), or both To obtain multiple partial products. More descriptions about partial products will be described later in conjunction with the drawings.

In another embodiment, the partial product summation unit may include an adder, which is used to add the intermediate result to obtain the sum result. In yet another embodiment, the partial product summation unit includes a Wallace tree and an adder, wherein the Wallace tree is used to add the intermediate results to obtain a second intermediate result, and the adder uses To add the second intermediate result to obtain the added result. In these embodiments, the adder may include at least one of a full adder, a tandem adder, and a forward bit adder.

In an embodiment, the multiplier of the present disclosure further includes a regularization unit 318 and a rounding unit 320. The regularization unit can be used to perform floating-point regularization processing on the mantissa and exponent after the multiplication operation to obtain a regularized exponent result and a regularized mantissa result, and combine the regularized exponent result and the regularized mantissa result As the exponent after the multiplication operation and the mantissa after the multiplication operation. For example, according to the data format indicated by the operation mode, the regularization unit can adjust the bit width of the exponent and the mantissa to meet the requirements of the data format indicated above. In addition, the regularization unit can also make other adjustments to the exponent or mantissa. For example, in some application scenarios, when the value of the mantissa is not 0, the most significant bit of the mantissa bit should be 1; otherwise, you can modify the exponent bit and shift the mantissa bit at the same time to make it a normalized number. form. In another embodiment, the regularization unit may also adjust the exponent after the multiplication operation according to the mantissa after the multiplication operation. For example, when the highest bit of the mantissa after the multiplication operation is 1, the exponent obtained after the multiplication operation can be increased by 1. Correspondingly, the rounding unit may be used to perform a rounding operation on the regularized mantissa result according to a rounding mode, and use the mantissa after the rounding operation is performed as the mantissa after the multiplication operation. According to different application scenarios, the rounding unit may perform rounding operations including rounding down, rounding up, and rounding to the nearest significant number, for example. In some application scenarios, the rounding unit can also round the 1 that is shifted out in the process of shifting the mantissa to the right.

In addition to the exponent processing unit and the mantissa processing unit, the multiplier of the present disclosure may also optionally include a sign processing unit. When the input floating-point number is a floating-point number with a sign bit, the sign processing unit can be used according to the first The sign of the floating-point number and the sign of the second floating-point number obtain the sign after the multiplication operation. For example, in one embodiment, the symbol processing unit may include an XOR logic circuit 322, which is used to perform XOR according to the sign of the first floating-point number and the sign of the second floating-point number. Or operation to obtain the sign after the multiplication operation. In another embodiment, the symbol processing unit can also be implemented by a truth table or logical judgment.

In addition, in order to make the input or received first and second floating-point numbers comply with the prescribed format, in one embodiment, the multiplier of the present disclosure may further include a normalization processing unit 324 for when the first floating-point number When the point or the second floating-point number is a non-normalized non-zero floating-point number, the first floating-point number or the second floating-point number is normalized according to the operation mode to obtain the corresponding exponent And mantissa. For example, when the selected operation mode is the second operation mode shown in Table 2, and the input first and second floating-point numbers are FP16 data, the FP16 data can be normalized by the normalization processing unit It is BF16 type data, so that the multiplier can operate in the second operation mode. In one or more embodiments, the normalization processing unit may also be used to preprocess the mantissa of normalized floating-point numbers with an implicit 1 and non-normalized floating-point numbers without an implicit 1 (for example, Mantissa expansion) to facilitate subsequent mantissa processing unit operations. Based on the above description, it can be understood that the normalization processing unit 324 and the aforementioned regularization unit 318 can also perform the same or similar operations in some embodiments. The difference is that the normalization processing unit 324 is specific to the input. The floating point data of is normalized, and the regularization unit 318 regularizes the mantissa and exponent to be output.

The multiplier of the present disclosure and its various embodiments have been described above with reference to FIG. 3. Based on the above description, those with ordinary knowledge in the art can understand that the solution of the present disclosure obtains the result of the multiplication operation (including the exponent, the mantissa and optional signs) through the execution of the multiplier. According to different application scenarios, for example, when the aforementioned regularization processing and rounding processing are not required, the result obtained by the mantissa processing unit and the exponential processing unit can be regarded as the final operation result. Furthermore, when the aforementioned regularization processing and rounding processing are required, the exponent and mantissa obtained after the regularization processing and rounding processing can be regarded as the final calculation result, or a part of the final calculation result (when considering The final symbol). Furthermore, the solution of the present disclosure uses multiple operation modes to enable the multiplier to support the operation of floating-point numbers of different types or data formats, so that the multiplexing of the multiplier can be realized, thereby saving the overhead of chip design and the calculation cost. In addition, through the multiple call mechanism, the multiplier of the present disclosure also supports the calculation of high-bit-width floating-point numbers. In view of the fact that in the floating-point number multiplication operation, the multiplication operation of the mantissa (also called the mantissa bit or the mantissa part) is very important to the performance of the entire floating-point operation, the following will describe the mantissa operation of the present disclosure with reference to FIG. 4.

FIG. 4 is a schematic block diagram showing the operation 400 of the mantissa processing unit according to an embodiment of the present disclosure. As shown in Figure 4, the mantissa processing operation of the present disclosure may mainly involve two units, namely the partial product operation unit and the partial product summation unit discussed in Figure 3 in combination with the foregoing. From the perspective of operation sequence, the mantissa processing operation can be roughly divided into the first stage and the second stage. In the first stage, the mantissa processing operation will obtain intermediate results, and in the second stage, the mantissa processing operation will obtain the addition The mantissa result output by the converter 408.

In an exemplary specific operation, the first floating-point number and the second floating-point number received by the multiplier may be divided into multiple parts, namely the aforementioned sign (optional), exponent, and mantissa. Optionally, after the normalization process, the mantissa part of the two floating-point numbers will enter the mantissa processing unit (such as the mantissa processing unit in Figure 2 or Figure 3) as input, and specifically enter the partial product Operation unit. As shown in Figure 4, the present disclosure uses Booth coding circuit 402 to fill the high and low bits of the mantissa of the second floating-point number (that is, the multiplier in floating-point operations) with zeros, and performs Booth coding processing, so that in part The intermediate result is obtained in the product generating circuit 404. Of course, the first floating-point number and the second floating-point number here are only for illustrative and not restrictive purposes. Therefore, in some application scenarios, the first floating-point number can be a multiplier and the second floating-point number can be Is the multiplicand. Correspondingly, in some encoding processes, encoding operations can also be performed on floating-point numbers that serve as multiplicands.

In order to better understand the technical solution of the present disclosure, the following briefly introduces Booth coding. Generally, when two binary numbers are multiplied, a large number of intermediate results called partial products will be produced through the multiplication operation, and then these partial products are accumulated to obtain the multiplication of two binary numbers. Final Results. The greater the number of partial products, the greater the area and power consumption of the array multiplier, the slower the execution speed, and the more difficult it is to implement the circuit. The purpose of Booth coding is to effectively reduce the number of summations of partial products, thereby reducing the circuit area. The algorithm is to first encode the input multiplier according to the corresponding rules. In one embodiment, the encoding rules may be, for example, the rules shown in Table 4 below: Table 4 Data to be encoded Coded signal y _2i+1 y _2i y _2i-1 PPi 0 0 0 0 0 0 1 X 0 1 0 X 0 1 1 2X 1 0 0 -2X 1 0 1 -X 1 1 0 -X 1 1 1 -0(=0)

”，則可以獲得下述的部分積：Among them, y _2i+1 , y _2i and y _{2i-1 in} Table 4 can represent the value corresponding to each group of sub-data to be coded (ie, the multiplier), and X can represent the first floating point number (ie, the multiplicand) Mantissa. After Booth coding processing is performed on each group of corresponding data to be coded, the corresponding coded signal PPi (i=0, 1, 2, ..., n) is obtained. As shown schematically in Table 4, the coded signal obtained after Booth coding can include five types, which are -2X, 2X, -X, X, and 0, respectively. Exemplarily, based on the above encoding rules, if the received multiplicand is 8-bit data "

", the following partial product can be obtained:

”，第9位是符號位，即

；1) When the multiplier digits include the continuous three-digit data "001" in the above table, the partial product is X, which can be expressed as "

", the 9th bit is the sign bit, that is

；

0”，即

；2) When the multiplier digits include the continuous three-digit data "011" in the above table, the partial product is 2X, which can be expressed as X shifted by one bit to the left, and "

0", that is

；

”，表示對“

”按位取反再加1，即

；3) When the multiplier digits include the continuous three-digit data "101" in the above table, the partial product is -X, which can be expressed as "

", which means "

"Invert the bit and add 1 again, that is

；

，表示對“

”左移一位後取反再加1，即

+1；4) When the multiplier digits include the continuous three-digit data "100" in the above table, the partial product is -2X, which can be expressed as

, Which means "

"Move to the left by one place, invert it and add 1 again, that is

+1;

。5) When the multiplier digits include the continuous three-digit data "111" or "000" in the above table, the partial product is 0, that is

.

It should be understood that the above description of the process of obtaining partial products in conjunction with Table 4 is only exemplary and not restrictive. Those with ordinary knowledge in the art can change the rules in Table 4 under the teaching of this disclosure. To obtain a partial product different from that shown in Table 4. For example, when there are multiple consecutive specific numbers (such as 3 or more) in the multiplier bits, the partial product obtained can be the complement of the multiplicand, or the above can be performed after adding the partial products. 3) and 4) "plus 1" operation.

According to the above introductory description, it can be understood that by using the Booth coding circuit to encode the mantissa of the second floating-point number, and using the mantissa of the first floating-point number, multiple partial products can be generated from the partial product generation circuit as intermediate results. And the intermediate result is sent to the Wallace Tree ("Wallace Tree") compressor 406 in the partial product summation unit. It should be understood that the use of Booth coding to obtain the partial product here is only a preferred method for obtaining the partial product in the present disclosure, and those with ordinary knowledge in the art can also obtain the partial product in other ways. For example, it can also be obtained through a shift operation, that is, according to whether the bit value of the multiplier is 1 or 0, the shift plus the multiplicand or the plus 0 is selected to obtain the corresponding partial product. Similarly, the use of a Wallace tree compressor to implement the addition operation of partial products is only exemplary and not restrictive. Those with ordinary knowledge in the art can also think of using other types of adders to implement such partial products. Add operation. The adder may be, for example, one or more full adders, half adders, or various combinations of the two.

Regarding the Wallace tree compressor (or Wallace tree for short), it is mainly used to sum the above-mentioned intermediate results (ie, multiple partial products) to reduce the number of accumulation of partial products (ie, compression). Generally, a Wallace tree compressor can adopt a carry-save CAS (carry-save) architecture and a Wallace tree algorithm. The calculation speed of the Wallace tree array is much faster than the traditional carry-save addition.

Specifically, the Wallace tree compressor can calculate the sum of the partial products of each row in parallel. For example, the number of accumulations of N partial products can be reduced from N-1 times to Log ₂ N times, thereby increasing the speed of the multiplier and reducing resources The effective use of it is of great significance. According to different application needs, the Wallace tree compressor can be designed into many types, such as 7-2 Wallace tree, 4-2 Wallace tree and 3-2 Wallace tree. In one or more embodiments, the present disclosure uses a 7-2 Wallace tree as an example for implementing various floating-point operations of the present disclosure, which will be described in detail later in conjunction with FIG. 5 and FIG. 6.

In some embodiments, the Wallace tree compression operation disclosed in the present disclosure may be arranged to have M inputs and N outputs, the number of which may not be less than K, where N is a preset positive integer less than M, and K is A positive integer not less than the maximum bit width of the intermediate result. For example, M can be 7, and N can be 2, which is a 7-2 Wallace tree which will be described in detail below. When the maximum bit width of the intermediate result is 48, K can take a positive integer of 48, which means that the number of Wallace trees can be 48.

In some embodiments, according to the operation mode, one or more groups of the Wallace trees can be selected to add the intermediate results, wherein each group has X Wallace trees, and X is the sum of the intermediate results. Digits. Further, the Wallace trees in each group may have a sequential carry relationship, but there is no carry relationship between each group. In an exemplary connection, the Wallace tree compressor can be connected by carrying, for example, the carry output from the low-level Wallace tree compressor (such as Cin in Figure 6) to the high-level Wallace tree, and the high-level Hua The Carry output (Cout) of the Laishi tree compressor can become a higher-order Wallace tree compressor to receive the carry input from the lower-order Wallace tree compressor. In addition, when one or more Wallace tree compressors are selected from multiple Wallace tree compressors, arbitrary selection can be made. For example, it can be selected in the order of 0, 1, 2 and 3, or 0 , 2, 4, and 6 are connected in the order of numbers, as long as the selected Wallace tree compressor is selected according to the above-mentioned carry relationship.

The following is an illustrative example to introduce the Wallace tree and its operation above. Assuming that the first floating-point number and the second floating-point number are 16-bit data (for example, FP16*FP16), the data width supported by the multiplier is 32 bits (thus supporting two sets of 16-bit parallel multiplication operations), The Wallace tree is a 7-2 Wallace tree compressor with 7 inputs (that is, an example value of M above) and 2 (that is, an example value of N above) output. In this example scenario, 48 Wallace trees (that is, an example value of K above) can be used to perform the multiplication operation of the two sets of data in parallel.

Among the above 48 Wallace trees, the 0th to 23rd Wallace trees (that is, the 24 Wallace trees in the first group of Wallace trees) can complete the partial product addition and operation of the first group of multiplications , And each Wallace tree in the group can be connected by carry in turn. Furthermore, the 24th to 47th Wallace trees (that is, the 24 Wallace trees in the second group of Wallace trees) can complete the partial product addition operation of the second group of multiplications, where each Wallace in the group The scholar trees are connected by carry in turn. In addition, there is no carry relationship between the 23rd Wallace tree in the first group and the 24th Wallace tree in the second group, that is, there is no carry relationship between Wallace trees in different groups.

Returning to Figure 4, after the partial products are added and compressed by the Wallace tree compressor, the compressed partial products are summed by the adder to obtain the result of the mantissa multiplication operation. Regarding the adder, in one or more embodiments of the present disclosure, it may include one of a full adder, a tandem adder, and an advance bit adder for adding and summing the Wallace tree compressor. The obtained partial products of the last two rows are summed to obtain the result of the mantissa multiplication operation.

It can be understood that the mantissa multiplication operation shown in Figure 4, especially the exemplary use of Booth coding and Wallace tree, can effectively obtain the result of the mantissa multiplication operation. Specifically, Booth encoding processing can effectively reduce the number of partial product summations, thereby reducing the circuit area, while the Wallace compression tree can calculate the sum of partial products of each row in parallel, thereby increasing the speed of the multiplier.

The example operation process of the partial product sum 7-2 Wallace tree will be described in detail below in conjunction with Figures 5 and 6. It can be understood that the description here is merely exemplary rather than restrictive, and is only for a better understanding of the present disclosure.

Figure 5 shows the partial product 500 obtained after passing through the partial product generating circuit in the mantissa processing unit described in conjunction with Figures 2 to 4, as shown in the figure between the two dashed lines in four rows of white dots , Where each row of white dots identifies a partial product. In order to facilitate the subsequent implementation of the Wallace tree compressor, the number of bits can be expanded in advance. For example, the black dot in Figure 5 is the highest value of each 9-bit partial product copied. It can be seen that the partial product is expanded and aligned to 16(8+8)bit (that is, the bit width of the multiplicand mantissa is 8bit+ The bit width of the multiplier mantissa is 8bit). In another embodiment, for example, for the partial product of 25*13 binary multiplication, the partial product is expanded to 38 (25+13) bits (ie, the bit width of the multiplicand mantissa is 25 bits + the bit width of the multiplier mantissa is 13 bits ).

Figure 6 is a schematic block diagram 600 showing the operation flow of the Wallace tree compressor according to an embodiment of the present disclosure.

As shown in Figure 6, after performing the multiplication operation on the mantissa of the two floating-point numbers, for example, as described above, the multiplier can be obtained by Booth coding and the multiplicand as shown in Figure 6. Out of the 7 partial products. Due to the use of Booth coding algorithm, the number of partial products generated is reduced. For ease of understanding, in the figure, a dashed frame is used in the partial product part to identify a Wallace tree that includes 7 elements, and the process of compressing it from 7 elements to 2 elements is further shown with arrows. In one embodiment, the compression process (or called the addition process) can be implemented by means of a full adder, that is, three elements are input and two elements are output (ie, a sum "sum" and a carry "carry" to the higher order) . The schematic block diagram of the 7-2 Wallace Tree Compressor is shown on the right side of Figure 6. It can be understood that the Wallace Tree Compressor includes 7 inputs from a column of partial products (as indicated in the dashed box on the left side of Figure 6). Of the seven elements). In operation, the carry input of the Wallace tree in the 0th column is 0, and the carry output Cout of each Wallace tree is used as the carry input Cin of the next Wallace tree.

It can be seen from the left part of Figure 6 that after four compressions, the Wallace tree including 7 elements can be compressed to include 2 elements. As mentioned earlier, this disclosure uses a 7-2 Wallace tree compressor to finally compress the partial product of 7 rows into a partial product with two rows (ie, the second intermediate result of this disclosure), and uses an adder (for example, Advance bit adder) to get the mantissa result.

In order to further illustrate the principle of the present disclosure, the following will exemplarily describe how the multiplier of the present disclosure completes the operation in the first stage under the four operation modes of FP16*FP16, FP16*FP16, FP32*FP32 and FP32*BF16, namely Until the Wallace tree compressor completes the summation of the intermediate results to obtain the second intermediate result:

(1)FP16*FP16

In this operation mode of the multiplier, the mantissa bits of the floating-point number are 10 bits. Considering the non-normalized non-zero numbers under the IEEE754 standard, the mantissa bits can be extended by 1 bit, so that the mantissa bits are 11 bits. In addition, because the mantissa bits are unsigned numbers, when Booth coding algorithm is used, 1 bit of 0 can be extended in the high bit, so the total mantissa bits are 12 bits. When Booth encoding is used as the second floating-point number, that is, the multiplier, and referring to the first floating-point number, the partial product generation circuit can obtain 7 partial products in the high and low parts respectively, and the seventh partial product is 0. , The bit width of each partial product is 24bit. At this time, 48 7-2 Wallace trees can be compressed, and the carry of the 23rd to 24th Wallace trees is 0.

(2)BF16*BF16

In this operation mode of the multiplier, the mantissa of the floating-point number is 7 bits. Considering the non-normalized non-zero number under the IEEE754 standard and the expansion to a signed number, the mantissa can be expanded to 9 bits. When Booth coding is used as the second floating-point number, that is, the multiplier, and referring to the first floating-point number, the partial product generation circuit can obtain 7 effective partial products in the high and low parts respectively, of which the 6th and 7th parts The product is 0, and the bit width of each part is 18bit. Compression is performed by using the 7-2 Wallace trees of the 0th to 17th and the 24th to 41st groups, of which the 23rd to the 24th Wallace The carry of the tree is 0.

(3)FP32*FP32

In this operation mode of the multiplier, the mantissa bits of the floating-point number can be 23 bits. Considering the non-normalized non-zero numbers under the IEEE754 standard and expansion to signed numbers, the mantissa can be expanded to 25 bits. In order to save the area of the multiplication unit, for example, the bit width supported by the multiplier can be designed to be smaller, and the multiplier of the present disclosure can be called twice in this operation mode to complete an operation. For this reason, the multiplication of the mantissa bits each time is 25bit*13bit, that is, the first floating-point number ina is expanded by 1 bit 0 to become a 25-bit signed number, and the 24bit mantissa bits of the second floating-point number inb are divided into high and low parts, 12 bits respectively. Extend 1 bit 0 to get two 13-bit multipliers, which are expressed as the high and low parts of inb_high13 and inb_low13. In the specific operation, the multiplier of the present disclosure is called for the first time to calculate ina*inb_low13, and the multiplier is called for the second time to calculate ina*inb_high13. In each calculation, 7 effective partial products are generated through Booth coding, and the bit width of each partial product is 38 bits, compressed by the 0th to 37th 7-2 Wallace trees.

(4)FP32*BF16

In this operation mode of the multiplier, the mantissa bit of the first floating-point number ina is 23bit, and the mantissa bit of the second floating-point number inb is 7bit. Considering the denormalized non-zero number under the IEEE754 standard and the expansion to a signed number , The mantissa can be expanded to 25bit and 9bit respectively, and the multiplication of 25bit×9bit is performed to obtain 7 effective partial products. The sixth and seventh partial products are 0, and the bit width of each partial product is 34bit. 33 Wallace trees are compressed.

The above describes how the multiplier of the present disclosure completes the first stage of operation in four operation modes through specific examples, in which the Booth coding algorithm and the 7-2 Wallace tree are preferably used. Based on the above description, those with ordinary knowledge in the art can understand that this disclosure uses 7 partial products, so that the 7-2 Wallace tree can be reused in different operation modes.

The case where the multiplier (mantissa processing unit and exponent processing unit) of the present disclosure is called multiple times will be described in more detail below.

According to another aspect of the present disclosure, as shown in FIG. 3, the mantissa processing unit may include a control circuit 316, and the control circuit 316 may be used to set the mantissa bit width of at least one of the two floating-point numbers to be larger than the mantissa. When the processing unit can process the data bit width at one time, the mantissa processing unit is called multiple times. The data bit width that can be processed by the mantissa processing unit at one time refers to two bit widths (for example, the multiplier bit width and the multiplicand bit width) supported by the mantissa processing unit. Therefore, it can be understood that the control circuit is configured to perform according to the bit width of one of the two floating-point numbers and one of the two bit widths supported by the mantissa processing unit, or according to the two floating-point numbers. The bit width of the mantissa of the point and the two bit widths supported by the mantissa processing unit determine that the mantissa processing unit is called multiple times to obtain the mantissa after the multiplication operation. Therefore, this repeated invocation of the mantissa processing unit in the multiplier avoids arranging large-area multiplier components to handle large-bit-width mantissa operations and avoids arranging small-area multiplier components that cannot handle large-bit-width mantissa operations. The applicability is stronger and it is conducive to reducing the wafer area.

According to the first embodiment of the present disclosure, the two floating point numbers include a first floating point number and a second floating point number, the mantissa processing unit supports a first bit width and a second bit width, and the first floating point number The mantissa of the point is used as the first input corresponding to the first bit width, the mantissa of the second floating point number is used as the second input corresponding to the second bit width, and the bit width of the first input is less than Or equal to the first bit width, and the control circuit is configured to call the mantissa processing unit multiple times to obtain the mantissa after the multiplication operation when the bit width of the second input is greater than the second bit width . According to this embodiment, it is known that the bit width of one of the two inputs is fixed to be less than or equal to the bit width supported by the corresponding mantissa processing unit. Therefore, it is only necessary to determine whether the other input is supported by the corresponding mantissa processing unit. The size relationship of the bit width can determine whether to call the mantissa processing unit multiple times.

According to a second embodiment of the present disclosure, the two floating-point numbers include a first floating-point number and a second floating-point number, the mantissa processing unit supports a first bit width and a second bit width, and the first floating point number The mantissa of the point is used as the first input corresponding to the first bit width, the mantissa of the second floating-point number is used as the second input corresponding to the second bit width, and the control circuit is used when the When the bit width of the first input is greater than the first bit width and the bit width of the second input is less than or equal to the second bit width, when the bit width of the second input is greater than the second bit width and When the bit width of the first input is less than or equal to the first bit width or when the bit width of the first input is greater than the first bit width and the bit width of the second input is greater than the second bit When it is wide, the mantissa processing unit is called multiple times to obtain the mantissa after the multiplication operation. According to this embodiment, the relationship between the bit widths of the two inputs and the two bit widths supported by the mantissa processing unit is uncertain. It is necessary to determine the relationship between the two inputs and the bit widths supported by the respective mantissa processing units to determine Whether to call the mantissa processing unit multiple times.

According to this second embodiment, when the mantissa bit width of the first floating-point number is smaller than the mantissa bit width of the second floating-point number and the first bit width is greater than the second bit width, or when the When the mantissa bit width of the first floating-point number is greater than the mantissa bit width of the second floating-point number and the first bit width is less than the second bit width, the control circuit selects the first floating-point number The mantissa of is used as the second input corresponding to the second bit width and the mantissa of the second floating point number is selected as the first input corresponding to the first bit width. It should be understood that when the mantissa of two floating-point numbers is entered irregularly, the mantissa of the two input floating-point numbers can be first inputted according to the strategy of large bit width to large bit width and small bit width to small bit width and the mantissa processing unit The supported two bit widths are matched to avoid multiple calls that can be done to complete the mantissa operation of two floating-point numbers at one time.

Further, when the bit width of the first input is greater than the first bit width and the bit width of the second input is less than or equal to the second bit width, the control circuit according to the first input The bit width and the first bit width determine the number of times the mantissa processing unit is called and the data of the mantissa processing unit is input in each call. When the bit width of the second input is greater than the second bit width and the bit width of the first input is less than or equal to the first bit width, the control circuit is based on the sum of the bit widths of the second input The second bit width determines the number of times the mantissa processing unit is called and the data of the mantissa processing unit is input in each call. When the bit width of the first input is greater than the first bit width and the bit width of the second input is greater than the second bit width, the control circuit is based on the bit width of the first input and the The first bit width and the bit width of the second input and the second bit width determine the number of times the mantissa processing unit is called and the data of the mantissa processing unit is input in each call.

In the present disclosure, the description of the first floating-point number and the second floating-point number is only for distinguishing the two floating-point numbers, where "first" and "second" have no limiting effect. Similarly, the description about the first bit width and the second bit width is only for distinguishing the two maximum processing bit widths supported by the mantissa processing unit, and the description about the first input and the second input is only for distinguishing the mantissa processing unit The two inputs corresponding to the two maximum processing bit widths, so neither "first" nor "second" has a limiting effect.

It is worth noting that the floating-point number of the input multiplier described in the above embodiment is a floating-point number that meets the format required by the operation and applies to the internal and external components of the multiplier, that is, the floating-point number that has undergone preprocessing such as normalization. It should be understood that the floating-point number input to the multiplier can be a normalized or non-normalized floating-point number. Combining the description of the normalization unit above, it can be known that if at least one of the two input floating-point numbers is non-standardized. For a normalized non-zero floating-point number, the at least one floating-point number may be normalized by a normalization unit first to obtain a normalized exponent and mantissa, and then the normalized mantissa is used as the mantissa processing unit. Input to perform the floating-point number multiplication described above. In addition, the Booth coding circuit mentioned in the present disclosure performs signed fixed-point multiplication calculations, so it is necessary to extend the mantissa by 1 bit 0, that is, the mantissa becomes a signed positive number, and then use the extended signed mantissa as the mantissa. The input of the unit performs the floating-point number multiplication described above. Of course, it is also possible to perform other preprocessing on floating-point numbers, and use the mantissa of the pre-processed floating-point number as the input of the mantissa processing unit to perform the above-mentioned floating-point number multiplication operation, for example, in the description of the normalization unit above As mentioned above for the normalization of floating-point numbers in order to apply the operation mode, the first and second embodiments of the present disclosure are also applicable to the above-mentioned operation of floating-point numbers according to the operation mode.

Three examples of the multi-call mantissa processing unit according to the above-mentioned second embodiment of the present disclosure will be described in detail below. In order to understand these three examples more clearly and intuitively, the above-mentioned first input may be a multiplier, for example, the second input may be a multiplicand, and the first bit width may be, for example, the maximum multiplier bit width supported by the mantissa processing unit. The two-bit width may be, for example, the maximum multiplicand bit width supported by the mantissa processing unit.

According to the first example of the multi-call mantissa processing unit of the present disclosure, combined with the floating-point number multiplication operation according to the operation mode described above, the two floating-point numbers input to the multiplier of the present disclosure are denormalized, non-zero floats. Take the number of points as an example, and combine the Booth coding circuit used in the present disclosure to perform signed fixed-point number multiplication. First, the two floating-point numbers are normalized, so the mantissa of the two floating-point numbers is extended by 1 bit. In addition, for application In the Booth coding circuit in the embodiment of the present disclosure, the two mantissas are extended by 1 bit to form a signed number. After these preprocessing, the mantissa of the two floating-point numbers and the input of the mantissa processing unit are matched. Therefore, when the bit width of the multiplier is greater than the maximum multiplier bit width and the bit width of the multiplicand is less than or equal to the maximum multiplicand, the control circuit only normalizes the original mantissa corresponding to the multiplier as the waiting number. The mantissa is truncated, and in order to be applicable to the Booth coding circuit in the embodiment of the present disclosure, the sign bit is extended for each truncated part. In order to enable the mantissa processing unit to process the mantissa to be truncated, the part of the mantissa to be truncated is truncated with a bit width of A-1 in each call, where A represents the maximum bit width of the multiplier supported by the mantissa processing unit. The part with the bit width A-1 of the second interception is supplemented with a bit 0 at the high bit as a symbol to form a multiplier part with a bit width A, and the multiplier part is used as an input of the mantissa processing unit in each call. In addition, the multiplicand (in this embodiment, the multiplicand is a normalized and extended sign bit mantissa) is input to the mantissa processing unit as another input in each call. Therefore, the following formula can be used to determine the number of calls of the mantissa processing unit:

n=ceil((B+1)/(A-1)),

Among them, n represents the number of times the mantissa processing unit is called, B represents the bit width of the unnormalized mantissa without extending the sign bit, B+1 represents the bit width after the mantissa is normalized, and B+1 can also be understood as B+2 -1, that is, the bit width of the multiplier minus the bit width of the sign bit, A represents the bit width of the multiplier part (the maximum bit width of the multiplier supported by the mantissa processing unit), A-1 represents the mantissa to be truncated in each call The bit width of the intercepted part in.

For example, the maximum multiplier bit width supported by the mantissa processing unit is, for example, 8bit, and the maximum multiplicand bit width is, for example, 32bit. The two floating-point numbers input to the multiplier are FP32 and BF16 floating-point numbers, so choose Multiplication is performed in the FP32*BF16 operation mode, and the two floating-point numbers are non-normalized non-zero numbers. Therefore, the mantissa of the two floating-point numbers has a bit width of 23bit and 7bit respectively. Considering the IEEE754 standard, the two mantissas are The bit width can be expanded to 24bit and 8bit. In order to be applicable to the Booth coding circuit in the embodiment of the present disclosure, the two mantissas are extended by 1 bit 0 to become 25-bit and 9-bit signed numbers. Therefore, the control circuit takes the mantissa with a bit width of 9bit as the multiplier corresponding to the maximum multiplier bit width and uses the mantissa with a bit width of 25bit as the multiplicand corresponding to the maximum multiplicand bit width. Since only the bit width of the multiplier (9bit ) Is greater than the maximum multiplier bit width (8bit), and the bit width of the multiplicand (25bit) is less than the maximum multiplicand bit width (32bit), so the original mantissa corresponding to the multiplier is only the normalized mantissa as the mantissa to be intercepted The mantissa inb, the multiplicand is used as the multiplicand ina of the input mantissa processing unit. According to the above formula, ceil((7+1)/(8-1))=2, therefore, it is necessary to call the mantissa processing unit twice, and in each call, intercept 7bit data in inb each time, and call it the last time (The second call), if there is less than 7bit data, all the remaining data will be intercepted and 0 will be added to the front to make up 7bit, and each intercepted 7bit data will be extended by 1 bit 0 (sign bit) to 8bit as the multiplier part inb_m, Therefore, the calculation performed at each call is ina*inb_m, that is, the multiplication operation of the multiplicand with a bit width of 25bit and the multiplier part with a bit width of 8bit, so that the mantissa result obtained by the call can be calculated. It is worth noting that the interception of the mantissa to be truncated can be performed in the order from high to low, or in the order from low to high. It should be noted that this example is also applicable to the above-mentioned first embodiment of the present disclosure.

According to the second example of the multiple-call mantissa processing unit of the present disclosure, in combination with the floating-point number multiplication operation according to the operation mode described above, the two floating-point numbers input to the multiplier of the present disclosure are denormalized non-zero floats. Take the number of points as an example, and combine the Booth coding circuit used in the present disclosure to perform signed fixed-point number multiplication. First, the two floating-point numbers are normalized, so the mantissa of the two floating-point numbers is extended by 1 bit. In addition, for application In the Booth coding circuit in the embodiment of the present disclosure, the two mantissas are extended by 1 bit to form a signed number. After these preprocessing, the mantissa of the two floating-point numbers and the input of the mantissa processing unit are matched. Therefore, when the bit width of the multiplicand is greater than the maximum multiplicand bit width and the bit width of the multiplier is less than or equal to the maximum multiplier bit width, the control circuit only normalizes the original mantissa corresponding to the multiplicand to the mantissa formed As the mantissa to be truncated, and in order to be applicable to the Booth coding circuit in the embodiment of the present disclosure, the sign bit is extended for each truncated part. In order to enable the mantissa processing unit to process the mantissa to be truncated, the part with a bit width of C-1 is truncated from the mantissa in each call, where C represents the maximum bit width of the multiplicand supported by the mantissa processing unit. The truncated part with a bit width of C-1 is supplemented with a bit of 0 at the high bit as a symbol to form a multiplicand part with a bit width of C, which is used as an input of the mantissa processing unit in each call. In addition, the multiplier (in this embodiment, the multiplier is a normalized and extended sign bit mantissa) is input to the mantissa processing unit as another input in each call. Therefore, the following formula can be used to determine the number of calls of the mantissa processing unit:

n=ceil((D+1)/(C-1)),

Among them, n represents the number of times the mantissa processing unit is called, D represents the bit width of the unnormalized mantissa without extending the sign bit, D+1 represents the bit width after the mantissa is normalized, and D+1 can also be understood as D+2 -1, that is, the bit width of the multiplicand minus the bit width of the sign bit, C represents the bit width of the multiplicand part (the maximum bit width of the multiplicand supported by the mantissa processing unit), C-1 represents the bit width of the multiplicand from each call The bit width of the truncated part of the mantissa to be truncated.

For example, the maximum multiplier bit width supported by the mantissa processing unit is, for example, 12bit, and the maximum multiplicand bit width is, for example, 16bit. The two floating-point numbers input to the multiplier are FP32 and BF16 floating-point numbers, so choose Multiplication is performed in the FP32*BF16 operation mode, and the two floating-point numbers are non-normalized non-zero numbers. Therefore, the mantissa of the two floating-point numbers has a bit width of 23bit and 7bit respectively. Considering the IEEE754 standard, the two mantissas are The bit width can be expanded to 24bit and 8bit. In order to be applicable to the Booth coding circuit in the embodiment of the present disclosure, the two mantissas are extended by 1 bit 0 to become 25-bit and 9-bit signed numbers. Therefore, the control circuit takes the mantissa with a bit width of 9 bits as the multiplier corresponding to the maximum multiplier bit width and uses the mantissa with a bit width of 25 bits as the multiplicand corresponding to the maximum multiplicand bit width, because only the bit width of the multiplicand ( 25bit) is greater than the maximum multiplicand bit width (16bit) supported by the mantissa processing unit, and the multiplier bit width (9bit) is less than the maximum multiplier bit width (12bit), so the original mantissa corresponding to the multiplicand is only normalized The resulting mantissa is used as the mantissa to be truncated ina, and the multiplier is used as the multiplier inb of the input mantissa processing unit. According to the above formula, ceil((23+1)/(16-1))=2, therefore, it is necessary to call the mantissa processing unit twice, and in each call, 15bit data is intercepted in ina each time, and the last call (The second call), if the data is less than 15bit, add 0 to the front to make up 15bit, and each intercepted 15bit data is extended by 1 bit 0 (sign bit) to become 16bit as the multiplicand part ina_m, therefore, in each call The calculation performed at this time is ina_m*inb, that is, the multiplication operation of the multiplicand part with a bit width of 16 bits and a multiplier with a bit width of 9 bits, so that the mantissa result obtained by this call can be calculated. It is worth noting that the interception of the mantissa to be truncated can be performed in the order from high to low, or in the order from low to high. It should be noted that this example is also applicable to the above-mentioned first embodiment of the present disclosure.

According to the third example of the multi-call mantissa processing unit of the present disclosure, combined with the floating-point number multiplication operation according to the operation mode described above, the two floating-point numbers input to the multiplier of the present disclosure are denormalized non-zero floats. Take the number of points as an example, and combine the Booth coding circuit used in the present disclosure to perform signed fixed-point number multiplication. First, the two floating-point numbers are normalized, so the mantissa of the two floating-point numbers is extended by 1 bit. In addition, for application In the Booth coding circuit in the embodiment of the present disclosure, the two mantissas are extended by 1 bit to form a signed number. After these preprocessing, the mantissa of the two floating-point numbers and the input of the mantissa processing unit are matched. Therefore, when the bit width of the multiplier is greater than the maximum multiplier bit width and the multiplicand (in this embodiment, the multiplicand is a normalized and extended sign bit mantissa) bit width is greater than the When the maximum bit width of the multiplicand is the mantissa to be truncated by the control circuit, the original mantissa corresponding to the multiplier is only normalized and the mantissa formed by the original mantissa corresponding to the multiplicand is only normalized as the mantissa to be truncated. In the Booth coding circuit in the embodiment of the present disclosure, the sign bit is extended for each intercepted part. In order to enable the mantissa processing unit to process these two mantissas to be truncated, in each call the part of the mantissa to be truncated corresponding to the multiplier is truncated with a bit width of A-1 and the mantissa to be truncated corresponding to the multiplicand is truncated. The part where the bit width of the interception is C-1, where A represents the maximum multiplier bit width supported by the mantissa processing unit, and C represents the maximum multiplicand bit width supported by the mantissa processing unit. The bit width for each interception is A- The part of 1 is supplemented with a bit of 0 at the high bit as a symbol to form a multiplier part with a bit width of A. The multiplier part is used as an input to the mantissa processing unit in each call, and the bit width for each interception is C- The part of 1 is supplemented with a bit of 0 at the high bit as a symbol to form a multiplicand part with a bit width of C. The multiplicand part is used as another input of the mantissa processing unit in each call. Therefore, the following formula can be used to determine the number of calls of the mantissa processing unit:

n=ceil((B+1)/(A-1))* ceil((D+1)/(C-1))

Among them, n represents the number of times the mantissa processing unit is called, B represents the bit width of the unnormalized mantissa without extending the sign bit, B+1 represents the bit width after the mantissa is normalized, and B+1 can also be understood as B+2 -1, that is, the bit width of the multiplier minus the bit width of the sign bit, A represents the bit width of the multiplier part (the maximum multiplier bit width supported by the mantissa processing unit), and A-1 represents the slave and multiplier in each call Corresponding to the bit width of the truncated part of the mantissa to be truncated, D represents the bit width of the unnormalized and unexpanded sign bit mantissa, D+1 represents the bit width after the mantissa is normalized, and D+1 can also be understood as D +2-1, that is, the bit width of the multiplicand minus the bit width of the sign bit, C represents the bit width of the multiplicand part (the maximum bit width of the multiplicand supported by the mantissa processing unit), and C-1 represents each call The bit width of the part to be truncated from the mantissa to be truncated in.

For example, the maximum multiplier bit width supported by the mantissa processing unit is, for example, 8bit, and the maximum multiplicand bit width is, for example, 16bit. The two floating-point numbers input to the multiplier are both FP32-type floating-point numbers, so choose FP32* Multiplication is performed in the FP32 operation mode, and the two floating-point numbers are non-normalized non-zero numbers, so the mantissa width of the two floating-point numbers is 23bit. Considering the IEEE754 standard, the bit width of the two mantissas can be extended to 24bit . In order to be applicable to the Booth coding circuit in the embodiment of the present disclosure, the two mantissas are extended by 1 bit 0 to become a signed number of 25 bits. Therefore, the control circuit selects the mantissa of the two floating-point numbers as the multiplier corresponding to the maximum multiplier bit width and the multiplicand corresponding to the maximum multiplicand bit width (because the mantissa of the two floating-point numbers has the same bit width after expansion , So you can choose one as the multiplier and the other as the multiplicand), because the bit width of the multiplier (25bit) is greater than the maximum multiplier bit width (8bit) and the bit width of the multiplicand (25bit) Is greater than the maximum multiplicand bit width (16bit), so the mantissa formed by normalizing the original mantissa corresponding to the multiplier is used as the mantissa to be truncated inb, and the mantissa formed by normalizing the original mantissa corresponding to the multiplicand is used as the mantissa to be truncated. Truncate the mantissa ina. According to the above formula, ceil((23+1)/(8-1))* ceil((23+1)/(16-1))=8, therefore, the mantissa processing unit needs to be called eight times. At each call, intercept 7bit data in inb each time. At the last call, if there is less than 7bit data, then all the remaining data will be intercepted and the first 0 will be added to make up 7bit, and the 7bit data intercepted each time will be extended by 1 bit 0 The (sign bit) becomes 8bit as the multiplier part inb_m. Since inb is cut into four parts, there can be four multiplier parts inb_m1, inb_m2, inb_m3, and inb_m4. In addition, at each call, 15bit data is intercepted in ina each time. At the last call, if there is less than 15bit data, all the remaining data will be intercepted and 0 to make up 15bit, and the 15bit data intercepted will be extended by 1 bit each time. 0 (sign bit) becomes 16bit as the multiplicand part ina_m. Since ina is truncated into two parts, it can have two multiplicand parts ina_m1 and ina_m2. Therefore, for example, when the mantissa processing unit is called eight times, the following calculations can be performed sequentially: ina_m1*inb_m1, ina_m1*inb_m2, ina_m1*inb_m3, ina_m1*inb_m4, ina_m2*inb_m1, ina_m2*inb_m2, ina_m2*inb_m3, inb_m2*in The following calculations can also be performed in sequence: inb_m1*ina_m1, inb_m1*ina_m2, inb_m2*ina_m1, inb_m2*ina_m2, inb_m3*ina_m1, inb_m3*ina_m2, inb_m4*ina_m1, inb_m4*ina_m2. The calculation for each call is the multiplication of the multiplicand part with a bit width of 16 bits and the multiplier part with a bit width of 8 bits, so that the mantissa result obtained by the call can be calculated. It is worth noting that the interception of the mantissa to be truncated can be performed in the order from high to low, or in the order from low to high.

The above examples are only for illustrative and not restrictive purposes. According to these examples, those with ordinary knowledge in the art can think of calling the floating-point number multiplication performed by the mantissa processing unit that supports any bit width multiple times in other operation modes. Operation.

In view of the above multiple calls to the mantissa processing unit, the mantissa processing unit may further include a shift and add circuit for obtaining the multiplication operation according to the mantissa result obtained by calling the mantissa processing unit each time After the mantissa.

Further, the shift and add circuit includes a shifter, an intermediate memory, and an adder. When the control circuit calls the mantissa processing unit multiple times according to the operation mode, after the first call, the shift The shifter shifts the mantissa result obtained in the first call to obtain the shifted mantissa result and stores the shifted mantissa result in the intermediate memory. Starting from the second call, the shifter will be The mantissa result obtained in this call is shifted to obtain the current mantissa result, and the adder adds the current mantissa result to the result stored in the intermediate memory and stores the added result in the The intermediate memory is updated in the intermediate memory, and the result stored in the intermediate memory after the last call is used as the mantissa after the multiplication operation.

In this embodiment, for example, the truncation of the mantissa to be truncated is performed in the order from high order to low order. Each time the mantissa processing unit is called, the shifter shifts the mantissa result obtained in the current call according to the following formula:

Y=k+j

Among them, Y represents the number of shifts required for the mantissa result obtained in the current call, and k represents the sum of the digits of all data behind the intercepted part used in the current call in the mantissa to be truncated corresponding to the multiplier , J represents the sum of the digits of all data after the intercepted part used in the current call in the mantissa to be intercepted corresponding to the multiplicand. It should be understood that if only the bit width of the multiplier is greater than the maximum multiplicand bit width or only the bit width of the multiplicand is greater than the maximum multiplicand bit width, then only the mantissa to be truncated corresponding to the multiplier or the to be truncated corresponding to the multiplicand is required. Truncate the mantissa for truncation, and the mantissa that does not need to be truncated uses all its data each time it is called, so there is no data behind, so the value of k or j is 0, which shows that the bit width of only the multiplier is greater than the maximum In the case of the multiplier bit width, the above formula for calculating the shift number can be written as: Y=k. For the case where only the bit width of the multiplicand is greater than the maximum multiplicand bit width, the above formula for calculating the shift number can be written as: Y = j.

For example, as mentioned above, in the FP32*BF16 operation mode, when only the bit width of the multiplier is greater than the maximum multiplier bit width, the mantissa processing unit is called twice, and for example, the interception of the mantissa to be truncated is performed according to From high order to low order. Specifically, for example, the multiplier parts in the two calls are inb_m1 and inb_m2 respectively. After the first call, the shifter shifts the result of ina*inb_m1 to the left, because 7bit is intercepted in the first call Therefore, the sum of the digits of all the data after the 7bit data used in this call is k=8-7=1bit. According to the above formula, Y=1, therefore, the number of bits shifted to the left is 1 bit to obtain the result R1 shifted by 1 bit. The adder stores this R1 in the intermediate memory; after the second call (the last call), the shifter will ina*inb_m2 The result of is shifted to the left. Since the last 1 bit of data has been intercepted in the second call, there is no data after the 1bit data used in this call. According to the above formula, Y=0, therefore, The number of bits shifted to the left is 0 bits, that is, it is not shifted, so that the result R2 is obtained. The adder adds this R2 to R1 stored in the intermediate memory, and stores the result of the addition in the intermediate memory. The intermediate memory is updated in the intermediate memory. Since the second call is the last call, the result stored in the intermediate memory after the second call is the mantissa after the multiplication operation. For the above-mentioned situation when only the bit width of the multiplicand is greater than the maximum bit width of the multiplicand, the shift addition circuit can work in the same way.

For example, as mentioned above, in the FP32*FP32 operation mode, when the bit width of the multiplier is greater than the maximum multiplier bit width and the bit width of the multiplicand is greater than the maximum multiplicand bit width , The mantissa processing unit is called eight times, and for example, the truncation of the mantissa to be truncated is performed in order from high to low. Specifically, for example, the multiplier parts in the eight calls are inb_m1, inb_m2, inb_m3, and inb_m4, respectively, and the multiplicand parts are ina_m1, ina_m2, respectively. For example, when the mantissa processing unit is called eight times, the following calculations are sequentially performed: ina_m1*inb_m1, ina_m1*inb_m2, ina_m1*inb_m3, ina_m1*inb_m4, ina_m2*inb_m1, ina_m2*inb_m2, ina_m2*inb_m3, ina_m2*inb_m4. In the first call, the shifter shifts the result of ina_m1*inb_m1 to the left. Since the 7-bit data is intercepted in the mantissa to be truncated corresponding to the multiplier in the first call, the mantissa is to be truncated The sum of the digits of all the data after the 7bit data used in this call is k=24-7=17bit, and 15bit data is truncated in the mantissa to be truncated corresponding to the multiplicand, so the mantissa to be truncated is The sum of the digits of all data after the 15bit data used in this call is j=24-15=9bit. According to the above formula, Y=17+9=26. Therefore, the number of bits shifted to the left It is 26 bits to obtain the result S1 shifted by 26 bits. The adder stores the S1 in the intermediate memory; after the second call, the shifter shifts the result of ina_m1*inb_m2 to the left Shift, because in the second call, the next 7-bit data is intercepted in the mantissa to be truncated corresponding to the multiplier, so in the mantissa to be truncated, the number of bits in all the data after the 7-bit data used in the call is The sum is k=24-7-7=10bit, and in the mantissa to be truncated corresponding to the multiplicand, the same 7-bit data as in the previous call is intercepted (using the same 7-bit data as the previous call), so the The sum of the digits of all data after the 7bit data used in this call in the truncation mantissa is still j=24-15=9bit. According to the above formula, Y=10+9=19, therefore, shift to the left The number of bits of is 19 bits, so that the result S2 shifted by 19 bits is obtained. The adder adds this S2 to S1 stored in the intermediate memory, and stores the result of the addition in the intermediate memory To update the intermediate memory; repeat the call to the mantissa processing unit until the fourth call. In the fourth call, the shifter shifts the result of ina_m1*inb_m4 to the left, because in the fourth call The last 3bit data in the mantissa to be truncated corresponding to the multiplier is intercepted, so there is no data in the mantissa to be truncated after the 3bit data used in this call, so k=0, and the data in the mantissa corresponding to the multiplicand In the truncation mantissa, the same 7-bit data as the last call is intercepted. Therefore, the sum of the digits of all data after the 7-bit data used in the call in the mantissa to be truncated is still j=24-15=9bit, according to The above formula shows that Y=0+9=9, therefore, the number of bits shifted to the left is 9 bits, so as to obtain the result S4 shifted by 9 bits, and the adder stores this S4 and the intermediate memory in the intermediate memory. Add the results in and store the added results in the intermediate memory to update the intermediate memory; because in the fifth to eighth calls, the to-be intercepted corresponding to the multiplicand is intercepted The last 9bit data in the mantissa, and there is no more data after the 9bit data, so in the fifth to the eighth call, j=0, in the fifth call, so The shifter shifts the result of ina_m2*inb_m1 to the left. Because in the fifth call, the same 7bit data as in the first call is intercepted in the mantissa to be truncated corresponding to the multiplier, so k=24- 7=17bit. According to the above formula, Y=17+0=17. Therefore, the number of bits shifted to the left is 17 bits to obtain the result S5 shifted by 17 bits. The adder divides the result S5 with The result stored in the intermediate memory is added, and the result of the addition is stored in the intermediate memory to update the intermediate memory; in this way, the mantissa processing unit is called repeatedly until the eighth call, and at the eighth call , The shifter shifts the result of ina_m2*inb_m4 to the left. Since the last 3bit data in the mantissa to be truncated corresponding to the multiplier is intercepted in the eighth call, in the mantissa to be truncated, After calling the used 3bit data, there is no data, so k=0. According to the above formula, Y=0+0=0. Therefore, the number of bits shifted to the left is 0 bits, that is, no shift is obtained. The result of shifting S8, the adder adds S8 to the result stored in the intermediate memory, and stores the result of the addition in the intermediate memory to update the intermediate memory; The eight calls are the last call, so the result stored in the intermediate memory after the eighth call is the mantissa after the multiplication operation.

On the other hand, in order to further reduce the area of the multiplier, the exponent processing unit includes a second control circuit (not shown in the figure). The exponent bit width of and one of the two bit widths supported by the exponent processing unit or multiple times are determined according to the exponent bit width of the two floating-point numbers and the two bit widths supported by the exponent processing unit The exponent processing unit is called to obtain the exponent after the multiplication operation.

According to a third embodiment of the present disclosure, the two floating point numbers include a first floating point number and a second floating point number, the exponent processing unit supports a third bit width and a fourth bit width, and the first floating point number The exponent of the number of points is used as the third input corresponding to the third bit width, the exponent of the second floating point number is used as the fourth input corresponding to the fourth bit width, and the bit width of the third input is less than Or equal to the third bit width, and the second control circuit is configured to call the exponent processing unit multiple times to obtain the multiplication operation when the fourth input has a bit width greater than the fourth bit width. The index. According to this embodiment, it is known that the bit width of one of the two inputs is fixed to be less than or equal to the bit width supported by the corresponding exponential processing unit. Therefore, it is only necessary to determine that the other input is supported by the corresponding exponential processing unit. The size relationship of the bit width can determine whether to call the exponential processing unit multiple times.

According to the fourth embodiment of the present disclosure, the two floating-point numbers include a first floating-point number and a second floating-point number, the exponent processing unit supports a third bit width and a fourth bit width, and the first floating-point number The exponent of the number of points is used as the third input corresponding to the third bit width, the exponent of the second floating point number is used as the fourth input corresponding to the fourth bit width, and the second control circuit is used for When the bit width of the third input is greater than the third bit width and the bit width of the fourth input is less than or equal to the fourth bit width, when the bit width of the fourth input is greater than the fourth bit width Wide and the bit width of the third input is less than or equal to the third bit width or when the bit width of the third input is greater than the third bit width and the bit width of the fourth input is greater than the first When it is four bits wide, the exponent processing unit is called multiple times to obtain the exponent after the multiplication operation. According to this embodiment, the relationship between the bit widths of the two inputs and the two bit widths supported by the exponential processing unit is uncertain. It is necessary to determine the relationship between the two inputs and the bit widths supported by their respective exponential processing units to determine Whether to call the index processing unit multiple times.

According to this fourth embodiment, when the exponent bit width of the first floating-point number is smaller than the exponent bit width of the second floating-point number and the third bit width is greater than the fourth bit width, or when the When the exponent bit width of the first floating-point number is greater than the exponent bit width of the second floating-point number and the third bit width is less than the fourth bit width, the second control circuit selects the first floating The exponent of the number of points is used as the fourth input corresponding to the fourth bit width and the exponent of the second floating point number is selected as the third input corresponding to the third bit width. It should be understood that when the exponents of two floating-point numbers are entered irregularly, the exponents of the two input floating-point numbers can be first inputted according to the strategy of large bit width to large bit width and small bit width to small bit width and the exponent processing unit The two supported bit widths are matched to avoid the exponential operation of two floating-point numbers that can be processed at one time, but multiple calls are made.

Further, when the bit width of the third input is greater than the third bit width and the bit width of the fourth input is less than or equal to the fourth bit width, when the bit width of the fourth input is greater than the When the fourth bit width and the bit width of the third input is less than or equal to the third bit width or when the bit width of the third input is greater than the third bit width and the bit width of the fourth input is larger In the fourth bit width, the second control circuit is used when the bit width of the third input is less than or equal to the bit width of the fourth input and the third bit width is less than or equal to the first bit width. When the width is four bits, the number of invocations of the index processing unit and the data of the index processing unit are input in each invocation according to the bit width of the fourth input and the third bit width. It is worth noting that, in the above three cases, the number of calls to the index processing unit and the data input to the index processing unit in each call are based on the larger of the third input and the fourth input bit width and the first one. The smaller of the three-digit width and the fourth-digit width is determined. Of course, when the bit width of the third input and the fourth input are the same or the third bit width and the fourth bit width are the same, you can choose one of the two with the same bit width.

In this embodiment, the description of the first floating-point number and the second floating-point number is only for distinguishing between the two floating-point numbers, where "third" and "fourth" do not have a limiting effect. Similarly, the description of the third input and the fourth input is only to distinguish the two inputs of the exponent processing unit, and the description of the third and fourth bit width is only to distinguish between the exponential processing unit supported and the exponential processing unit. The two inputs of the index processing unit correspond to the two maximum processing bit widths, so neither "third" nor "fourth" has a limiting effect.

It is worth noting that the floating-point number of the input multiplier described in the above embodiment is a floating-point number that meets the format required by the operation and applies to the internal and external components of the multiplier, that is, the floating-point number that has undergone preprocessing such as normalization. It should be understood that the floating-point number input to the multiplier can be a normalized or non-normalized floating-point number. Combining the description of the normalization unit above, it can be known that if at least one of the two input floating-point numbers is non-standardized. For a normalized non-zero floating-point number, the at least one floating-point number may be normalized by a normalization unit first to obtain a normalized exponent and mantissa, and then the normalized exponent is used as the exponent processing unit. Input to perform the floating-point number multiplication described above. Of course, you can also perform other preprocessing on floating-point numbers, and use the exponent of the pre-processed floating-point number as the input of the exponent processing unit to perform the above-mentioned floating-point number multiplication operation, for example, in the description of the normalization unit above As mentioned above for the normalization of floating-point numbers in order to apply the operation mode, the third and fourth embodiments of the present disclosure are also applicable to the above-mentioned operation of floating-point numbers according to the operation mode.

An example of calling the index processing unit multiple times will be described in detail below. In order to understand this example more clearly and intuitively, the above-mentioned third input may be an addend, for example, the fourth input may be an addend, and the third bit width may be, for example, the maximum addend bit width supported by the exponent processing unit. The width may be, for example, the maximum addendum width supported by the exponential processing unit.

According to the example of multiple calls to the exponential processing unit of the present disclosure, combined with the floating-point number multiplication operation according to the operation mode described above, the two floating-point numbers input to the multiplier of the present disclosure are denormalized non-zero floating-point numbers As an example, first normalize two floating-point numbers, so the mantissa of the two floating-point numbers is extended by 1 bit. After this preprocessing, the exponents of the two floating-point numbers are matched with the input of the exponent processing unit. Therefore, when the bit width of the addend is greater than the maximum addend bit width and the bit width of the addend is less than or equal to the maximum addend bit width, when the bit width of the addend is greater than the maximum addend bit width and the bit width of the addend is less than Or equal to the maximum addend bit width or when the addend bit width is greater than the maximum addend bit width and the addend bit width is greater than the maximum addend bit width, the control circuit may determine the number of calls of the exponent processing unit according to the following formula :

m= ceil(P/(Q-1)),

Among them, m represents the number of times the exponent processing unit is called, P represents the bit width of the addend, Q represents the maximum addend bit width, and Q-1 represents the bit width of the part intercepted from the addend and the addend in each call. In each call, the addend and the addend are intercepted at the same time as the part of the bit width Q-1, so that the parts with the same bit width and the same digits intercepted from the addend and the addend are added. If in the call The intercepted part of the data is less than Q-1 bits or there is no data. Add 0 to the front or all of it to make up the Q-1 bits of data. After extending a carry before the part intercepted from the addend and the addend, the addend part and the addend part of the input exponent processing unit are formed. Therefore, Q also represents the addend of the input exponential processing unit each time it is called. The bit width of the part and the addend part.

Therefore, the second control circuit can intercept the Q-1 bit part from the addend and the addend in the same order as the input of the exponent processing unit every time the exponent processing unit is called, and obtain this time by the exponent processing unit. The index result of the call, and the final index is obtained after calling the index processing unit m times. It is worth noting that the above-mentioned same order can be from high order to low order, or from low order to high order.

For example, the bit width of the addend is 6 bits, the bit width of the addend is 9 bits, and the maximum addend bit width and the maximum addend bit width supported by the exponent processing unit are both 8 bits. Therefore, the number of times the exponent processing unit is called is ceil(9/(8-1))=2, and first add 0 in front of the addend, so that the bit width of the addend and the bit width of the addend are the same, and then every time In the call, the 7-bit part of the addend and the addend are simultaneously intercepted in the order from high to low, and the two intercepted parts are extended by one carry bit to form two 8-bit carry bits. The data is added. In the second call (that is, the last call), only 2 bits of data can be intercepted from the addend and the addend (only 2 bits of data are left). Therefore, the intercepted data in the second call Add 0 to the front of the 2-bit data to make up 7 bits, and expand a carry bit to form two 8-bit data with carry to add.

It is worth noting that in this example, when the bit width of the addend is greater than the maximum addend bit width and the bit width of the addend is less than or equal to the maximum addend bit width and when the bit width of the addend is greater than the maximum addend bit width And when the bit width of the addend is less than or equal to the maximum addend bit width, the call to the exponential processing unit is also applicable to the third embodiment of the present disclosure.

According to an embodiment, the exponent processing unit may further include a second shift and add circuit configured to obtain the post-multiplication operation according to the exponent result obtained by calling the exponent processing unit each time The index.

Further, the second shift and add circuit includes a second shifter, a second intermediate memory, and a second adder. When the second control circuit calls the exponent processing unit multiple times, after the first call , The second shifter shifts the index result obtained by the first call and stores the shifted index result in the second intermediate memory, starting from the second call of the index processing unit, the The second shifter shifts the exponent result obtained in the current call, and the second adder adds the shifted exponent result to the value stored in the second intermediate memory and adds the result of the addition. The second intermediate memory is stored in the second intermediate memory to update the second intermediate memory, and the value stored in the second intermediate memory in the last call is used as the exponent after the multiplication operation.

Each time the exponent processing unit is called, the second shifter shifts the exponent result obtained in the current call in the following manner: if the exponent processing unit is called, the index is intercepted and added in the order from high to low. When the number and the addend, the part intercepted from the addend and the addend in the current call is shifted to the left. The shift bit is the bit of the part after the part intercepted from the addend in the current call number.

For example, combining the above example, for example, the bit width of the addend is 6bit, the bit width of the addend is 9bit, and the maximum addend bit width and the maximum addend bit width supported by the exponent processing unit are both 8bit. In accordance with the order from high to low, both the addend and the addend are truncated with a bit width of 7 bits. Specifically, after the exponent processing unit is called for the first time, the second shifter shifts the exponent result obtained in the first call by 2 bits to the left (because there are 2 bits after the part intercepted by the addend in this call. Data) and store the shifted index result in the second intermediate memory. Starting from the second call to the index processing unit, the second shifter shifts the index result obtained in the current call to the left , Because there is no more data after the intercepted part in this call, it is shifted by 0 bits to the left, that is, without shifting, the second adder will shift the result of the exponent by 0 bits with the result of the exponent stored in the second intermediate memory. Add the values and store the result of the addition in the second intermediate memory to update the second intermediate memory. Since this second call is the last call, it is stored in the second intermediate memory after the second call. The value in the second intermediate memory is the exponent after the multiplication operation.

According to the situation that the multiplier (mantissa processing unit and exponent processing unit) of the present disclosure described above is called multiple times, it can be known that the control module may include multiple sub-modules, and the multiple sub-modules may be used to execute multiple sub-modules. Various operations in this call, such as determining multiple calls to the mantissa processing unit, determining the number of calls, determining the input of the mantissa processing unit data in each call, determining whether the mantissa bit width matches the bit width supported by the mantissa processing unit, and adjusting Mantissa input, etc. The second control module may also include multiple sub-modules, and similarly, these sub-modules may respectively perform various operations in multiple calls.

The foregoing describes in detail the operations performed by the multiplier of the present disclosure to multiply the mantissa of the first floating-point number and the second floating-point number when performing floating-point operations in conjunction with FIGS. 4-6. Of course, in Figure 4, in order to focus on describing the operation of the mantissa processing unit of the multiplier of the present disclosure, other units, such as the exponent processing unit and the symbol processing unit, are not drawn and described. Hereinafter, the overall description of the multiplier of the present disclosure will be given in conjunction with FIG. 7. The previous description of the mantissa processing unit is also applicable to the situation depicted in FIG. 7.

FIG. 7 is an overall schematic block diagram showing a multiplier 700 according to an embodiment of the present disclosure. It should be understood that the positions, existence, and connection relationships of the various units depicted in the figure are only exemplary and not restrictive. For example, some of the units can be integrated, while other units can also be separated or depending on the application scenario. It is omitted or replaced if it is different.

The multiplier of the present disclosure can be exemplarily divided into a first stage and a second stage in the operation of each operation mode according to the operation flow, as shown by the dotted line in the figure. In summary, in the first stage: output the calculation result of the sign bit, output the intermediate calculation result of the exponent bit, output the intermediate calculation result of the mantissa bit (for example, including the aforementioned encoding process of the input mantissa fixed-point multiplication Booth algorithm and Hua Laisha tree compression process). In the second stage: regularize and round the exponent and mantissa to output the calculation result of the exponent and the calculation result of the mantissa.

As shown in Figure 7, the multiplier of the present disclosure may include a mode selection unit 702 and a normalization processing unit 704, wherein the mode selection unit may select an operation mode according to the input mode signal (in_mode). In an embodiment, the input mode signal may correspond to the operation mode number in Table 2. For example, when the input mode signal indicates the operation mode number "1" in Table 2, the multiplier can be made to work in the operation mode of FP16*FP16, and when the input mode signal indicates the operation mode number "3" in Table 2 At this time, the multiplier can be operated in the FP32*FP32 operation mode. For the purpose of illustration, Figure 7 only shows four exemplary operation modes of FP16*FP16, BF16*BF16, FP32*FP32, and FP32*BP16. However, as mentioned above, the multiplier of the present disclosure also supports many other different operation modes.

The normalization processing unit may be configured to perform processing on the first floating-point number or the second floating-point number according to the operation mode when the first floating-point number or the second floating-point number is a non-normalized non-zero floating-point number. Normalization processing to obtain the corresponding exponent and mantissa, for example, according to the IEEE754 standard, the floating-point number in the data format indicated by the operation mode is regularized.

Further, the multiplier includes a mantissa processing unit to perform a multiplication operation of the first floating-point number mantissa and the second floating-point number mantissa. To this end, in one or more embodiments, the mantissa processing unit may include a bit expansion circuit 706, a Booth encoder 708, a partial product generation circuit 710, a Wallace tree compressor 712, and an adder 714. The number expansion circuit may be used to expand the mantissa of at least one of the first floating-point number and the second floating-point number by a number of bits, for example, adding zeros to the upper bits, so as to be suitable for the operation of the Booth encoder. The control circuit can perform the above operations of calling the mantissa processing unit multiple times according to the mantissa obtained after the sign bit extension of the mantissa by the bit extension circuit. Since the Booth encoder, partial product generation circuit, Wallace tree compressor and adder have been described in detail in conjunction with Figures 4-6, the same description is also applicable here and will not be repeated here. .

In some embodiments, the multiplier of the present disclosure further includes a regularization unit 716 and a rounding unit 718, and the regularization unit and the rounding unit have the same functions as the units shown in FIG. 3. Specifically, for the regularization unit, it can perform floating-point numbers on the addition result and the exponent data from the exponent processing unit according to the data format indicated by the output mode signal "out_mode" as shown in Figure 7. Regularization processing to obtain regularized exponent results and regularized mantissa results. For example, according to the data format indicated by the output mode signal, the regularization unit can adjust the bit width of the exponent and the mantissa to meet the requirements of the data format indicated above. For another example, when the highest bit of the mantissa is 0, and the mantissa is not 0, the regularization unit can repeatedly shift the mantissa by 1 bit to the left, and subtract 1 from the exponent until the highest bit value is 1. For the rounding unit, in one embodiment, it can be used to perform a rounding operation on the regularized mantissa result according to a rounding mode to obtain a rounded mantissa, and use the rounded mantissa as the multiplication operation After the mantissa.

In one or more embodiments, the aforementioned output mode signal may be a part of the operation mode, and is used to indicate the data format after the multiplication operation. For example, as described in Table 3 above, when the operation mode number is "12", the number "1" can be equivalent to the aforementioned "in_mode" signal, which is used to instruct the execution of the FP16*FP16 multiplication operation, and The digit "2" can be equivalent to the "out_mode" signal, which is used to indicate that the data type of the output result is BF16. Therefore, it can be understood that in some application scenarios, the output mode signal may be combined with the aforementioned input mode signal to provide the mode selection unit. Based on the combined mode signal, the mode selection unit can clarify the data format of the input data and the output result in the initial stage of the operation of the multiplier without separately providing the output mode signal to the regularization, which can further simplify the operation.

In one or more embodiments, for the aforementioned rounding operation, the following five rounding modes can be exemplarily included.

(1) Round to the nearest value: In this mode, when the two values are similarly close, the even number takes precedence. At this time, the result will be rounded to the closest and representable value, but when there are two numbers that are equally close, the even number among them is taken as the rounding result (in the binary bit, it is a number ending in 0);

(2) Rounding: See the example below for exemplary operations;

(3) Rounding towards +∞: Under this rule, the result will be rounded towards positive infinity;

(4) Rounding towards -∞: Under this rule, the result will be rounded towards negative infinity; and

(5) Rounding towards 0: Under this rule, the result will be rounded towards 0.

For the example of mantissa rounding in "rounding" mode: for example, the 24-bit mantissa of two normalized floating-point numbers is multiplied to obtain a 48-bit (47~0) mantissa, which is normalized (if the highest bit of the mantissa is If it is 0, move the mantissa to the left by 1 bit; if the highest bit of the mantissa is 1, the mantissa does not move, and the temporary order code requested above is added by 1), and only the 46th to the 24th digits are taken during output. When the 23rd digit of the mantissa is 0, the (23-0) digit is discarded; when the 23rd digit of the mantissa is 1, the 24th digit is 1 and the (23-0) digit is discarded.

Returning to Figure 7, the multiplier of the present disclosure further includes an exponent processing unit 720 and a sign processing unit 722, wherein the exponent processing unit can be used to obtain the exponent of the first floating-point number and the exponent of the second floating-point number according to the operation mode, The exponent after the multiplication operation. For example, the exponent processing circuit can add the exponent bit data of the first floating-point number, the exponent bit data of the second floating-point number, and the respective offset values of the corresponding input floating-point data type, and subtract the output floating-point data type To obtain the exponent bit data of the product of the first floating-point number and the second floating-point number. In one or more embodiments, the exponent processing unit may be implemented as or include an addition and subtraction circuit, which is configured to perform according to the operation mode, the exponent of the first floating-point number, the exponent of the second floating-point number, and The operation mode obtains the exponent after the multiplication operation.

The sign processing unit may be implemented as an exclusive OR circuit in one embodiment, which is used to perform an exclusive OR operation on the sign bit data of the first floating point number and the second floating point number to obtain the first floating point number The sign data of the product of the second floating-point number.

The entire multiplier of the present disclosure is described in detail above in conjunction with Figure 7. Through this description, those with ordinary knowledge in the art can understand that the multiplier of the present disclosure supports operations in multiple operation modes, thereby overcoming the defect of the multiplier that only supports a single floating-point operation in the prior art. Furthermore, because the multiplier of the present disclosure can be multiplexed, it also supports high-bit wide floating-point data, which reduces the computational cost and overhead. In one or more embodiments, the multiplier of the present disclosure may also be arranged or included in an integrated circuit chip or a computing device to implement multiplication operations on floating-point numbers in multiple operation modes.

FIG. 8 is a flowchart illustrating a method 800 for performing floating-point number multiplication operations using a multiplier according to an embodiment of the present disclosure. It can be understood that the multiplier described here is the multiplier described in detail in conjunction with Figures 1-7, so the previous descriptions of the multiplier and its internal composition, functions and operations are also applicable here. description of.

As shown in Figure 8, the method 800 may include using the exponent processing unit of the multiplier at step S802 to obtain the exponent according to the operation mode, the exponent of the first floating-point number, and the exponent of the second floating-point number. Exponent after multiplication. As mentioned earlier, the operation mode can be one of a variety of operation modes, and can be used to indicate the data format of floating-point numbers. In one or more embodiments, the operation mode can also be used to determine the data format of the floating point number of the output result.

Next, at step S804, the method 800 may use the mantissa processing unit of the multiplier to obtain the mantissa after the multiplication operation according to the operation mode, the first floating-point number, and the second floating-point number. Regarding the exemplary operation of the mantissa, the present disclosure uses the Booth coding algorithm and the Wallace tree compressor in some preferred embodiments, so as to improve the efficiency of the mantissa processing. In addition, when the first floating-point number and the second floating-point number are signed numbers, the method 800 may also be used in step S806 to obtain the post-multiplication operation according to the sign of the first floating-point number and the sign of the second floating-point number. symbol.

Although the above method shows the use of the multiplier of the present disclosure to perform floating-point number multiplication in the form of steps, the order of these steps does not mean that the steps of the method must be executed in the stated order, but can be performed in other orders or in parallel. Way to deal with. In addition, the other steps of the method 800 are not described here for the sake of brevity of description, but those with ordinary knowledge in the field can understand that the method can also be executed by using a multiplier in combination with Figures 1-7. Various operations described.

In the above-mentioned embodiments of the present disclosure, the description of each embodiment has its own focus. For parts that are not described in detail in an embodiment, reference may be made to related descriptions of other embodiments. The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, all possible combinations of the various technical features in the above-mentioned embodiments are not described. However, as long as there is no contradiction in the combination of these technical features, they should all be combined. It is considered as the range described in this specification.

Figure 9 is a structural diagram showing a combined processing device 900 according to an embodiment of the present disclosure. As shown in the figure, the combined processing device 900 includes a computing device 902, which may include the multiplier of the present disclosure as described above with reference to the accompanying drawings. In addition, the combined processing device also includes a universal interconnection interface 904 and other processing devices 906. The computing device according to the present disclosure interacts with other processing devices to jointly complete the operation specified by the user.

According to the solution of the present disclosure, the other processing device may include one or more types of general-purpose and/or special-purpose processors such as a central processing unit ("CPU"), a graphics processing unit ("GPU"), and a neural network processor. The number of processors is not limited but determined according to actual needs. In one or more embodiments, the other processing device can be used as an interface between the computing device of the present disclosure (which can be embodied as a machine learning computing device) and external data and control, and perform operations including but not limited to data handling, and complete the processing of the machine. The basic control of the start and stop of the learning computing device; other processing devices can also cooperate with the machine learning computing device to complete computing tasks.

According to the solution of the present disclosure, the universal interconnection interface can be used to transmit data and control commands between a computing device and other processing devices. For example, the computing device can obtain required input data from other processing devices via the universal interconnection interface, and write the input data to the on-chip storage device of the computing device. Further, the computing device can obtain control instructions from other processing devices via the universal interconnection interface, and write them into the on-chip control buffer of the computing device. Alternatively or alternatively, the universal interconnection interface can also read the data in the storage module of the computing device and transmit it to other processing devices.

Optionally, the combined processing device may further include a storage device 908, which may be connected to the computing device and the other processing device respectively. In one or more embodiments, the storage device may be used to store the data of the computing device and the other processing device, and it is especially suitable for the data required to be calculated in the internal storage of the computing device or other processing device. Saved information.

According to different application scenarios, the combined processing device of the present disclosure can be used as a system-on-chip for mobile phones, robots, drones, video capture, video surveillance equipment and other equipment, thereby effectively reducing the core area of the control part, increasing the processing speed and reducing the overall Power consumption. In this case, the universal interconnection interface of the combined processing device is connected to some parts of the equipment. Some components here can be, for example, a monitor, a display, a mouse, a keyboard, a network card, or a wifi interface.

In some embodiments, the present disclosure also discloses a chip or integrated circuit chip, which includes the above-mentioned computing device, the combined processing device, and the multiplier of the present disclosure. In other embodiments, the present disclosure also discloses a chip package structure, which includes the above-mentioned chip.

In some embodiments, the present disclosure also discloses a board card, which includes the above-mentioned chip packaging structure. Refer to Figure 10, which provides the aforementioned exemplary board card 1000. In addition to the aforementioned chip 1002, the board card 1000 may also include other supporting components. The supporting components may include, but are not limited to: a storage device 1004, an interface device 1006 and control device 1008.

The storage device is connected with the chip in the chip package structure through a bus bar for storing data. The storage device may include multiple groups of storage units 1010. Each group of the storage unit and the chip are connected by a bus bar. It can be understood that each group of the storage units may be DDR SDRAM ("Double Data Rate SDRAM", double-rate synchronous dynamic random memory).

DDR does not need to increase the clock frequency to double the speed of SDRAM. DDR allows data to be read on the rising and falling edges of the clock pulse. The speed of DDR is twice that of standard SDRAM. In an embodiment, the storage device may include 4 groups of the storage unit. Each group of the memory cell may include a plurality of DDR4 particles (wafers). In an embodiment, the chip may include four 72-bit DDR4 controllers. In the 72-bit DDR4 controller, 64 bits are used for data transmission and 8 bits are used for ECC verification.

In an embodiment, each group of the storage unit may include a plurality of double-rate synchronous dynamic random memories arranged in parallel. DDR can transmit data twice in one clock cycle. A controller for controlling the DDR is arranged in the chip for controlling the data transmission and data storage of each storage unit.

The interface device is electrically connected to the chip in the chip package structure. The interface device is used to implement data transmission between the chip and an external device 1012 (such as a server or a computer). For example, in one embodiment, the interface device may be a standard PCIE interface. For example, the data to be processed is transferred from the server to the chip through a standard PCIE interface to realize data transfer. In another embodiment, the interface device may also be other interfaces. The present disclosure does not limit the specific manifestations of the other interfaces mentioned above, as long as the interface unit can realize the switching function. In addition, the calculation result of the chip is still sent back to an external device (such as a server) by the interface device.

The control device is electrically connected with the wafer to monitor the state of the wafer. Specifically, the chip and the control device may be electrically connected through an SPI interface. The control device may include a microcontroller ("MCU", Micro Controller Unit). The wafer may include multiple processing wafers, multiple processing cores, or multiple processing circuits, and can drive multiple loads. Therefore, the wafer can be in different working states such as multi-load and light-load. The control device can realize the regulation and control of the working states of multiple processing wafers, multiple processing and/or multiple processing circuits in the wafer.

In some embodiments, the present disclosure also discloses an electronic device or device, which includes the above-mentioned board. According to different application scenarios, electronic equipment or devices can include data processing devices, robots, computers, printers, scanners, tablets, smart terminals, mobile phones, driving recorders, navigators, sensors, monitors, Servers, cloud servers, cameras, cameras, projectors, watches, headsets, mobile storage, wearable devices, vehicles, household appliances, and/or medical equipment. The transportation means include airplanes, ships and/or vehicles; the household appliances include televisions, air conditioners, microwave ovens, refrigerators, electric cookers, humidifiers, washing machines, electric lights, gas stoves, and range hoods; and the medical equipment includes nuclear magnetic resonance Instrument, B-ultrasound instrument and/or electrocardiograph.

It should be noted that for the foregoing method embodiments, for the sake of simple description, they are all expressed as a series of action combinations, but those with ordinary knowledge in the art should know that this disclosure is not subject to the described sequence of actions. Restricted, because according to this disclosure, certain steps can be performed in other order or at the same time. Secondly, those with ordinary knowledge in the art should also be aware that the embodiments described in the specification are optional embodiments, and the actions and modules involved are not necessarily required for this disclosure.

In the above-mentioned embodiments, the description of each embodiment has its own focus. For parts that are not described in detail in an embodiment, reference may be made to related descriptions of other embodiments.

In the several embodiments provided in this disclosure, it should be understood that the disclosed device can be implemented in other ways. For example, the device embodiments described above are merely illustrative, for example, the division of the units is only a logical function division, and there may be other divisions in actual implementation, for example, multiple units or elements can be combined or integrated. To another system, or some features can be ignored, or not implemented. In addition, the displayed or discussed mutual coupling or direct coupling or communication connection may be indirect coupling or communication connection through some interfaces, devices or units, and may be in electrical, optical, acoustic, magnetic or other forms.

The units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed to multiple network units. . Some or all of the units may be selected according to actual needs to achieve the objectives of the solutions of the embodiments.

In addition, the functional units in the various embodiments of the present disclosure may be integrated into one processing unit, or each unit may exist alone physically, or two or more units may be integrated into one unit. The above-mentioned integrated unit can be realized either in the form of hardware or in the form of software program modules.

If the integrated unit is realized in the form of a software program module and sold or used as an independent product, it can be stored in a computer readable memory. Based on this understanding, when the technical solution of this disclosure can be embodied in the form of a software product, the computer software product is stored in a memory and includes a number of instructions to enable a computer device (which can be a personal computer, a server or a network). Road equipment, etc.) execute all or part of the steps of the methods described in the various embodiments of the present disclosure. The aforementioned memory includes: flash drives, read-only memory ("ROM", Read-Only Memory), random access memory ("RAM", Random Access Memory), mobile hard drives, magnetic disks or optical disks, etc. The medium on which the program code is stored.

The foregoing can be better understood according to the following clauses:

Clause A1, a multiplier for multiplication of floating-point numbers, wherein the multiplier includes:

The mantissa processing unit is configured to obtain the mantissa after the multiplication operation according to the mantissa of the floating-point number,

The mantissa processing unit includes a control circuit configured to call the mantissa multiple times when the bit width of at least one of the two floating-point numbers is greater than the data bit width that can be processed by the mantissa processing unit at one time Processing unit.

Clause A2, the multiplier according to clause A1, wherein the two floating-point numbers include a first floating-point number and a second floating-point number, and the mantissa processing unit supports a first bit width and a second bit width, The mantissa of the first floating-point number is used as the first input corresponding to the first bit width, the mantissa of the second floating-point number is used as the second input corresponding to the second bit width, and the first The bit width of the input is less than or equal to the first bit width, and the control circuit is configured to call the mantissa processing unit multiple times to obtain the bit width of the second input when the bit width of the second input is greater than the second bit width. The mantissa after the multiplication operation.

Clause A3, the multiplier according to clause A1 or clause A2, wherein the two floating-point numbers include a first floating-point number and a second floating-point number, and the mantissa processing unit supports a first bit width and a second bit width. Bit width, the mantissa of the first floating point number is used as the first input corresponding to the first bit width, and the mantissa of the second floating point number is used as the second input corresponding to the second bit width, so The control circuit is used for when the bit width of the first input is greater than the first bit width and the bit width of the second input is less than or equal to the second bit width, when the bit width of the second input is larger When the second bit width and the bit width of the first input are less than or equal to the first bit width or when the bit width of the first input is greater than the first bit width and the second input When the bit width is greater than the second bit width, the mantissa processing unit is called multiple times to obtain the mantissa after the multiplication operation.

Clause A4, the multiplier according to any one of clauses A1-A3, wherein when the mantissa bit width of the first floating-point number is smaller than the mantissa bit width of the second floating-point number and the first bit width is larger At the second bit width, or when the mantissa bit width of the first floating-point number is greater than the mantissa bit width of the second floating-point number and the first bit width is smaller than the second bit width, The control circuit selects the mantissa of the first floating-point number as the second input corresponding to the second bit width and selects the mantissa of the second floating-point number as the mantissa corresponding to the first bit width The first input.

Clause A5, the multiplier according to any one of clauses A1-A4, wherein when the bit width of the first input is greater than the first bit width and the bit width of the second input is less than or equal to the first bit width When the width is two bits, the control circuit determines the number of invocations of the mantissa processing unit according to the bit width of the first input and the first bit width and inputs the data of the mantissa processing unit in each call.

Clause A6, the multiplier according to any one of clauses A1-A5, wherein when the bit width of the second input is greater than the second bit width and the bit width of the first input is less than or equal to the first input When one bit is wide, the control circuit determines the number of invocations of the mantissa processing unit according to the bit width of the second input and the second bit width and inputs the data of the mantissa processing unit in each call.

Clause A7, the multiplier according to any one of clauses A1-A6, wherein when the bit width of the first input is greater than the first bit width and the bit width of the second input is greater than the second bit When it is wide, the control circuit determines the number of times to call the mantissa processing unit according to the bit width of the first input and the first bit width, and the bit width of the second input and the second bit width, and Enter the data of the mantissa processing unit in each call.

Clause A8, the multiplier according to any one of clauses A1-A7, wherein the mantissa processing unit further includes a shift and add circuit, and the shift and add circuit is configured to obtain the result of each invocation of the mantissa processing unit. The mantissa result of to obtain the mantissa after the multiplication operation.

Clause A9, the multiplier according to any one of clauses A1-A8, wherein the shift and add circuit includes a shifter, an intermediate memory, and an adder, and when the control circuit calls the mantissa processing unit multiple times After the first call, the shifter shifts the mantissa result obtained in the first call to obtain the shifted mantissa result and stores the shifted mantissa result in the intermediate memory, starting from the first At the beginning of the second call, the shifter shifts the mantissa result obtained in the current call to obtain the current mantissa result, and the adder compares the current mantissa result with the result stored in the intermediate memory. Add and store the result of the addition in the intermediate memory to update the intermediate memory, and the result stored in the intermediate memory after the last call is used as the mantissa after the multiplication operation.

Clause A10, the multiplier according to any one of clauses A1-A9, wherein the multiplier further includes an exponent processing unit configured to obtain the exponent of the two floating-point numbers The exponent after the multiplication operation, the exponent processing unit includes a second control circuit, and the second control circuit is used to determine the exponent width of one of the two floating-point numbers and the two supported by the exponent processing unit. One of the bit widths or the exponent bit width of the two floating-point numbers and the two bit widths supported by the exponent processing unit are used to determine multiple calls to the exponent processing unit to obtain the multiplication index.

Clause A11. The multiplier according to any one of clauses A1-A10, wherein the two floating-point numbers include a first floating-point number and a second floating-point number, and the exponent processing unit supports a third bit width and The fourth bit width, the exponent of the first floating point number is used as the third input corresponding to the third bit width, and the exponent of the second floating point number is used as the fourth input corresponding to the fourth bit width , The bit width of the third input is less than or equal to the third bit width, and the second control circuit is configured to call the third bit width multiple times when the fourth input bit width is greater than the fourth bit width. The exponent processing unit obtains the exponent after the multiplication operation.

Clause A12. The multiplier according to any one of clauses A1-A11, wherein the two floating-point numbers include a first floating-point number and a second floating-point number, and the exponent processing unit supports a third bit width and The fourth bit width, the exponent of the first floating point number is used as the third input corresponding to the third bit width, and the exponent of the second floating point number is used as the fourth input corresponding to the fourth bit width The second control circuit is used for when the bit width of the third input is greater than the third bit width and the bit width of the fourth input is less than or equal to the fourth bit width, when the fourth bit width is When the bit width of the input is greater than the fourth bit width and the bit width of the third input is less than or equal to the third bit width or when the bit width of the third input is greater than the third bit width and the When the bit width of the fourth input is greater than the fourth bit width, the exponent processing unit is called multiple times to obtain the exponent after the multiplication operation.

Clause A13, the multiplier according to any one of clauses A1-A12, wherein when the exponent bit width of the first floating-point number is smaller than the exponent bit width of the second floating-point number and the third bit width is larger When the fourth bit width, or when the exponent bit width of the first floating-point number is greater than the exponent bit width of the second floating-point number and the third bit width is smaller than the fourth bit width, The second control circuit selects the exponent of the first floating-point number as the fourth input corresponding to the fourth bit width and selects the exponent of the second floating-point number as the third bit width Corresponding third input.

Clause A14, the multiplier according to any one of clauses A1-A13, wherein the second control circuit is used when the bit width of the third input is less than or equal to the bit width of the fourth input and the When the third bit width is less than or equal to the fourth bit width, the number of times the exponent processing unit is called is determined according to the bit width of the fourth input and the third bit width, and the Data of the index processing unit.

Clause A15, the multiplier according to any one of clauses A1-A14, wherein the exponent processing unit further includes a second shift and add circuit, and the second shift and add circuit is configured to call the exponent according to each time The exponent result obtained by the processing unit is used to obtain the exponent after the multiplication operation.

Clause A16, the multiplier according to any one of clauses A1-A15, wherein the mantissa processing unit includes a partial product operation unit and a partial product summation unit, wherein the partial product operation unit is configured to The mantissa of the floating-point number obtains an intermediate result, and the partial product summation unit is configured to perform an addition operation on the intermediate result to obtain an addition result, and use the addition result as the mantissa after the multiplication operation.

Clause A17. The multiplier according to any one of clauses A1 to A16, wherein the partial product operation unit includes a Booth coding circuit, and the Booth coding circuit is configured to compare the first floating-point number or the The mantissa of the second floating-point number is subjected to Booth coding processing to obtain the intermediate result.

Clause A18, the multiplier according to any one of clauses A1-A17, wherein the partial product summation unit includes an adder, and the adder is used to add the intermediate result to obtain the sum result.

Clause A19, the multiplier according to any one of clauses A1 to A18, wherein the partial product summation unit includes a Wallace tree and an adder, and the Wallace tree is used to perform a calculation on the intermediate result And to obtain a second intermediate result, and the adder is used to add the second intermediate result to obtain the added result.

Clause A20. The multiplier according to any one of clauses A1-A19, wherein the adder includes at least one of a full adder, a tandem adder, and a forward bit adder.

Clause A21, the multiplier according to any one of clauses A1-A20, wherein, when the number of intermediate results is less than M, a zero value is added as an intermediate result, so that the number of intermediate results is equal to M, where M is a preset positive integer.

Clause A22, the multiplier according to any one of clauses A1-A21, wherein each of the Wallace trees has M inputs and N outputs, and the number of Wallace trees is not less than K, where N Is a preset positive integer less than M, and K is a positive integer not less than the maximum bit width of the intermediate result.

Clause A23, the multiplier according to any one of clauses A1-A22, wherein the partial product summation unit is used to select one or more groups of the Wallace trees to add the intermediate results, wherein Each group of the Wallace trees has X Wallace trees, and X is the number of bits of the intermediate result, wherein the Wallace trees in each group have a sequential carry relationship, and between the groups The Wallace tree does not have a carry relationship.

Clause A24. The multiplier according to any one of clauses A1-A23, wherein the multiplier further includes:

A normalization processing unit, configured to perform normalization processing on the at least one floating-point number when at least one of the two floating-point numbers is a non-normalized non-zero floating-point number to obtain the corresponding The exponent and mantissa.

Clause A25, the multiplier according to any one of clauses A1-A24, wherein the multiplier is configured to perform a multiplication operation of the two floating-point numbers according to an operation mode, and the operation mode indicates the two floating-point numbers The mantissa processing unit is used to obtain the mantissa after the multiplication operation according to the operation mode and the mantissa of the two floating-point numbers, and the exponent processing unit is used to obtain the mantissa after the multiplication operation according to the operation mode And the exponent of the two floating-point numbers to obtain the exponent after the multiplication operation.

Clause A26, according to the multiplier of any one of clauses A1-A25, the normalization processing unit is further configured to normalize at least one of the two floating-point numbers according to the operation mode Process to obtain the corresponding exponent and mantissa.

Clause A27, the multiplier according to any one of clauses A1-A26, wherein the data format includes half-precision floating-point numbers, single-precision floating-point numbers, brain floating-point numbers, double-precision floating-point numbers, custom At least one of floating point numbers.

Clause A28, the multiplier according to any one of clauses A1-A27, wherein the mantissa processing unit includes a bit number expansion circuit, and the bit number expansion circuit is configured to compare the first floating-point number and the first The mantissa of at least one of the two floating-point numbers is expanded by digits.

Clause A29. The multiplier according to any one of clauses A1-A28, wherein the floating-point number further includes a sign, and the multiplier further includes:

The sign processing unit is used to obtain the sign after the multiplication operation according to the sign of the two floating-point numbers.

Clause A30. The multiplier according to any one of clauses A1-A29, wherein the sign processing unit includes an exclusive-or logic circuit, and the exclusive-or logic circuit is used to perform an exclusive operation according to the signs of the two floating-point numbers. Or operation to obtain the sign after the multiplication operation.

Clause A31, the multiplier according to any one of clauses A1-A30, further includes a regularization unit for:

Perform floating-point regularization processing on the mantissa and exponent after the multiplication operation to obtain a regularized exponent result and a regularized mantissa result, and use the regularized exponent result and the regularized mantissa result as the multiplication operation After the exponent and the mantissa after the multiplication operation.

Clause A32, the multiplier according to any one of clauses A1-A31, further includes:

The rounding unit is configured to perform a rounding operation on the regularized mantissa result according to a rounding mode to obtain a rounded mantissa, and use the rounded mantissa as the mantissa after the multiplication operation.

Item A33, a method for performing floating-point number multiplication using a multiplier, where,

Using the mantissa processing unit of the multiplier to obtain the mantissa after the multiplication operation according to the mantissa of the floating-point number,

The mantissa processing unit includes a control circuit configured to call the mantissa multiple times when the bit width of at least one of the two floating-point numbers is greater than the data bit width that can be processed by the mantissa processing unit at one time Processing unit.

Clause A34, an integrated circuit chip including the multiplier according to any one of clauses A1-A31.

Clause A35, a computing device comprising the multiplier according to any one of clauses A1-A31 or the integrated circuit chip according to clause A34.

The embodiments of the disclosure are described in detail above, and specific examples are used in this article to illustrate the principles and implementation of the disclosure. The descriptions of the above embodiments are only used to help understand the methods and core ideas of the disclosure; at the same time, for Those with ordinary knowledge in the field, based on the ideas of this disclosure, will have changes in the specific implementation and scope of application. In summary, the content of this specification should not be construed as a limitation on this disclosure.

It should be understood that the terms "first", "second", "third" and "fourth" in the scope of patent application, specification and drawings of this disclosure are used to distinguish different objects, not to describe specific order. The terms "including" and "comprising" used in the specification and the scope of the patent application of this disclosure indicate the existence of the described features, wholes, steps, operations, elements and/or elements, but do not exclude one or more other features, wholes The existence or addition of, steps, operations, elements, elements, and/or collections thereof.

It should also be understood that the terms used in this disclosure specification are only for the purpose of describing specific embodiments, and are not intended to limit the disclosure. As used in this disclosure specification and the scope of the patent application, unless the context clearly indicates other circumstances, the singular forms of "a", "an" and "the" are intended to include plural forms. It should be further understood that the term "and/or" used in this disclosure specification and the scope of the patent application refers to any combination of one or more of the items listed in association and all possible combinations, and includes these combinations.

As used in this specification and the scope of the patent application, the term "if" can be interpreted as "when" or "once" or "in response to determination" or "in response to detection" depending on the context. Similarly, the phrase "if determined" or "if detected [described condition or event]" can be interpreted as meaning "once determined" or "response to determination" or "once detected [described condition or event]" depending on the context. Event]" or "in response to the detection of [the described condition or event]".

The embodiments of the present disclosure are described in detail above, and specific examples are used in this article to illustrate the principles and implementation manners of the present disclosure. The descriptions of the above embodiments are only used to help understand the methods and core ideas of the present disclosure. At the same time, any changes or modifications made by those with ordinary knowledge in the field based on the ideas of this disclosure, the specific implementation and application scope of this disclosure, are all within the protection scope of this disclosure. In summary, the content of this specification should not be construed as a limitation of this disclosure.

100: floating point data format 102: sign bit 104: Exponent bit 106: Mantissa digit 200, 300, 700: multiplier 202, 720: Index processing unit 204: Mantissa Processing Unit 206, 722: symbol processing unit 308: Mode selection unit 312: Partial product operation unit 314: Partial product summation unit 316: control circuit 318, 716: Regularization Unit 320: rounding unit 322: XOR logic circuit 324: Normalized Processing Unit 400: Mantissa processing unit operation 402: Booth coding circuit 404: Partial product generation circuit 406: Wallace compressor 408, 714: adder 500: partial product 600: Operation process and schematic block diagram of Wallace Tree Compressor 702: Mode selection unit 704: Normalized Processing Unit 706: Digit Expansion Circuit 708: Booth Encoder 710: Partial product generation circuit 712: Wallace Tree Compressor 800: Method of performing floating-point number multiplication using a multiplier 716: mode selection unit 720: Mode selection unit 722: Mode Selection Unit 900: Combination processing device 902: computing device 904: Universal Interconnect Interface 906: other processing devices 908: storage device 1000: board 1002: chip 1004: storage device 1006: Interface device 1008: control device 1010: storage unit 1012: external equipment S802-S806: steps

[Figure 1] A schematic diagram showing a floating-point data format according to an embodiment of the present disclosure. [Figure 2] shows a schematic structural block diagram of a multiplier according to an embodiment of the present disclosure. [Figure 3] A block diagram showing more details of the multiplier according to an embodiment of the present disclosure. [Figure 4] A schematic block diagram showing a mantissa processing unit according to an embodiment of the present disclosure. [Figure 5] A schematic diagram showing the partial product operation according to an embodiment of the present disclosure. [Figure 6] shows the operation flow and schematic block diagram of the Wallace tree compressor according to an embodiment of the present disclosure. [Figure 7] shows an overall schematic block diagram of a multiplier according to an embodiment of the present disclosure. [Figure 8] A flowchart showing a method for performing floating-point number multiplication using a multiplier according to an embodiment of the present disclosure. [Figure 9] shows a structural diagram of a combined processing device according to an embodiment of the present disclosure. [Figure 10] A schematic diagram showing the structure of a board card according to an embodiment of the disclosure.

900: Combination processing device

902: computing device

904: Universal Interconnect Interface

906: other processing devices

908: storage device

Claims (35)

A multiplier used for multiplication of floating-point numbers, wherein the multiplier includes: The mantissa processing unit is configured to obtain the mantissa after the multiplication operation according to the mantissa of the floating-point number, The mantissa processing unit includes a control circuit configured to call the mantissa multiple times when the bit width of at least one of the two floating-point numbers is greater than the data bit width that can be processed by the mantissa processing unit at one time Processing unit. Such as the multiplier of claim 1, wherein the two floating-point numbers include a first floating-point number and a second floating-point number, and the mantissa processing unit supports a first bit width and a second bit width, and the first The mantissa of the floating point number is used as the first input corresponding to the first bit width, the mantissa of the second floating point number is used as the second input corresponding to the second bit width, and the bit width of the first input Is less than or equal to the first bit width, and the control circuit is configured to call the mantissa processing unit multiple times to obtain the multiplication operation when the second input bit width is greater than the second bit width mantissa. Such as the multiplier of claim 1, wherein the two floating-point numbers include a first floating-point number and a second floating-point number, and the mantissa processing unit supports a first bit width and a second bit width, and the first The mantissa of the floating point number is used as the first input corresponding to the first bit width, the mantissa of the second floating point number is used as the second input corresponding to the second bit width, and the control circuit is used for When the bit width of the first input is greater than the first bit width and the bit width of the second input is less than or equal to the second bit width, when the bit width of the second input is greater than the second bit width And the bit width of the first input is less than or equal to the first bit width or when the bit width of the first input is greater than the first bit width and the bit width of the second input is greater than the second bit width. When bit width, the mantissa processing unit is called multiple times to obtain the mantissa after the multiplication operation. Such as the multiplier of claim 3, wherein, when the mantissa bit width of the first floating-point number is smaller than the mantissa bit width of the second floating-point number and the first bit width is greater than the second bit width, Or when the mantissa bit width of the first floating-point number is greater than the mantissa bit width of the second floating-point number and the first bit width is smaller than the second bit width, the control circuit selects the first The mantissa of the floating point number is used as the second input corresponding to the second bit width and the mantissa of the second floating point number is selected as the first input corresponding to the first bit width. Such as the multiplier of claim 4, wherein, when the bit width of the first input is greater than the first bit width and the bit width of the second input is less than or equal to the second bit width, the control circuit The number of invocations of the mantissa processing unit and the input of data of the mantissa processing unit in each call are determined according to the bit width of the first input and the first bit width. Such as the multiplier of claim 4, wherein, when the bit width of the second input is greater than the second bit width and the bit width of the first input is less than or equal to the first bit width, the control circuit According to the bit width of the second input and the second bit width, the number of times the mantissa processing unit is called and the data of the mantissa processing unit are input in each call. Such as the multiplier of claim 4, wherein, when the bit width of the first input is greater than the first bit width and the bit width of the second input is greater than the second bit width, the control circuit The bit width of the first input and the first bit width and the bit width of the second input and the second bit width are used to determine the number of times the mantissa processing unit is called and the mantissa is input in each call Processing unit data. For example, the multiplier of any one of claims 2 to 7, wherein the mantissa processing unit further includes a shift and add circuit, and the shift and add circuit is used to calculate the mantissa result obtained by calling the mantissa processing unit each time Obtain the mantissa after the multiplication operation. For example, the multiplier of claim 8, wherein the shift and add circuit includes a shifter, an intermediate memory, and an adder. When the control circuit calls the mantissa processing unit multiple times, after the first call, the The shifter shifts the mantissa result obtained in the first call to obtain the shifted mantissa result and stores the shifted mantissa result in the intermediate memory. Starting from the second call, the shift The device shifts the mantissa result obtained in the current call to obtain the current mantissa result, the adder adds the current mantissa result to the result stored in the intermediate memory and stores the added result The intermediate memory is updated in the intermediate memory, and the result stored in the intermediate memory after the last call is used as the mantissa after the multiplication operation. Such as the multiplier of claim 1, wherein the multiplier further includes an exponent processing unit configured to obtain the exponent after the multiplication operation according to the exponents of the two floating-point numbers, the exponent The processing unit includes a second control circuit, the second control circuit is configured to use one of the exponent bit width of one of the two floating-point numbers and one of the two bit widths supported by the exponent processing unit, or according to the exponent bit width of one of the two floating-point numbers. The exponent bit width of the two floating-point numbers and the two bit width supported by the exponent processing unit determine that the exponent processing unit is called multiple times to obtain the exponent after the multiplication operation. For example, the multiplier of claim 10, wherein the two floating-point numbers include a first floating-point number and a second floating-point number, the exponent processing unit supports a third bit width and a fourth bit width, and the first The exponent of the floating point number is used as the third input corresponding to the third bit width, the exponent of the second floating point number is used as the fourth input corresponding to the fourth bit width, and the bit width of the third input is Less than or equal to the third bit width, and the second control circuit is configured to call the exponent processing unit multiple times to obtain the multiplication operation when the bit width of the fourth input is greater than the fourth bit width After the index. For example, the multiplier of claim 10, wherein the two floating-point numbers include a first floating-point number and a second floating-point number, the exponent processing unit supports a third bit width and a fourth bit width, and the first The exponent of the floating point number is used as the third input corresponding to the third bit width, the exponent of the second floating point number is used as the fourth input corresponding to the fourth bit width, and the second control circuit is used for When the bit width of the third input is greater than the third bit width and the bit width of the fourth input is less than or equal to the fourth bit width, when the bit width of the fourth input is greater than the fourth bit width Bit width and the bit width of the third input is less than or equal to the third bit width or when the bit width of the third input is greater than the third bit width and the bit width of the fourth input is greater than the When the fourth bit is wide, the exponent processing unit is called multiple times to obtain the exponent after the multiplication operation. Such as the multiplier of claim 12, wherein, when the exponent bit width of the first floating-point number is smaller than the exponent bit width of the second floating-point number and the third bit width is greater than the fourth bit width, Or when the exponent bit width of the first floating-point number is greater than the exponent bit width of the second floating-point number and the third bit width is smaller than the fourth bit width, the second control circuit selects the The exponent of the first floating point number is used as the fourth input corresponding to the fourth bit width and the exponent of the second floating point number is selected as the third input corresponding to the third bit width. Such as the multiplier of claim 13, wherein the second control circuit is used when the bit width of the third input is less than or equal to the bit width of the fourth input and the third bit width is less than or equal to the When the fourth bit is wide, the number of invocations of the index processing unit and the data of the index processing unit are input in each invocation according to the bit width of the fourth input and the third bit width. For example, the multiplier of any one of claims 11 to 14, wherein the exponent processing unit further includes a second shift and add circuit, and the second shift and add circuit is used to obtain the value obtained by calling the exponent processing unit each time The result of the exponent is used to obtain the exponent after the multiplication operation. For example, the multiplier of claim 1, wherein the mantissa processing unit includes a partial product operation unit and a partial product summation unit, wherein the partial product operation unit is used to obtain an intermediate result according to the mantissa of the two floating-point numbers, The partial product summation unit is configured to perform an addition operation on the intermediate result to obtain an addition result, and use the addition result as the mantissa after the multiplication operation. For example, the multiplier of claim 16, wherein the partial product operation unit includes a Booth coding circuit, and the Booth coding circuit is used to distribute the mantissa of the first floating-point number or the second floating-point number Encoding process to obtain the intermediate result. Such as the multiplier of claim 17, wherein the partial product summation unit includes an adder, and the adder is used to add the intermediate result to obtain the added result. Such as the multiplier of claim 17, wherein the partial product summation unit includes a Wallace tree and an adder, wherein the Wallace tree is used to add the intermediate results to obtain a second intermediate result , The adder is used to add the second intermediate result to obtain the added result. Such as the multiplier of claim 18 or 19, wherein the adder includes at least one of a full adder, a tandem adder, and an advance bit adder. For example, the multiplier of claim 19, wherein when the number of intermediate results is less than M, zero is added as an intermediate result, so that the number of intermediate results is equal to M, where M is a preset positive integer. For example, the multiplier of claim 21, wherein each of the Wallace trees has M inputs and N outputs, and the number of the Wallace trees is not less than K, where N is a preset positive integer less than M , K is a positive integer not less than the maximum bit width of the intermediate result. For example, the multiplier of claim 22, wherein the partial product summation unit is used to select one or more groups of the Wallace trees to add the intermediate results, wherein each group of the Wallace trees has X Wallace trees, X is the number of digits of the intermediate result, wherein the Wallace trees in each group have a sequential carry relationship, and the Wallace trees between each group do not have a carry relationship. Such as the multiplier of claim 10, wherein the multiplier further includes: A normalization processing unit, configured to perform normalization processing on the at least one floating-point number when at least one of the two floating-point numbers is a non-normalized non-zero floating-point number to obtain the corresponding The exponent and mantissa. Such as the multiplier of claim 10, wherein the multiplier is used to perform the multiplication operation of the two floating-point numbers according to the operation mode, the operation mode indicates the data format of the two floating-point numbers, and the mantissa is processed The unit is used to obtain the mantissa after the multiplication operation according to the operation mode and the mantissa of the two floating-point numbers, and the exponent processing unit is used to obtain the mantissa after the multiplication operation according to the operation mode and the mantissa of the two floating-point numbers. Exponent to obtain the exponent after the multiplication operation. For example, the multiplier of claim 25, wherein the normalization processing unit is further configured to perform normalization processing on at least one of the two floating-point numbers according to the operation mode to obtain a corresponding exponent And mantissa. For example, the multiplier of request 26, wherein the data format includes at least one of half-precision floating-point numbers, single-precision floating-point numbers, brain floating-point numbers, double-precision floating-point numbers, and custom floating-point numbers. For example, the multiplier of claim 17, wherein the mantissa processing unit includes a bit number expansion circuit, and the bit number expansion circuit is used to calculate at least one of the first floating-point number and the second floating-point number. The mantissa is expanded by digits. Such as the multiplier of claim 1, wherein the floating-point number further includes a sign, and the multiplier further includes: The sign processing unit is used to obtain the sign after the multiplication operation according to the sign of the two floating-point numbers. For example, the multiplier of claim 29, wherein the sign processing unit includes an exclusive OR logic circuit, and the exclusive OR logic circuit is used to perform an exclusive OR operation according to the signs of the two floating-point numbers to obtain the multiplication operation symbol. For example, the multiplier of claim 25 further includes a regularization unit for: Perform floating-point regularization processing on the mantissa and exponent after the multiplication operation to obtain a regularized exponent result and a regularized mantissa result, and use the regularized exponent result and the regularized mantissa result as the multiplication operation After the exponent and the mantissa after the multiplication operation. For example, the multiplier of claim 31 further includes: The rounding unit is configured to perform a rounding operation on the regularized mantissa result according to a rounding mode to obtain a rounded mantissa, and use the rounded mantissa as the mantissa after the multiplication operation. A method of using a multiplier to perform floating-point number multiplication, where, Using the mantissa processing unit of the multiplier to obtain the mantissa after the multiplication operation according to the mantissa of the floating-point number, The mantissa processing unit includes a control circuit configured to call the mantissa multiple times when the bit width of at least one of the two floating-point numbers is greater than the data bit width that can be processed by the mantissa processing unit at one time Processing unit. An integrated circuit chip comprising the multiplier described in any one of claim items 1 to 32. A computing device, comprising the multiplier described in any one of claim items 1-32 or the integrated circuit chip described in claim 34.

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