TWI763079B - Multiplier and method for floating-point arithmetic, integrated circuit chip, and computing device - Google Patents

Abstract

The present invention relates to a multiplier and a method for floating-point arithmetic, an integrated circuit chip, and a computing device. The computing device can be included in a combination processing device. The combination processing device may also include a universal interconnection interface and other processing device(s). The computing device interacts with the other processing device(s) to together accomplish an arithmetic operation prescribed by a user. The combination processing device may also include a storage device. The storage device is connected to the computing device and the other processing device(s) and used for data of the computing device and the other processing device(s). Schemes of the present invention can be widely applied to various floating-point data arithmetic operations.

Description

Multiplier, method, integrated circuit chip, and computing device for floating-point operations

The present disclosure relates to the technical field of floating-point operations, and more particularly, to a method, a multiplier, an integrated circuit chip, and a computing device for floating-point operations.

In various current signal processing algorithms, such as the inner product operation between vectors and the convolution operation of matrices, a large number of multiplication and addition operations are used, and the efficiency of these multiplication and addition operations often depends on the execution speed of the multiplier. Although the current multipliers have achieved significant improvements in execution efficiency, there is still room for improvement in handling floating-point type data. Therefore, how to obtain a multiplier with high efficiency, low power consumption and low cost to perform the multiplication operation of floating-point data becomes a problem to be solved in the prior art.

In order to at least partially solve the technical problems mentioned in the prior art, the solutions of the present disclosure provide a multiplier for floating-point operations, a method, an integrated circuit chip including the multiplier, and a computing device.

In one aspect, the present disclosure provides a multiplier for performing a multiplication operation of floating-point numbers, wherein the multiplier includes: a mantissa processing unit for obtaining the multiplication operation according to the mantissa of the floating-point number After the mantissa, the mantissa processing unit includes a control circuit, and the control circuit is used for multiple times when the mantissa bit width of at least one of the two floating-point numbers is larger than the data bit width that the mantissa processing unit can process at one time. The mantissa processing unit is called.

In another aspect, the present disclosure provides a method for performing a floating-point multiplication operation using a multiplier, wherein the multiplied mantissa is obtained according to the mantissa of the floating-point number using a mantissa processing unit of the multiplier , the mantissa processing unit includes a control circuit, the control circuit is configured to call the Mantissa processing unit.

In yet another aspect, the present disclosure provides an integrated circuit chip including the multiplier. In one or more embodiments, the multipliers of the present disclosure may constitute a separate IC chip or be disposed on an IC chip or computing device to perform operations on floating-point numbers in a variety of different data formats.

Using the multipliers, corresponding operation methods, integrated circuit chips, and computing devices of the present disclosure, operations on multiple floating-point type data can be supported without providing multiple separate multipliers for different floating-point type data. Therefore, the multiplier of the present disclosure is flexible in application, and can be widely used in various floating-point data operations. In addition, when processing input data with a larger bit width, the multiplier of the present disclosure supports loop multiplexing operations, so that more processing wafers need not be arranged, thereby reducing the layout area of the integrated circuit.

The technical solutions of the present disclosure generally provide a multiplier, method, integrated circuit chip, and computing device for floating-point number operations. Different from the floating-point operation multiplier of the prior art, the present disclosure provides a multiplier that supports multiple operation modes, thereby overcoming the defect that the conventional multiplier can only support one type of floating-point operation. In particular, the present disclosure utilizes multiple operation modes to indicate different floating-point data types, and during multiplication of floating-point numbers, various operations on the data are performed based on one of the operation modes, including, for example, encoding, compressing, summing , normalization, and rounding operations to implement operations associated with one of several floating-point data types. Thus, the multiplier of the present disclosure can support operations in multiple modes, further improving the flexibility of floating-point operations and reducing the cost of operations.

The technical solution of the present disclosure and its multiple embodiments will be described in detail below with reference to the accompanying drawings. It should be understood that numerous specific details will be set forth with regard to floating point operations in order to provide a thorough understanding of the various embodiments of the present disclosure. However, one of ordinary skill in the art, given the teachings of this disclosure, may practice the various embodiments described in this disclosure without these specific details. In other instances, the disclosure has not described well-known methods, procedures and elements in detail in order to avoid unnecessarily obscuring the embodiments described in this disclosure. Additionally, this description should not be construed as limiting the scope of the various embodiments of the present disclosure.

FIG. 1 is a schematic diagram illustrating a floating point data format 100 according to an embodiment of the present disclosure. As shown in Figure 1, a floating-point number to which the technical solution of the present disclosure can be applied may include three parts, such as sign (or sign bit 102), exponent (or exponent bit 104) and mantissa (or mantissa bit 106), wherein For unsigned floating point numbers there may be no sign or sign bit. In some embodiments, floating-point numbers suitable for use in the multipliers of the present disclosure may include at least half-precision floating-point numbers, single-precision floating-point numbers, brain floating-point numbers, double-precision floating-point numbers, custom floating-point numbers A sort of. Specifically, in some embodiments, the floating-point number format to which the technical solutions of the present disclosure can be applied may be a floating-point number format conforming to the IEEE754 standard, such as double-precision floating-point number (float64, abbreviated as "FP64"), single-precision floating-point number A floating point number (float32, abbreviated "FP32") or a half-precision floating point number (float16, abbreviated "FP16"). In other embodiments, the floating-point number format may also be an existing 16-bit brain floating-point number (bfloat16, abbreviated as "BF16"), or a custom floating-point number format, such as an 8-bit brain floating-point number ( bfloat8, abbreviated "BF8"), unsigned half-precision floating point number (unsigned float16, abbreviated "UFP16"), unsigned 16-bit brain floating point number (unsigned bfloat16, abbreviated "UBF16"). For ease of understanding, the following Table 1 shows some of the above-mentioned data formats, wherein the sign bit width, the exponent bit width and the mantissa bit width are only used for exemplary illustration purposes. Table 1 data type symbol width Exponential bit width mantissa bit width FP16 1 5 10 BF16 1 8 7 FP32 1 8 twenty three BF8 1 5 3 UFP16 0 5 (or 6) 11 (or 10) UBF16 0 8 8

For the various floating-point number formats mentioned above, the multiplier of the present disclosure can at least support the multiplication operation between two floating-point numbers in any of the above-mentioned formats, wherein the two floating-point numbers can have the same or Different floating point data formats. For example, a multiply operation between two floating point numbers can be FP16*FP16, BF16*BF16, FP32*FP32, FP32*BF16, FP16*BF16, FP32*FP16, BF8*BF16, UBF16*UFP16, or UBF16*FP16 Equal multiplication operation between two floating point numbers.

FIG. 2 is a block diagram illustrating a schematic structure of a multiplier 200 according to an embodiment of the present disclosure. As mentioned above, the multiplier of the present disclosure supports the multiplication of floating-point numbers in various data formats, and these data formats can be indicated by the operation mode of the present disclosure, so that the multiplier operates in one of the various operation modes.

As shown in Figure 2, the multiplier of the present disclosure may generally include an exponent processing unit 202 for processing the exponent bits of a floating point number and a mantissa processing unit 204 for processing the floating point The mantissa digits of the number. Alternatively or additionally, in some embodiments, when the floating point number processed by the multiplier has a sign bit, the multiplier may further include a sign processing unit 206, which may be used to process the floating point number including the sign bit. number.

In operation, the multiplier may perform floating-point operations on received, input or buffered first and second floating-point numbers according to one of the operation modes, the first and second floating-point numbers having One of the floating point data formats as discussed earlier. For example, when the multiplier is in the first operation mode, it can support the multiplication of two floating-point numbers FP16*FP16, and when the multiplier is in the second operation mode, it can support the multiplication of two floating-point numbers BF16*BF16 Multiplication operation. Similarly, when the multiplier is in the third operation mode, it can support the multiplication of two floating-point numbers FP32*FP32, and when the multiplier is in the fourth operation mode, it can support two floating-point numbers FP32*BF16 the multiplication operation. Here, the corresponding relationship between the operation mode of the example and the floating point number is shown in Table 2 below. Table 2 Operation mode number Operation floating point type 1 FP16*FP16 2 BF16*BF16 3 FP32*FP32 4 FP32*BF16

In one embodiment, the above-mentioned table 2 may be stored in a memory of the multiplier, and the multiplier selects one of the operation modes in the table according to an instruction received from an external device, and the external device may be, for example, the tenth External device 1012 shown in the figure. In another embodiment, the input of the operation mode can also be realized automatically via the mode selection unit 308 as shown in FIG. 3 . For example, when two FP16 floating-point numbers are input to the multiplier of the present disclosure, the mode selection unit can select the multiplier to operate in the first operation mode according to the data formats of the two floating-point numbers. For another example, when an FP32 type floating point number and a BF16 type floating point number are input to the multiplier of the present disclosure, the mode selection unit can select the multiplier to work in the fourth operation mode according to the data format of the two floating point numbers. middle.

It can be seen that the different operation modes of the present disclosure are associated with corresponding floating point data. That is, the operation mode of the present disclosure can be used to indicate the data format of the first floating point number and the data format of the second floating point number. In another embodiment, the operation mode of the present disclosure can not only indicate the data format of the first floating-point number and the data format of the second floating-point number, but also can be used to indicate the data format after the multiplication operation. The operation modes extended in conjunction with Table 2 are shown in Table 3 below. table 3 Operation mode number Operation floating point type output result type 11 FP16*FP16 FP16 12 BF16 13 FP32 twenty one BF16*BF16 FP16 twenty two BF16 twenty three FP32 31 FP32*FP32 FP16 32 BF16 33 FP32 41 FP32*BF16 FP16 42 BF16 43 FP32

Different from the operation mode numbers shown in Table 2, the operation modes in Table 3 are extended by one bit to indicate the data format after the floating-point multiplication operation. For example, when the multiplier works in operation mode 21, it performs floating-point operations on the input two floating-point numbers, BF16*BF16, and outputs the floating-point multiplication in the FP16 data format.

The above numbered operation modes to indicate floating point data formats are merely exemplary and non-limiting, and in accordance with the teachings of the present disclosure, it is also conceivable to index according to the operation modes to determine the format of the multiplier and multiplicand. For example, the operation mode includes two indexes, the first index is used to indicate the type of the first floating point number, and the second index is used to indicate the type of the second floating point number, for example, the first index "1" in operation mode 13 "indicates that the first floating-point number (or multiplicand) is in the first floating-point format, namely FP16, and the second index "3" indicates that the second floating-point number (or multiplier) is in the second floating-point format, Namely FP32. Further, a third index can also be added to the operation mode, the third index indicates the data format of the output result, for example, for the third index "1" in the operation mode 131, it can indicate that the data format of the output result is the first floating point format, i.e. FP16. When the number of operation modes increases, corresponding indexes or levels of indexes can be added as required, so as to facilitate the establishment of the relationship between operation modes and data formats.

In addition, although the operation mode is exemplarily referred to by number numbers, in other examples, the operation mode can also be referred to by other symbols or codes according to application requirements, such as letters, symbols or numbers and their Combining, etc., and expressing through such letters, numbers, symbols, or combinations thereof, refer to the operation mode and identify the first floating point number, the second floating point number, and the data format of the output result. In addition, when these expressions are formed in the form of an instruction, the instruction may include three fields or fields, the first field for indicating the data format of the first floating point number and the second field for indicating the data of the second floating point number format, and the third field is used to indicate the data format of the output result. Of course, these fields can also be combined into one field, or new fields can be added to indicate more content related to the floating-point data format. It can be seen that the operation mode of the present disclosure can not only be associated with the input floating point data format, but also can be used to normalize the output result to obtain the product result in the desired data format.

FIG. 3 is a block diagram illustrating a more detailed structure of the multiplier 300 according to an embodiment of the present disclosure. As can be seen from the content shown in Figure 3, it not only includes the exponent processing unit 202, the mantissa processing unit 204 and the optional sign processing unit 206 shown in Figure 2, but also shows the internal elements that these units may include As well as the units related to the operations of these units, exemplary operations of these units will be described in detail below with reference to FIG. 3 .

In order to perform the multiplication operation of the floating point number, the exponent processing unit may be configured to obtain the exponent after the multiplication operation according to the aforementioned operation mode, the exponent of the first floating point number and the exponent of the second floating point number. In one embodiment, the exponent processing unit may be implemented by an addition and subtraction circuit. For example, the exponent processing unit here may be used to add the exponent of the first floating point number, the exponent of the second floating point number, and the respective offset values of the input floating point data format, and then subtract the output floating point value The offset value of the data format to obtain the exponent of the multiplication of the first floating point number and the second floating point number.

Further, the mantissa processing unit of the multiplier may be configured to obtain the mantissa after the multiplication operation according to the aforementioned operation mode, the first floating point number and the second floating point number. In one embodiment, the mantissa processing unit may include a partial product operation unit 312 and a partial product summation unit 314, wherein the partial product operation unit is used to obtain the mantissa of the first floating point number and the mantissa of the second floating point number Intermediate results. In some embodiments, the intermediate result may be a plurality of partial products obtained during the multiplication operation of the first floating-point number and the second floating-point number (as schematically shown in FIGS. 5 and 6 ). of). The partial product summation unit is configured to perform an addition operation on the intermediate results to obtain an addition result, and use the addition result as the mantissa after the multiplication operation.

In order to obtain an intermediate result, in one embodiment, the present disclosure utilizes a Booth (“Booth”) encoding circuit to fill the high and low bits of the mantissa of the second floating-point number (eg, serving as a multiplier in a floating-point operation) with zeros (wherein The high-order 0-fill is to convert the mantissa as an unsigned number to a signed number) in order to obtain the intermediate result. It should be understood that, depending on the encoding method, the mantissa of the first floating-point number (for example, serving as the multiplicand in floating-point operations) can also be encoded (for example, the high and low bits are filled with 0), or both are encoded. , to obtain multiple partial products. More descriptions about the partial product will be explained later in conjunction with the accompanying drawings.

In another embodiment, the partial product summation unit may include an adder for summing the intermediate results to obtain the summation result. In yet another embodiment, the partial product summation unit includes a Wallace tree and an adder, wherein the Wallace tree is used to add the intermediate results to obtain a second intermediate result, and the adder uses and summing the second intermediate result to obtain the summation result. In these embodiments, the adder may include at least one of a full adder, a tandem adder, and a carry-lookahead adder.

In one embodiment, the multiplier of the present disclosure further includes a regularization unit 318 and a rounding unit 320 . The regularization unit can be used to perform floating point regularization processing on the mantissa and exponent after the multiplication operation, so as to obtain a regularized exponent result and a regularized mantissa result, and combine the regularized exponent result and the regularized mantissa result as the exponent after the multiplication operation and the mantissa after the multiplication operation. For example, according to the data format indicated by the operation mode, the regularization unit can adjust the bit widths of the exponent and the mantissa to make them meet the requirements of the data format indicated above. In addition, the regularization unit can also make other adjustments to the exponent or mantissa. For example, in some application scenarios, when the value of the mantissa is not 0, the most significant bit of the mantissa bit should be 1; otherwise, the exponent bit can be modified and the mantissa bit can be shifted at the same time to make it normalized. form. In another embodiment, the regularization unit may further adjust the exponent after the multiplication operation according to the mantissa after the multiplication operation. For example, when the highest bit of the mantissa after the multiplication operation is 1, the exponent obtained after the multiplication operation can be increased by 1. Correspondingly, the rounding unit may be configured to perform a rounding operation on the result of the regularized mantissa according to a rounding mode, and use the mantissa after performing the rounding operation as the mantissa after the multiplication operation. According to different application scenarios, the rounding unit may perform rounding operations including rounding down, rounding up, rounding to the nearest significant digit, and the like. In some application scenarios, the rounding unit can also round the 1 shifted out during the right shift of the mantissa.

In addition to the exponent processing unit and the mantissa processing unit, the multiplier of the present disclosure may optionally include a sign processing unit, which can be used to The sign of the floating point number and the sign of the second floating point number obtain the sign after the multiplication operation. For example, in one embodiment, the sign processing unit may include an exclusive-OR logic circuit 322, the exclusive-OR logic circuit is configured to perform XOR according to the sign of the first floating-point number and the sign of the second floating-point number OR operation to obtain the symbol after the multiplication operation. In another embodiment, the symbol processing unit can also be implemented by a truth table or logical judgment.

In addition, in order to make the input or received first and second floating-point numbers conform to a specified format, in one embodiment, the multiplier of the present disclosure may further include a normalization processing unit 324 for when the first floating-point number is When the point number or the second floating point number is a denormalized non-zero floating point number, normalize the first floating point number or the second floating point number according to the operation mode to obtain the corresponding exponent and mantissa. For example, when the selected operation mode is the second operation mode shown in Table 2, and the input first and second floating-point numbers are FP16 type data, the normalization processing unit can be used to normalize the FP16 type data For BF16 type data, so that the multiplier operates in the second operation mode. In one or more embodiments, the normalization processing unit may also be used to preprocess the mantissas of normalized floating point numbers with implicit 1s and denormalized floating point numbers without implicit 1s (eg, Mantissa expansion) to facilitate subsequent mantissa processing unit operations. Based on the above description, it can be understood that the normalization processing unit 324 here and the aforementioned regularization unit 318 can also perform the same or similar operations in some embodiments, the difference is that the normalization processing unit 324 is for the input The floating-point data is normalized and the regularization unit 318 is regularized for the mantissa and exponent to be output.

The multiplier and its various embodiments of the present disclosure are described above in conjunction with FIG. 3 . Based on the above description, those skilled in the art can understand that the solution of the present disclosure obtains the multiplication result (including the exponent, the mantissa and the optional sign) through the execution of the multiplier. According to different application scenarios, for example, when the aforementioned regularization processing and rounding processing are not required, the result obtained by the mantissa processing unit and the exponent processing unit can be regarded as the final operation result. Further, when the aforementioned regularization processing and rounding processing are required, the exponent and mantissa obtained after the regularization processing and rounding processing can be regarded as the final operation result, or a part of the final operation result (when considering final symbol). Further, the solution of the present disclosure enables the multiplier to support the operation of floating-point numbers of different types or data formats through multiple operation modes, so as to realize the multiplexing of the multiplier, thereby saving the cost of chip design and the calculation cost. In addition, the multiplier of the present disclosure also supports the computation of high-bit-width floating-point numbers through the multiple-call mechanism. In view of the fact that in the floating-point multiplication operation, the multiplication operation of the mantissa (or the mantissa bits or the mantissa part) is very important to the performance of the whole floating-point operation, the mantissa operation of the present disclosure will be described below with reference to FIG. 4 .

Figure 4 is a schematic block diagram illustrating mantissa processing unit operations 400 in accordance with an embodiment of the present disclosure. As shown in FIG. 4 , the mantissa processing operations of the present disclosure may primarily involve two units, the partial product operation unit and the partial product summation unit discussed above in connection with FIG. 3 . In terms of operation timing, the mantissa processing operation can be roughly divided into the first stage and the second stage. In the first stage, the mantissa processing operation will obtain an intermediate result, and in the second stage, the mantissa processing operation will obtain the result from the addition. The mantissa result output by the device 408.

In an exemplary specific operation, the first floating point number and the second floating point number received by the multiplier may be divided into a plurality of parts, ie the aforementioned sign (optional), exponent and mantissa. Optionally, after normalization processing, the mantissa part of the two floating-point numbers will be input into the mantissa processing unit (such as the mantissa processing unit in Figure 2 or Figure 3), and specifically into the partial product. operation unit. As shown in Fig. 4, the present disclosure uses the Booth encoding circuit 402 to add 0s to the high and low bits of the mantissa of the second floating-point number (ie, the multiplier in the floating-point operation), and performs Booth encoding processing, so that the partial The intermediate result is obtained in the product generation circuit 404 . Of course, the first floating-point number and the second floating-point number here are only used for illustrative rather than restrictive purposes, so in some application scenarios, the first floating-point number may be a multiplier and the second floating-point number may be is the multiplicand. Accordingly, in some encoding processes, encoding operations may also be performed on floating-point numbers serving as multiplicands.

In order to better understand the technical solutions of the present disclosure, the Booth coding is briefly introduced below. Generally, when two binary numbers are multiplied, a large number of intermediate results called partial products are generated through the multiplication operation, and then these partial products are accumulated to obtain the multiplication of the two binary numbers. Final result. The larger the number of partial products, the larger the area and power consumption of the array multiplier will be, the slower the execution speed will be, and the more difficult it will be to implement the circuit. The purpose of Booth coding is to effectively reduce the number of summation terms of partial products, thereby reducing the circuit area. Its algorithm is to first encode the corresponding rules for the input multipliers. In one embodiment, the encoding rules can be, for example, the rules shown in Table 4 below: Table 4 data to be encoded encoded signal y _2i+1 y _2i y _2i-1 PPi 0 0 0 0 0 0 1 X 0 1 0 X 0 1 1 2X 1 0 0 -2X 1 0 1 - X 1 1 0 - X 1 1 1 -0(=0)

”，則可以獲得下述的部分積：Wherein y _2i+1 , y _2i and y _2i-1 in Table 4 can represent the values corresponding to each group of sub-data to be encoded (ie multiplier), and X can represent the first floating point number (ie multiplicand) the mantissa. After each group of corresponding data to be encoded is subjected to Booth encoding, a corresponding encoded signal PPi (i=0, 1, 2, . . . , n) is obtained. As schematically shown in Table 4, the encoded signal obtained after Booth encoding may include five types, namely -2X, 2X, -X, X and 0, respectively. Exemplarily, based on the above encoding rules, if the received multiplicand is 8-bit data "

”, the following partial product can be obtained:

”，第9位是符號位，即

；1) When the multiplier digit includes the continuous three data "001" in the above table, the partial product is X, which can be expressed as "

", the 9th bit is the sign bit, that is

;

0”，即

；2) When the multiplier bits include the consecutive three-digit data "011" in the above table, the partial product is 2X, which can be expressed as X shifted to the left by one place to get "

0", i.e.

;

”，表示對“

”按位取反再加1，即

；3) When the multiplier bits include the consecutive three data "101" in the above table, the partial product is -X, which can be expressed as "

, indicating that "

"Invert the bit and add 1, i.e.

;

，表示對“

”左移一位後取反再加1，即

+1；4) When the multiplier bits include the three consecutive data "100" in the above table, the partial product is -2X, which can be expressed as

, indicating that "

"Shift one bit to the left, invert and add 1, that is

+1;

。5) When the multiplier bits include the consecutive three data "111" or "000" in the above table, the partial product is 0, that is

.

It should be understood that the above description of the process of obtaining the partial product in conjunction with Table 4 is only exemplary and not restrictive, and those with ordinary knowledge in the art can make changes to the rules in Table 4 under the teaching of the present disclosure, to obtain partial products other than those shown in Table 4. For example, when there is a specific number of consecutive multiple digits (such as 3 digits or more) in the multiplier digits, the obtained partial product can be the complement of the multiplicand, or the above-mentioned partial product can be added after adding the partial product. "Add 1" operation in items 3) and 4).

As can be understood from the above introductory description, by encoding the mantissa of the second floating-point number using the Booth encoding circuit, and using the mantissa of the first floating-point number, a plurality of partial products can be generated from the partial product generating circuit as intermediate results, And the intermediate result is fed into a Wallace Tree ("Wallace Tree") compressor 406 in the partial product summation unit. It should be understood that the use of Booth coding to obtain the partial product here is only a preferred way of obtaining the partial product in the present disclosure, and those with ordinary knowledge in the art can also obtain the partial product in other ways. For example, it can also be obtained by a shift operation, that is, according to whether the bit value of the multiplier is 1 or 0, the corresponding partial product is obtained by selecting the shift plus the multiplicand or the plus 0. Similarly, the use of the Wallace tree compressor to realize the addition operation of the partial product is only exemplary and non-limiting, and those with ordinary knowledge in the art can also think of using other types of adders to realize such partial products. Addition operation. The adder may be, for example, one or more full adders, half adders, or various combinations of the two.

Regarding the Wallace Tree Compressor (or simply Wallace Tree), it is mainly used to sum the above-mentioned intermediate results (ie, multiple partial products) to reduce the number of accumulations (ie, compression) of the partial products. Generally, a Wallace tree compressor can adopt a carry-save CAS (carry-save) architecture and a Wallace tree algorithm, which utilizes a Wallace tree array to compute much faster than traditional carry-pass addition.

Specifically, the Wallace tree compressor can calculate the sum of the partial products of each row in parallel, for example, the accumulation times of N partial products can be reduced from N-1 times to Log ₂ N times, thereby improving the speed of the multiplier and saving resources. effective use is of great significance. According to different application needs, the Wallace tree compressor can be designed into various types, such as 7-2 Wallace tree, 4-2 Wallace tree and 3-2 Wallace tree, etc. In one or more embodiments, the present disclosure uses a 7-2 Wallace tree as an example of implementing the various floating point operations of the present disclosure, which will be described in detail later in conjunction with FIGS. 5 and 6 .

In some embodiments, the Wallace tree compression operation disclosed in the present disclosure may be arranged to have M inputs and N outputs, the number of which may not be less than K, where N is a preset positive integer smaller than M, and K is A positive integer not less than the maximum bit width of the intermediate result. For example, M could be 7 and N could be 2, a 7-2 Wallace tree as described in detail below. When the maximum bit width of the intermediate result is 48, K can take a positive integer of 48, that is to say, the number of Wallace trees can be 48.

In some embodiments, according to the operation mode, one or more groups of the Wallace trees may be selected to add the intermediate results, wherein each group has X Wallace trees, and X is the sum of the intermediate results. digits. Further, there may be a sequential carry relationship between the Wallace trees in each group, but there is no carry relationship between each group. In an exemplary connection, the Wallace Tree Compressor may be connected via carry, such as the carry output from the lower Wallace Tree Compressor (such as Cin in Figure 6) to the upper Wallace Tree, and the upper Wallace Tree Compressor The carry output (Cout) of the Race tree compressor can in turn become a higher order Wallace tree compressor receiving the carry input from the lower order Wallace tree compressor. In addition, when selecting one or more Wallace tree compressors from multiple Wallace tree compressors, any selection can be made, such as either in the order of numbers 0, 1, 2, and 3, or 0 , 2, 4 and 6 are connected in the order of numbering, as long as the selected Wallace tree compressor is selected according to the above-mentioned carry relationship.

The above Wallace tree and its operations are described below in conjunction with an illustrative example. Assuming that the first floating point number and the second floating point number are 16-bit data (such as FP16*FP16), the data bit width supported by the multiplier is 32 bits (thereby supporting two sets of 16-bit parallel multiplication operations), A Wallace tree is a 7-2 Wallace tree compressor with 7 (ie an example value of M above) inputs and 2 (ie an example value of N above) outputs. In this example scenario, 48 Wallace trees (that is, an example value of K above) can be used to complete the multiplication operation of the two sets of data in parallel.

Among the above 48 Wallace trees, the 0th to 23rd Wallace trees (that is, 24 Wallace trees in the first group of Wallace trees) can complete the partial product addition and operation of the first group of multiplications , and each Wallace tree in the group can be sequentially connected by carry. Further, the 24th to 47th Wallace trees (that is, 24 Wallace trees in the second group of Wallace trees) can complete the partial product addition and sum operation of the second group of multiplications, wherein each Wallace tree in this group The trees are in turn connected by carry. In addition, there is no carry relationship between the 23rd Wallace tree in the first group and the 24th Wallace tree in the second group, that is, there is no carry relationship between different groups of Wallace trees.

Returning to Figure 4, after adding and compressing the partial products through the Wallace tree compressor, the compressed partial products are summed through the adder to obtain the result of the mantissa multiplication operation. Regarding the adder, in one or more embodiments of the present disclosure, it may include one of a full adder, a tandem adder, and a carry-lookahead adder for summing the Wallace tree compressor. The resulting last two rows of partial products are summed to obtain the result of the mantissa multiplication operation.

It will be appreciated that the result of the mantissa multiplication operation can be efficiently obtained by the mantissa multiplication operation shown in FIG. 4, in particular using Booth coding and Wallace tree exemplarily. Specifically, the Booth coding process can effectively reduce the number of partial product summation terms, thereby reducing the circuit area, while the Wallace compressed tree can calculate the sum of partial products of each row in parallel, thereby increasing the speed of the multiplier.

An example operation process of the partial product sum 7-2 Wallace tree will be described in detail below with reference to Figures 5 and 6. It is to be understood that the description herein is merely exemplary and not restrictive, and is only for a better understanding of the present disclosure.

Fig. 5 shows the partial product 500 obtained after passing through the partial product generating circuit in the mantissa processing unit described above in conjunction with Fig. 2-Fig. 4, as shown in the figure, there are four rows of white dots between the two dotted lines in the figure , where each row of white dots identifies a partial product. To facilitate subsequent Wallace tree compressor implementation, the number of bits may be expanded in advance. For example, the black dot in Figure 5 is the highest value of each 9-bit partial product copied, it can be seen that the partial product is extended and aligned to 16(8+8)bit (that is, the bit width of the multiplicand mantissa is 8bit+ The bit width of the mantissa of the multiplier is 8 bits). In another embodiment, for example, for the partial product of 25*13 binary multiplication, the partial product is extended to 38(25+13) bits (that is, the bit width of the multiplicand mantissa is 25 bits + the bit width of the multiplier mantissa is 13 bits. ).

FIG. 6 is a schematic block diagram 600 illustrating an operational flow and a schematic block diagram 600 of a Wallace tree compressor according to an embodiment of the present disclosure.

As shown in Figure 6, after performing a multiplication operation on the mantissas of two floating-point numbers, for example, as previously described, by Booth-coding the multiplier and passing the multiplicand as shown in Figure 6 out of the 7 partial products. Due to the use of the Booth coding algorithm, the number of partial products generated is reduced. For ease of understanding, a Wallace tree including 7 elements is marked with a dashed box in the partial product part in the figure, and the process of compressing it from 7 elements to 2 elements is further shown with arrows. In one embodiment, the compression process (or the summation process) can be implemented by means of a full adder, that is, three elements are input and two elements are output (ie, a sum "sum" and a carry to the high order "carry") . The schematic block diagram of the 7-2 Wallace tree compressor is shown on the right side of Figure 6, it can be understood that the Wallace tree compressor includes 7 inputs from a column of partial products (as identified in the dashed box on the left side of Figure 6). seven elements). In operation, the carry input of the 0th column of Wallace trees is 0, and the carry output Cout of each column of Wallace trees is used as the carry input Cin of the next column of Wallace trees.

As you can see from the left part of Figure 6, a Wallace tree with 7 elements can be compressed to include 2 elements after four compressions. As mentioned earlier, the present disclosure utilizes a 7-2 Wallace tree compressor to finally compress a partial product of 7 rows into a partial product with two rows (ie, the second intermediate result of the present disclosure), and utilizes an adder (eg, carry lookahead adder) to get the mantissa result.

In order to further illustrate the principle of the disclosed solution, the following will exemplarily describe how the multiplier of the present disclosure completes the operations in the first stage under the four operation modes of FP16*FP16, FP16*FP16, FP32*FP32 and FP32*BF16, namely, Until the Wallace tree compressor finishes summing the intermediate results to get the second intermediate result:

(1)FP16*FP16

In this operation mode of the multiplier, the mantissa of the floating-point number is 10 bits. Considering the denormalized non-zero number under the IEEE754 standard, it can be extended by 1 bit, so that the mantissa is 11 bits. In addition, since the mantissa bits are unsigned numbers, 1-bit 0 can be extended in the high order when using Booth coding algorithm, so the total number of mantissa digits is 12 bits. When Booth coding is performed on the multiplier as the second floating-point number, and the first floating-point number is referred to, 7 partial products can be obtained in the high and low parts respectively through the partial product generating circuit, and the seventh partial product is 0 , the bit width of each partial product is 24 bits, at this time, 48 7-2 Wallace trees can be used for compression, and the carry from the 23rd to 24th Wallace trees is 0.

(2)BF16*BF16

In this operation mode of the multiplier, the mantissa of the floating-point number is 7 bits. Considering the denormalized non-zero number and extension to a signed number under the IEEE754 standard, the mantissa can be extended to 9 bits. When Booth coding is performed on the multiplier as the second floating-point number, and the first floating-point number is referred to, then 7 effective partial products can be obtained respectively in the high and low parts through the partial product generating circuit, among which the sixth and seventh parts are The product is 0, and the bit width of each partial product is 18bit. It is compressed by using the 0~17th and 24th~41st two groups of 7-2 Wallace trees, of which the 23rd to 24th Wallace trees The tree has a carry of 0.

(3)FP32*FP32

In this operation mode of the multiplier, the mantissa of the floating-point number can be 23 bits. Considering the denormalized non-zero number and the extension to a signed number under the IEEE754 standard, the mantissa can be extended to 25 bits. To save the area of the multiplication unit, for example, the bit width supported by the multiplier can be designed to be smaller, and the multiplier of the present disclosure can be called twice in this operation mode to complete one operation. For this reason, the multiplication of each mantissa bit is 25bit*13bit, that is, the first floating-point number ina is expanded by 1 bit 0 to become a 25-bit signed number, and the 24-bit mantissa of the second floating-point number inb is divided into two parts, high and low, 12 bits respectively. Extend 1 bit 0 to get two 13bit multipliers, which are expressed as inb_high13 and inb_low13 high and low parts. In the specific operation, the multiplier of the present disclosure is called for the first time to calculate ina*inb_low13, and the multiplier is called for the second time to calculate ina*inb_high13. In each calculation, 7 effective partial products are generated by Booth coding, and the bit width of each partial product is 38 bits, which is compressed by the 0~37th 7-2 Wallace tree.

(4)FP32*BF16

In this operation mode of the multiplier, the mantissa bits of the first floating-point number ina are 23 bits, and the mantissa bits of the second floating-point number inb are 7 bits. Considering the denormalized non-zero number and extension to a signed number under the IEEE754 standard , then the mantissa can be expanded to 25bit and 9bit respectively, multiplication of 25bit×9bit is performed, and 7 effective partial products are obtained, of which the 6th and 7th partial products are 0, and the bit width of each partial product is 34bit. 33 Wallace trees for compression.

The above describes how the multiplier of the present disclosure completes the operation of the first stage in four operation modes through specific examples, among which the Booth coding algorithm and the 7-2 Wallace tree are preferably used. Based on the above description, those skilled in the art can understand that the present disclosure uses 7 partial products, so that the 7-2 Wallace tree can be reused in different operation modes.

The case where the multipliers (mantissa processing unit and exponent processing unit) of the present disclosure are called multiple times will be described in more detail below.

According to another aspect of the present disclosure, as shown in FIG. 3, the mantissa processing unit may include a control circuit 316, and the control circuit 316 may be used for at least one of the two floating point numbers whose mantissa is wider than the mantissa. When the processing unit can process the data bit width at a time, the mantissa processing unit is called multiple times. The data bit width that the mantissa processing unit can process at one time refers to two bit widths (eg, the multiplier bit width and the multiplicand bit width) supported by the mantissa processing unit. Therefore, it can be understood that the control circuit is configured to operate according to the mantissa bit width of one of the two floating-point numbers and one of the two bit widths supported by the mantissa processing unit, or according to the two floating-point numbers. The mantissa bit width of the point number and the two bit widths supported by the mantissa processing unit determine that the mantissa processing unit is called multiple times to obtain the mantissa after the multiplication operation. Therefore, this repeated invocation of the mantissa processing unit in the multiplier avoids arranging large-area multiplier components to handle large-bit-wide mantissa operations and avoids arranging small-area multiplier components that cannot handle large-bit-wide mantissa operations, resulting in The applicability is stronger and the wafer area is reduced.

According to the first embodiment of the present disclosure, the two floating point numbers include a first floating point number and a second floating point number, the mantissa processing unit supports a first bit width and a second bit width, the first floating point number The mantissa of the point number is used as the first input corresponding to the first bit width, the mantissa of the second floating point number is used as the second input corresponding to the second bit width, and the bit width of the first input is less than or equal to the first bit width, the control circuit is configured to call the mantissa processing unit multiple times to obtain the mantissa after the multiplication operation when the bit width of the second input is greater than the second bit width . According to this embodiment, it is known that the bit width of one of the two inputs is fixed less than or equal to the one supported by the corresponding mantissa processing unit. Therefore, it is only necessary to determine whether the other input is supported by the corresponding mantissa processing unit. The size relationship of the bit width can determine whether to call the mantissa processing unit multiple times.

According to the second embodiment of the present disclosure, the two floating point numbers include a first floating point number and a second floating point number, the mantissa processing unit supports a first bit width and a second bit width, the first floating point number The mantissa of the point number is used as the first input corresponding to the first bit width, the mantissa of the second floating point number is used as the second input corresponding to the second bit width, and the control circuit is used for when the When the bit width of the first input is greater than the first bit width and the bit width of the second input is less than or equal to the second bit width, when the bit width of the second input is greater than the second bit width and When the bit width of the first input is less than or equal to the first bit width or when the bit width of the first input is greater than the first bit width and the bit width of the second input is greater than the second bit width When wide, the mantissa processing unit is called multiple times to obtain the mantissa after the multiplication operation. According to this embodiment, the size relationship between the bit widths of the two inputs and the two bit widths supported by the mantissa processing unit is uncertain, and it is necessary to determine the size relationship between the two inputs and the bit widths supported by the corresponding mantissa processing units to determine Whether to call the mantissa processing unit multiple times.

According to this second embodiment, when the mantissa bit width of the first floating point number is smaller than the mantissa bit width of the second floating point number and the first bit width is larger than the second bit width, or when all the When the mantissa bit width of the first floating point number is greater than the mantissa bit width of the second floating point number and the first bit width is smaller than the second bit width, the control circuit selects the first floating point number The mantissa of is used as the second input corresponding to the second bit width and the mantissa of the second floating point number is selected as the first input corresponding to the first bit width. It should be understood that when the mantissas of two floating-point numbers are input irregularly, the mantissas of the two inputted floating-point numbers can be processed according to the strategy of large-bit width to large-bit width and small-bit width to small-bit width and the mantissa processing unit. The supported two-bit widths are matched to avoid multiple calls to the mantissa of two floating-point numbers that can be processed at one time.

Further, when the bit width of the first input is greater than the first bit width and the bit width of the second input is less than or equal to the second bit width, the control circuit will The bit width and the first bit width determine the number of times the mantissa processing unit is called and the data input to the mantissa processing unit in each call. When the bit width of the second input is greater than the second bit width and the bit width of the first input is less than or equal to the first The second bit width determines the number of calls to the mantissa processing unit and the data input to the mantissa processing unit in each call. When the bit width of the first input is larger than the first bit width and the bit width of the second input is larger than the second bit width, the control circuit can determine the The first bit width and the bit width of the second input and the second bit width determine the number of calls to the mantissa processing unit and the data input to the mantissa processing unit in each call.

In the present disclosure, the description about the first floating-point number and the second floating-point number is only for distinguishing the two floating-point numbers, wherein "first" and "second" have no limiting effect. Likewise, the description of the first and second bit widths is only to distinguish the two maximum processing bit widths supported by the mantissa processing unit, and the description of the first and second inputs is only to distinguish the mantissa processing unit The two inputs corresponding to the two maximum processing bit widths, so neither "first" nor "second" has a limiting effect.

It is worth noting that the floating-point numbers input to the multiplier described in the above embodiments are floating-point numbers that conform to the format required by the operation and are applicable to the internal and external components of the multiplier, that is, the floating-point numbers that have undergone preprocessing such as normalization. It should be understood that the floating-point number input to the multiplier may be a normalized or denormalized floating-point number. In combination with the above description of the normalization unit, it can be known that if at least one of the two input floating-point numbers is a non-normalized floating-point number For the normalized non-zero floating-point number, the at least one floating-point number may be normalized by a normalization unit to obtain a normalized exponent and a mantissa, and then the normalized mantissa may be used as the value of the mantissa processing unit. input to perform the floating-point multiplication operation described above. In addition, the Booth coding circuit mentioned earlier in this disclosure performs signed fixed-point multiplication calculation, so it is also necessary to extend 1-bit 0 in front of the mantissa, that is, to change the mantissa into a signed positive number, and then use the extended signed mantissa as the mantissa for processing The input of the unit is used to perform the floating-point multiplication operation described above. Of course, other preprocessing can also be performed on the floating-point number, and the mantissa of the pre-processed floating-point number is used as the input of the mantissa processing unit to perform the above-mentioned floating-point number multiplication operation. For example, in the above description of the normalization unit Regarding the normalization of floating-point numbers in order to apply the operation mode, the first and second embodiments of the present disclosure are also applicable to the above-mentioned operation of floating-point numbers according to the operation mode.

Three examples of calling the mantissa processing unit multiple times according to the above-described second embodiment of the present disclosure will be described in detail below. In order to understand these three examples more clearly and intuitively, the first input can be, for example, the multiplier, the second input can be, for example, the multiplicand, and the first bit width can be, for example, the maximum multiplier bit width supported by the mantissa processing unit, The two-bit width can be, for example, the maximum multiplicand bit-width supported by the mantissa processing unit.

According to the first example of the multi-call mantissa processing unit of the present disclosure, combined with the floating-point multiplication operation according to the operation mode described above, the two floating-point numbers input to the multiplier of the present disclosure are denormalized non-zero floating-point numbers. Taking points as an example, and combining with the Booth coding circuit used in the present disclosure to perform signed fixed-point multiplication, the two floating-point numbers are first normalized, so the mantissas of the two floating-point numbers are extended by 1 bit. In the Booth encoding circuit in the embodiment of the present disclosure, the two mantissas are further extended by 1 bit to form a signed number. After these preprocessing, the mantissa of the two floats is matched with the input of the mantissa processing unit. Therefore, when the bit width of the multiplier is greater than the maximum multiplier bit width and the bit width of the multiplicand is less than or equal to the maximum multiplicand, the control circuit only normalizes the original mantissa corresponding to the multiplier as the mantissa to be formed. The mantissa is truncated, and in order to be suitable for the Booth coding circuit in the embodiment of the present disclosure, the sign bit is extended for each truncated part. In order to enable the mantissa processing unit to process the mantissa to be truncated, the part with a bit width of A-1 is truncated from the mantissa to be truncated in each call, where A represents the maximum multiplier bit width supported by the mantissa processing unit. The truncated bit-width A-1 part is supplemented with a 0 in the upper bit as the sign to form a bit-width A multiplier part, which is used as an input to the mantissa processing unit in each call. In addition, the multiplicand (in this embodiment, the mantissa is the normalized and sign-extended mantissa) is entered into the mantissa processing unit as another input in each call. From this, the following formula can be used to determine the number of invocations of the mantissa processing unit:

n=ceil((B+1)/(A-1)),

Among them, n represents the number of calls to the mantissa processing unit, B represents the bit width of the unnormalized and unextended sign bit of the mantissa, B+1 represents the normalized bit width of the mantissa, and B+1 can also be understood as B+2 -1, that is, the bit width of the multiplier minus the bit width of the sign bit, A represents the bit width of the multiplier part (the maximum multiplier bit width supported by the mantissa processing unit), and A-1 represents the mantissa to be truncated in each call The bit width of the truncated portion in .

For example, the maximum multiplier bit width supported by the mantissa processing unit is, for example, 8 bits, and the maximum multiplicand bit width is, for example, 32 bits. The two floating-point numbers input to the multiplier are FP32 and BF16 floating-point numbers respectively. Therefore, choose The multiplication operation is performed in the FP32*BF16 operation mode, and the two floating-point numbers are denormalized non-zero numbers, so the mantissas of the two floating-point numbers have a bit width of 23bit and 7bit respectively. Considering the IEEE754 standard, the two mantissas are The bit width can be extended to 24bit and 8bit. In order to be applicable to the Booth coding circuit in the embodiment of the present disclosure, the two mantissas are further extended by 1 bit 0 to become signed numbers of 25 bits and 9 bits. Therefore, the control circuit takes the mantissa with a bit width of 9 bits as the multiplier corresponding to the maximum multiplier bit width and the mantissa with a bit width of 25 bits as the multiplicand corresponding to the maximum multiplicand bit width, since only the bit width of the multiplier (9 bits ) is larger than the maximum multiplier bit width (8bit), and the multiplicand’s bit width (25bit) is smaller than the maximum multiplicand bit width (32bit), so the original mantissa corresponding to the multiplier is only the mantissa formed after normalization as the to-be-truncated mantissa If the mantissa inb, the multiplicand is used as the multiplicand ina of the input mantissa processing unit. According to the above formula, ceil((7+1)/(8-1))=2, therefore, the mantissa processing unit needs to be called twice, and in each call, 7bit data is intercepted in inb each time, and the last call (the second call), if the data is less than 7bit, then all the remaining data will be intercepted and 0 is added in front to make up 7bit, and the intercepted 7bit data will be extended by 1 bit 0 (sign bit) to become 8bit as the multiplier part inb_m, Therefore, the calculation performed in each call is ina*inb_m, that is, the multiplication operation of the multiplicand with a bit width of 25 bits and the multiplier part with a bit width of 8 bits, so that the mantissa result obtained by this call can be calculated. It is worth noting that the truncation of the mantissa to be truncated can be performed in the order from the high order to the low order, or in the order from the low order to the high order. It is worth noting that this example is also applicable to the above-mentioned first embodiment of the present disclosure.

According to the second example of the multi-call mantissa processing unit of the present disclosure, combined with the floating-point multiplication operation according to the operation mode described above, the two floating-point numbers input to the multiplier of the present disclosure are denormalized non-zero floating-point numbers. Taking points as an example, and combining with the Booth coding circuit used in the present disclosure to perform signed fixed-point multiplication, the two floating-point numbers are first normalized, so the mantissas of the two floating-point numbers are extended by 1 bit. In the Booth encoding circuit in the embodiment of the present disclosure, the two mantissas are further extended by 1 bit to form a signed number. After these preprocessing, the mantissa of the two floats is matched with the input of the mantissa processing unit. Therefore, when the bit width of the multiplicand is greater than the maximum bit width of the multiplicand and the bit width of the multiplier is less than or equal to the maximum bit width of the multiplier, the control circuit only normalizes the original mantissa corresponding to the multiplicand and forms the mantissa. As the mantissa to be truncated, and in order to be suitable for the Booth coding circuit in the embodiment of the present disclosure, the sign bit is extended for each truncated part. In order to enable the mantissa processing unit to process the mantissa to be truncated, the part with a bit width of C-1 is truncated from the mantissa in each call, where C represents the maximum bit width of the multiplicand supported by the mantissa processing unit. The truncated part with a bit width of C-1 is supplemented with a 0 in the upper bit as a sign to form a multiplicand part with a bit width of C, which is used as an input to the mantissa processing unit in each call. In addition, the multiplier (in this embodiment, the multiplier is the normalized and sign-extended mantissa) is entered into the mantissa processing unit as another input in each call. From this, the following formula can be used to determine the number of invocations of the mantissa processing unit:

n=ceil((D+1)/(C-1)),

Among them, n represents the number of times the mantissa processing unit is called, D represents the bit width of the unnormalized and unextended sign bit of the mantissa, D+1 represents the normalized bit width of the mantissa, and D+1 can also be understood as D+2 -1, that is, the bit width of the multiplicand minus the bit width of the sign bit, C represents the bit width of the multiplicand part (the maximum multiplicand bit width supported by the mantissa processing unit), and C-1 represents the The bit width of the truncated part of the mantissa to be truncated.

For example, the maximum multiplier bit width supported by the mantissa processing unit is, for example, 12 bits, and the maximum multiplicand bit width is, for example, 16 bits. The two floating-point numbers input to the multiplier are FP32 type and BF16 type floating-point numbers respectively. Therefore, choose The multiplication operation is performed in the FP32*BF16 operation mode, and the two floating-point numbers are denormalized non-zero numbers, so the mantissas of the two floating-point numbers have a bit width of 23bit and 7bit respectively. Considering the IEEE754 standard, the two mantissas are The bit width can be extended to 24bit and 8bit. In order to be applicable to the Booth coding circuit in the embodiment of the present disclosure, the two mantissas are further extended by 1 bit 0 to become signed numbers of 25 bits and 9 bits. Therefore, the control circuit takes the mantissa with a bit width of 9 bits as the multiplier corresponding to the maximum multiplier bit width and the mantissa with a bit width of 25 bits as the multiplicand corresponding to the maximum multiplicand bit width, since only the bit width of the multiplicand ( 25bit) is larger than the maximum multiplicand bit width (16bit) supported by the mantissa processing unit, and the bit width of the multiplier (9bit) is smaller than the maximum multiplier bit width (12bit), so the original mantissa corresponding to the multiplicand is only normalized The mantissa formed later is used as the mantissa to be truncated ina, and the multiplier is used as the multiplier inb of the input mantissa processing unit. According to the above formula, ceil((23+1)/(16-1))=2, therefore, the mantissa processing unit needs to be called twice, and in each call, 15bit data is intercepted in ina, and the last call (the second call), if the data is less than 15bit, 0 is added in front to make up 15bit, and the 15bit data intercepted each time is expanded by 1 bit 0 (sign bit) to become 16bit as the multiplicand part ina_m, therefore, in each call The calculation performed at the time is ina_m*inb, that is, the multiplication operation of the multiplicand with a bit width of 16 bits and a multiplier with a bit width of 9 bits, so that the mantissa result obtained by this call can be calculated. It is worth noting that the truncation of the mantissa to be truncated can be performed in the order from the high order to the low order, or in the order from the low order to the high order. It is worth noting that this example is also applicable to the above-mentioned first embodiment of the present disclosure.

According to the third example of the multi-call mantissa processing unit of the present disclosure, combined with the floating-point multiplication operation according to the operation mode described above, the two floating-point numbers input to the multiplier of the present disclosure are denormalized non-zero floating-point numbers. Taking points as an example, and combining with the Booth coding circuit used in the present disclosure to perform signed fixed-point multiplication, the two floating-point numbers are first normalized, so the mantissas of the two floating-point numbers are extended by 1 bit. In the Booth encoding circuit in the embodiment of the present disclosure, the two mantissas are further extended by 1 bit to form a signed number. After these preprocessing, the mantissa of the two floats is matched with the input of the mantissa processing unit. Therefore, when the bit width of the multiplier is larger than the maximum multiplier bit width and the multiplicand (in this embodiment, the multiplicand is the mantissa of normalized and extended sign bits) is larger than the When the bit width of the multiplicand is the largest, the control circuit only takes the mantissa formed after normalization of the original mantissa corresponding to the multiplier and the mantissa formed only after the normalization of the original mantissa corresponding to the multiplicand as the mantissa to be truncated, and in order to apply In the Booth coding circuit in the embodiment of the present disclosure, the sign bit is extended for each truncated part. In order to enable the mantissa processing unit to process the two mantissas to be truncated, in each call, the part with a bit width of A-1 is truncated from the mantissa to be truncated corresponding to the multiplier, and the mantissa to be truncated corresponding to the multiplicand is truncated in each call. The truncated bit width is C-1, where A represents the maximum multiplier bit width supported by the mantissa processing unit, C represents the maximum multiplicand bit width supported by the mantissa processing unit, and the bit width for each interception is A- The part of 1 is supplemented with a 0 as a sign to form a multiplier part with a bit width of A. The multiplier part is used as an input to the mantissa processing unit in each call, and the bit width of each truncation is C- The part of 1 is supplemented with a 0 in the upper bit as the sign to form the multiplicand part of bit width C, which is used as another input to the mantissa processing unit in each call. From this, the following formula can be used to determine the number of invocations of the mantissa processing unit:

n=ceil((B+1)/(A-1))*ceil((D+1)/(C-1))

Among them, n represents the number of calls to the mantissa processing unit, B represents the bit width of the unnormalized and unextended sign bit of the mantissa, B+1 represents the normalized bit width of the mantissa, and B+1 can also be understood as B+2 -1, that is, the bit width of the multiplier minus the bit width of the sign bit, A represents the bit width of the multiplier part (the maximum multiplier bit width supported by the mantissa processing unit), and A-1 represents the sum of the multiplier in each call The corresponding bit width of the truncated part of the mantissa to be truncated, D represents the bit width of the unnormalized and unextended sign bit of the mantissa, D+1 represents the normalized bit width of the mantissa, D+1 can also be understood as D +2-1, that is, the bit width of the multiplicand minus the bit width of the sign bit, C represents the bit width of the multiplicand part (the maximum multiplicand bit width supported by the mantissa processing unit), and C-1 represents each call The bit width of the part truncated from the mantissa to be truncated.

For example, the maximum multiplier bit width supported by the mantissa processing unit is, for example, 8 bits, and the maximum multiplicand bit width is, for example, 16 bits. The multiplication operation is performed in the FP32 operation mode, and the two floating-point numbers are denormalized non-zero numbers, so the mantissa bit width of the two floating-point numbers is 23 bits. Considering the IEEE754 standard, the bit width of the two mantissas can be extended to 24 bits. . In order to be applicable to the Booth coding circuit in the embodiment of the present disclosure, the two mantissas are further extended by 1-bit 0 to become a 25-bit signed number. Therefore, the control circuit selects the mantissas of the two floating-point numbers as the multiplier corresponding to the maximum multiplier bit width and the multiplicand corresponding to the maximum multiplicand bit width (since the mantissas of the two floating-point numbers have the same bit width after expansion) , so choose one as the multiplier and the other as the multiplicand), since the bit width of the multiplier (25bit) is larger than the maximum multiplier bit width (8bit) and the bit width of the multiplicand (25bit) is larger than the maximum bit width of the multiplicand (16 bits), so the mantissa formed after normalizing the original mantissa corresponding to the multiplier is taken as the mantissa to be truncated inb and the mantissa formed after normalizing the original mantissa corresponding to the multiplicand is taken as the mantissa to be truncated. Truncate the mantissa ina. According to the above formula, ceil((23+1)/(8-1))* ceil((23+1)/(16-1))=8, therefore, the mantissa processing unit needs to be called eight times. In each call, 7bit data is intercepted in inb each time. When the last call is less than 7bit data, all remaining data are intercepted and 0 is added in front to make up 7bit, and the intercepted 7bit data is extended by 1 bit 0 each time. (sign bit) is 8 bits as the multiplier part inb_m, and since inb is cut into four parts, it can have four multiplier parts inb_m1, inb_m2, inb_m3, and inb_m4. In addition, in each call, 15bit data is intercepted in ina each time. When the last call is less than 15bit data, all the remaining data will be intercepted and filled with 0 in front to make up 15bit, and the 15bit data intercepted each time will be extended by 1 bit. 0 (sign bit) becomes 16 bits as the multiplicand part ina_m, and since ina is truncated into two parts, it is possible to have two multiplicand parts ina_m1 and ina_m2. Thus, for example, the following calculations can be performed in sequence with eight calls to the mantissa processing unit: ina_m1*inb_m1, ina_m1*inb_m2, ina_m1*inb_m3, ina_m1*inb_m4, ina_m2*inb_m1, ina_m2*inb_m2, ina_m2*inb_m3, ina_m2*inb_m4, of course The following calculations can also be performed in sequence: inb_m1*ina_m1, inb_m1*ina_m2, inb_m2*ina_m1, inb_m2*ina_m2, inb_m3*ina_m1, inb_m3*ina_m2, inb_m4*ina_m1, inb_m4*ina_m2. The calculation performed for each call is the multiplication operation of the multiplicand part with a bit width of 16 bits and the multiplier part with a bit width of 8 bits, so that the mantissa result obtained by the call can be calculated. It is worth noting that the truncation of the mantissa to be truncated can be performed in the order from the high order to the low order, or in the order from the low order to the high order.

The above examples are only for illustrative and non-limiting purposes. According to these examples, those skilled in the art can think of floating-point multiplication performed by multiple calls to the mantissa processing unit that supports the maximum arbitrary bit width in other operation modes. operation.

For the above multiple calls to the mantissa processing unit, the mantissa processing unit may further include a shift and addition circuit, and the shift and addition circuit is configured to obtain the multiplication operation according to the mantissa result obtained by calling the mantissa processing unit each time after the mantissa.

Further, the shift and addition circuit includes a shifter, an intermediate memory and an adder. When the control circuit calls the mantissa processing unit multiple times according to the operation mode, after the first call, the shift The shifter shifts the mantissa result obtained by the first call to obtain the shifted mantissa result and stores the shifted mantissa result in the intermediate memory. Starting from the second call, the shifter will The mantissa result obtained in the second call is shifted to obtain the current mantissa result, and the adder adds the current mantissa result and the result stored in the intermediate memory and stores the added result in the The intermediate storage is updated in the intermediate storage, and the result stored in the intermediate storage after the last call is used as the mantissa after the multiplication operation.

In this embodiment, for example, the truncation of the mantissa to be truncated is performed in order from high order to low order. Each time the mantissa processing unit is called, the shifter shifts the mantissa result obtained in the current call according to the following formula:

Y=k+j

Among them, Y represents the number of shifts required for the mantissa result obtained in the current call, and k represents the sum of the digits of all the data behind the truncated part used in the current call in the mantissa to be truncated corresponding to the multiplier , j represents the sum of the digits of all the data following the truncated part used in the current call in the mantissa to be truncated corresponding to the multiplicand. It should be understood that if only the bit width of the multiplier is larger than the maximum multiplier bit width or only the bit width of the multiplicand is larger than the maximum multiplicand bit width, it is only necessary to truncate the mantissa corresponding to the multiplier or the to-be-truncated mantissa corresponding to the multiplicand. Intercept the mantissa for interception, and the mantissa that does not need to be intercepted uses all its data each time it is called, so there is no data behind, so the value of k or j is 0, it can be seen that the bit width of only the multiplier is greater than the maximum In the case of the bit width of the multiplier, the above formula for calculating the number of shifts can be written as: Y=k. For the case where only the bit width of the multiplicand is greater than the maximum bit width of the multiplicand, the above formula for calculating the number of shifts can be written as: Y = j.

For example, as mentioned above, in the FP32*BF16 operation mode, when only the bit width of the multiplier is greater than the maximum multiplier bit width, the mantissa processing unit is called twice, and for example, the mantissa to be truncated is truncated according to in order from high to low. Specifically, for example, the multipliers in the two calls are inb_m1 and inb_m2 respectively. After the first call, the shifter shifts the result of ina*inb_m1 to the left, because 7 bits are intercepted in the first call data, so the sum of the digits of all the data after the 7bit data used in this call is k=8-7=1bit. According to the above formula, Y=1, so the number of digits shifted to the left is 1 bit to obtain the result R1 shifted by 1 bit, the adder stores this R1 in the intermediate memory; after the second call (the last call), the shifter will ina*inb_m2 The result of is shifted to the left. Since the last 1-bit data has been intercepted in the second call, there is no data after the 1-bit data used in this call. According to the above formula, Y=0, therefore, to The number of bits shifted to the left is 0 bits, that is, no shift is made, so that the result R2 is obtained, and the adder adds this R2 to R1 stored in the intermediate memory, and stores the added result in the The intermediate memory is updated by updating the intermediate memory. Since the second invocation is the last invocation, the result stored in the intermediate memory after the second invocation is the mantissa after the multiplication operation. For the above-mentioned case when only the bit width of the multiplicand is larger than the bit width of the maximum multiplicand, the shift-add circuit can also work in the same way.

For example, as described above, in the FP32*FP32 operation mode, when the bit width of the multiplier is larger than the maximum multiplier bit width and the bit width of the multiplicand is larger than the maximum multiplicand bit width , the mantissa processing unit is called eight times, and, for example, the truncation of the mantissa to be truncated is performed in order from high to low. Specifically, for example, the multiplier parts in the eight calls are inb_m1, inb_m2, inb_m3 and inb_m4 respectively, and the multiplicand parts are ina_m1 and inb_m2 respectively. For example, when the mantissa processing unit is called eight times, the following calculations are performed in sequence: ina_m1*inb_m1, ina_m1*inb_m2, ina_m1*inb_m3, ina_m1*inb_m4, ina_m2*inb_m1, ina_m2*inb_m2, ina_m2*inb_m3, ina_m2*inb_m4. In the first call, the shifter shifts the result of ina_m1*inb_m1 to the left. Since 7-bit data is intercepted in the mantissa to be truncated corresponding to the multiplier in the first call, the mantissa to be truncated in the first call The sum of the digits of all the data after the 7bit data used in this call is k=24-7=17bit, and 15bit data is truncated in the mantissa to be truncated corresponding to the multiplicand, so in the mantissa to be truncated The sum of the digits of all the data after the 15bit data used in this call is j=24-15=9bit. According to the above formula, Y=17+9=26, therefore, the number of digits shifted to the left is 26 bits, so the result S1 after shifting by 26 bits is obtained, and the adder stores the S1 in the intermediate memory; after the second call, the shifter shifts the result of ina_m1*inb_m2 to the left Shift, because in the second call, the next 7bit data is truncated in the mantissa to be truncated corresponding to the multiplier, so in the mantissa to be truncated, the sum of the digits of all the data after the 7bit data used in this call is The sum is k=24-7-7=10bit, and the same 7bit data as the last call (using the same 7bit data as the last call) is intercepted in the mantissa to be intercepted corresponding to the multiplicand, so in this pending The sum of the digits of all the data after the 7bit data used in this call in the truncated mantissa is still j=24-15=9bit. According to the above formula, Y=10+9=19, therefore, shift to the left The number of bits is 19, so that the result S2 shifted by 19 bits is obtained, the adder adds this S2 to S1 stored in the intermediate memory, and stores the added result in the intermediate memory to update the intermediate memory; the mantissa processing unit is called repeatedly until the fourth call, in which the shifter shifts the result of ina_m1*inb_m4 to the left, since in the fourth call Intercept the last 3bit data in the mantissa to be truncated corresponding to the multiplier, so there is no data in the mantissa to be truncated after the 3bit data used in this call, so k=0, and in the mantissa corresponding to the multiplicand The same 7bit data as the last call is intercepted in the truncated mantissa, so the sum of the digits of all the data after the 7bit data used in this call in the mantissa to be truncated is still j=24-15=9bit, according to The above formula shows that Y=0+9=9, therefore, the number of bits shifted to the left is 9 bits, so that the result S4 after shifting by 9 bits is obtained, and the adder stores the S4 and S4 in the intermediate memory. Add the results in , and store the added result in the intermediate memory to update the intermediate memory; because in the fifth to eighth calls, the to-be-intercepted corresponding to the multiplicand is intercepted The last 9bit data in the mantissa, and there is no more data after the 9bit data, so in the fifth to eighth calls, j=0, in the fifth call, all The shifter shifts the result of ina_m2*inb_m1 to the left, since in the fifth call, the same 7bit data as in the first call is truncated in the mantissa to be truncated corresponding to the multiplier, so k=24- 7=17bit, according to the above formula, Y=17+0=17, therefore, the number of bits shifted to the left is 17 bits, so the result S5 after shifting by 17 bits is obtained, and the adder combines the result S5 with The results stored in the intermediate memory are added, and the added results are stored in the intermediate memory to update the intermediate memory; so repeatedly call the mantissa processing unit until the eighth call, at the eighth call , the shifter shifts the result of ina_m2*inb_m4 to the left, since the last 3 bits of data in the mantissa to be truncated corresponding to the multiplier are truncated in the eighth call, so in the mantissa to be truncated this time There is no data after calling the 3-bit data used, so k=0. According to the above formula, Y=0+0=0. Therefore, the number of bits shifted to the left is 0 bits, that is, no shift is obtained. The shifted result S8, the adder adds this S8 to the result stored in the intermediate memory, and updates the intermediate memory by storing the added result in the intermediate memory; Eight calls are the last call, so the result stored in the intermediate memory after the eighth call is the mantissa after the multiplication.

On the other hand, in order to further reduce the area of the multiplier, the exponent processing unit includes a second control circuit (not shown in the figure), the second control circuit is used for according to one of the two floating-point numbers and one of the two bit widths supported by the exponent processing unit or determined multiple times according to the exponent bit widths of the two floating-point numbers and the two bit widths supported by the exponent processing unit The exponent processing unit is called to obtain the multiplied exponent.

According to a third embodiment of the present disclosure, the two floating-point numbers include a first floating-point number and a second floating-point number, the exponent processing unit supports a third bit width and a fourth bit width, the first floating point number The exponent of the point number is used as the third input corresponding to the third bit width, the exponent of the second floating point number is used as the fourth input corresponding to the fourth bit width, and the bit width of the third input is less than or equal to the third bit width, the second control circuit is configured to call the exponent processing unit multiple times to obtain the multiplication operation when the bit width of the fourth input is greater than the fourth bit width index. According to this embodiment, it is known that the bit width of one of the two inputs is fixed less than or equal to the one supported by the corresponding exponent processing unit. Therefore, it is only necessary to determine whether the other input is supported by the corresponding exponent processing unit. The size relationship of the bit width can determine whether to call the exponential processing unit multiple times.

According to a fourth embodiment of the present disclosure, the two floating-point numbers include a first floating-point number and a second floating-point number, the exponent processing unit supports a third bit width and a fourth bit width, the first floating point number The exponent of the point number is used as the third input corresponding to the third bit width, the exponent of the second floating point number is used as the fourth input corresponding to the fourth bit width, and the second control circuit is used when the When the bit width of the third input is greater than the third bit width and the bit width of the fourth input is less than or equal to the fourth bit width, when the bit width of the fourth input is greater than the fourth bit width width and the bit width of the third input is less than or equal to the third bit width or when the bit width of the third input is greater than the third bit width and the bit width of the fourth input is greater than the When the width is four bits, the exponent processing unit is called multiple times to obtain the exponent after the multiplication operation. According to this embodiment, the size relationship between the bit widths of the two inputs and the two bit widths supported by the exponent processing unit is uncertain, and it is necessary to determine the size relationship between the two inputs and the bit widths supported by the corresponding exponent processing units to determine Whether to call the exponential processing unit multiple times.

According to the fourth embodiment, when the exponent bit width of the first floating point number is smaller than the exponent bit width of the second floating point number and the third bit width is larger than the fourth bit width, or when all the When the exponent bit width of the first floating point number is greater than the exponent bit width of the second floating point number and the third bit width is smaller than the fourth bit width, the second control circuit selects the first floating point number. The exponent of the point number is selected as the fourth input corresponding to the fourth bit width and the exponent of the second floating point number is selected as the third input corresponding to the third bit width. It should be understood that when the exponents of two floating-point numbers are input irregularly, the exponents of the input two floating-point numbers can be firstly processed according to the strategy of large bit width to large bit width and small bit width to small bit width and the exponent processing unit. The supported two-bit widths are matched to avoid exponentiation of two floating-point numbers that can be processed at one time, but multiple calls are made.

Further, when the bit width of the third input is greater than the third bit width and the bit width of the fourth input is less than or equal to the fourth bit width, when the bit width of the fourth input is greater than the When the fourth bit width and the bit width of the third input is less than or equal to the third bit width or when the bit width of the third input is greater than the third bit width and the bit width of the fourth input is larger In the fourth bit width, the second control circuit is used for when the bit width of the third input is less than or equal to the bit width of the fourth input and the third bit width is less than or equal to the third input. When the width is four bits, the number of times to call the exponent processing unit and the data input to the exponent processing unit in each call is determined according to the bit width of the fourth input and the third bit width. It is worth noting that in the above three cases, the number of calls of the index processing unit and the data input to the index processing unit in each call are based on the larger of the bit widths of the third input and the fourth input and the third input. The smaller of the three-digit width and the fourth-digit width is determined. Of course, when the bit widths of the third input and the fourth input are the same or the third bit width and the fourth bit width are the same, either one of the same bit widths can be selected.

In this embodiment, the description about the first floating-point number and the second floating-point number is only for distinguishing the two floating-point numbers, wherein "third" and "fourth" have no limiting effect. Likewise, the description about the third input and the fourth input is only for distinguishing the two inputs of the exponent processing unit, and the description about the third bit width and the fourth bit width is only for distinguishing the one supported by the exponent processing unit from the The two inputs of the exponential processing unit correspond to the two maximum processing bit widths, so neither "third" nor "fourth" has a limiting effect.

It is worth noting that the floating-point numbers input to the multiplier described in the above embodiments are floating-point numbers that conform to the format required by the operation and are applicable to the internal and external components of the multiplier, that is, the floating-point numbers that have undergone preprocessing such as normalization. It should be understood that the floating-point number input to the multiplier may be a normalized or denormalized floating-point number. In combination with the above description of the normalization unit, it can be known that if at least one of the two input floating-point numbers is a non-normalized floating-point number For the normalized non-zero floating-point number, the at least one floating-point number may be normalized by the normalization unit to obtain the normalized exponent and the mantissa, and then the normalized exponent may be used as the value of the exponent processing unit. input to perform the floating-point multiplication operation described above. Of course, other preprocessing can also be performed on the floating point number, and the exponent of the preprocessed floating point number is used as the input of the exponent processing unit to perform the above-mentioned floating point number multiplication operation, for example, in the above description of the normalization unit Regarding the normalization of floating-point numbers in order to apply the operation mode, the third and fourth embodiments of the present disclosure are also applicable to the above-mentioned operation of floating-point numbers according to the operation mode.

An example of invoking the exponential processing unit multiple times is detailed below. In order to understand this example more clearly and intuitively, the above-mentioned third input may be, for example, the addend, the fourth input may be, for example, the summand, and the third bit width may be, for example, the maximum addend bit width supported by the exponent processing unit. The width may be, for example, the maximum summed digit width supported by the exponent processing unit.

According to the example of calling the exponent processing unit multiple times of the present disclosure, in combination with the floating-point multiplication operation according to the operation mode described above, the two floating-point numbers input to the multiplier of the present disclosure are denormalized non-zero floating-point numbers For example, the two floating-point numbers are first normalized, so the mantissas of the two floating-point numbers are extended by 1 bit. After this preprocessing, the exponents of the two floating point numbers are matched with the input to the exponent processing unit. Therefore, when the bit width of the summand is greater than the maximum addend bit width and the bit width of the summand is smaller than or equal to the maximum When it is equal to the maximum addend bit width or when the addend bit width is greater than the maximum addend bit width and the summand bit width is greater than the maximum summand bit width, the control circuit can determine the number of invocations of the exponent processing unit according to the following formula :

m=ceil(P/(Q-1)),

Among them, m represents the number of times the exponent processing unit is called, P represents the bit width of the summand, Q represents the maximum addend bit width, and Q-1 represents the bit width of the part truncated from the addend and the summand in each call. In each call, the part of the addend and the summand with a bit width of Q-1 is truncated at the same time, so that the part of the same bit width and the same number of digits truncated from the addend and the summand is added. If the data of the intercepted part is not enough for Q-1 bits or there is no data, 0 is added in front or all to make up the Q-1 bits of data. After extending a carry in front of the part truncated from the addend and summand, the addend part and the summand part of the input exponent processing unit are formed, so that Q also represents the addend of the input exponent processing unit on each call The bit width of the part and the summand part.

Therefore, the second control circuit can intercept the Q-1 bit part from the addend and the summand in the same order as the input of the exponent processing unit each time the exponent processing unit is called, and obtain this time through the exponent processing unit. The exponent result of the call, and the final exponent is obtained after calling the exponent processing unit m times. It is worth noting that the same order as above can be from high to low, or from low to high.

For example, the bit width of the addend is 6 bits, the bit width of the summand is 9 bits, and the maximum bit width of the addend and the maximum bit width of the augend supported by the exponent processing unit are both 8 bits. Therefore, the number of times the exponent processing unit is called is ceil(9/(8-1)) = 2, and the front of the addend is first filled with 0, so that the bit width of the addend is the same as the bit width of the summand. In the call, the addend and the summand are simultaneously truncated with a bit width of 7 bits in the order from high to low, and the two truncated parts are respectively extended by one carry bit to form two 8-bit carry bits The data is added. In the second call (that is, the last call), only 2 bits of data can be intercepted from the addend and the summand (only 2 bits of data are left). Therefore, the intercepted data in the second call The 2-bit data is filled with 0 to make up 7 bits, and a carry bit is extended to form two 8-bit data with carry for addition.

It is worth noting that in this example, when the bit width of the summand is greater than the maximum augend bit width and the bit width of the summand is less than or equal to the maximum augend bit width and when the bit width of the summand is greater than the maximum augend bit width And the call to the exponent processing unit when the bit width of the addend is less than or equal to the maximum addend bit width is also applicable to the third embodiment of the present disclosure.

According to an embodiment, the exponent processing unit may further include a second shift and addition circuit, and the second shift and addition circuit is configured to obtain the post-multiplication operation according to the exponent result obtained by calling the exponent processing unit each time. index.

Further, the second shift and add circuit includes a second shifter, a second intermediate memory and a second adder. When the second control circuit calls the exponent processing unit multiple times, after the first call , the second shifter shifts the exponent result obtained by the first invocation and stores the shifted exponent result in the second intermediate memory, starting from the second invocation of the exponent processing unit, the The exponent result obtained in the current call is shifted by a second shifter that adds the shifted exponent result to the value stored in the second intermediate memory and adds the added result The second intermediate storage is updated by storing in the second intermediate storage, and the value stored in the second intermediate storage in the last call is used as the exponent after the multiplication operation.

Each time the exponent processing unit is called, the second shifter shifts the exponent result obtained in the current call as follows: When counting and the summand, the part truncated from the addend and the summand in the current call is shifted to the left by the number of bits of the part after the part truncated from the summand in the current call. number.

For example, in combination with the above examples, for example, the bit width of the addend is 6 bits, the bit width of the summand is 9 bits, and the maximum bit width of the augand and the maximum bit width of the augend supported by the exponent processing unit are both 8 bits. Truncating the 7-bit part of the addend and the summand in the order from the high order to the low order. Specifically, after invoking the exponent processing unit for the first time, the second shifter shifts the exponent result obtained in the first invocation by 2 bits to the left (because there are 2 bits after the part truncated by the addend in this invocation data) and store the shifted exponent result in the second intermediate memory, starting from the second invocation of the exponent processing unit, the second shifter shifts the exponent result obtained in the current call to the left , since there is no more data after the intercepted part in this call, it is shifted to the left by 0 bits, that is, without shifting. Add the values and store the added result in the second intermediate memory to update the second intermediate memory. Since the second call is the last call, it is stored in the second intermediate memory after the second call. The value in the second intermediate storage is the exponent after the multiplication operation.

According to the situation that the multipliers (mantissa processing unit and exponent processing unit) of the present disclosure are called multiple times, it can be known that the control module may include multiple sub-modules, and the multiple sub-modules may be respectively used to execute multiple Various operations in the call, such as determining the number of calls to the mantissa processing unit, determining the number of calls, determining the data input to the mantissa processing unit in each call, judging whether the mantissa bit width matches the bit width supported by the mantissa processing unit, adjusting Mantissa input, etc. The second control module may also include multiple sub-modules, and similarly, these sub-modules may respectively perform various operations in multiple calls.

The operations performed by the multiplier of the present disclosure to multiply the mantissas of the first floating-point number and the second floating-point number when performing floating-point operations are described in detail above with reference to FIGS. 4 to 6 . Of course, in order to focus on describing the operation of the mantissa processing unit of the multiplier of the present disclosure, Fig. 4 does not draw and describe other units, such as the exponent processing unit and the sign processing unit. The multiplier of the present disclosure will be generally described below with reference to FIG. 7 , and the foregoing description of the mantissa processing unit is also applicable to the situation depicted in FIG. 7 .

FIG. 7 is an overall schematic block diagram illustrating a multiplier 700 according to an embodiment of the present disclosure. It should be understood that the positions, existence and connection relationships of various units shown in the figures are only exemplary and not limiting, for example, some of the units may be integrated, while other units may be separated or according to application scenarios. be omitted or replaced.

The multiplier of the present disclosure can be exemplarily divided into a first stage and a second stage according to the operation flow in the operation of each operation mode, as depicted by the dotted line in the figure. In general, in the first stage: output the calculation result of the sign bit, output the intermediate calculation result of the exponent bit, and output the intermediate calculation result of the mantissa bit (for example, including the encoding process of the aforementioned fixed-point multiplication Booth algorithm for the input mantissa bit and Huahua). Race tree compression process). In the second stage: the exponent and mantissa are regularized and rounded to output the calculation result of the exponent and the calculation result of the output mantissa.

As shown in FIG. 7, the multiplier of the present disclosure may include a mode selection unit 702 and a normalization processing unit 704, wherein the mode selection unit may select an operation mode according to an input mode signal (in_mode). In one embodiment, the input mode signal may correspond to the operation mode number in Table 2. For example, when the input mode signal indicates the operation mode number "1" in Table 2, the multiplier can be made to work in the operation mode of FP16*FP16, and when the input mode signal indicates the operation mode number "3" in Table 2 When , the multiplier can work in the operation mode of FP32*FP32. For the purpose of illustration, FIG. 7 only shows four exemplary operation modes of FP16*FP16, BF16*BF16, FP32*FP32 and FP32*BP16. However, as mentioned above, the multipliers of the present disclosure also support various other operation modes.

The normalization processing unit may be configured to, when the first floating point number or the second floating point number is a non-normalized non-zero floating point number, perform the first floating point number or the second floating point number according to the operation mode. Normalization processing is performed to obtain the corresponding exponent and mantissa, for example, according to the IEEE754 standard, regular processing is performed on the floating-point number in the data format indicated by the operation mode.

Further, the multiplier includes a mantissa processing unit to perform a multiplication operation of the first floating point mantissa and the second floating point mantissa. To this end, in one or more embodiments, the mantissa processing unit may include a bit expansion circuit 706, a Booth encoder 708, a partial product generation circuit 710, a Wallace tree compressor 712, and an adder 714, where the bits The number expansion circuit may be configured to perform digit expansion on the mantissa of at least one of the first floating-point number and the second floating-point number, for example, adding 0 to high-order bits, so as to be suitable for the operation of the Booth encoder. The control circuit may perform the above operations of calling the mantissa processing unit multiple times according to the mantissa obtained after the sign bit extension of the mantissa by the digit expansion circuit. Since the Booth encoder, the partial product generation circuit, the Wallace tree compressor and the adder have already been described in detail with reference to Figs. .

In some embodiments, the multiplier of the present disclosure also includes a regularization unit 716 and a rounding unit 718 that have the same functions as the units shown in FIG. 3 . Specifically, for the regularization unit, it can float the summation result and the exponent data from the exponent processing unit according to the data format indicated by the output mode signal "out_mode" as shown in FIG. 7 Regularize processing to obtain regularized exponent results and regularized mantissa results. For example, according to the data format indicated by the output mode signal, the regularization unit can adjust the bit widths of the exponent and the mantissa to make them meet the requirements of the data format indicated above. For another example, when the highest digit of the mantissa is 0, and the mantissa is not 0, the regularization unit can repeatedly shift the mantissa to the left by 1 bit, and decrease the exponent by 1, until the highest digit value is 1. For a rounding unit, in one embodiment, it may be used to perform a rounding operation on the regularized mantissa result to obtain a rounded mantissa according to a rounding mode, and use the rounded mantissa as the multiplication operation after the mantissa.

In one or more embodiments, the aforementioned output mode signal may be part of the operation mode for indicating the data format after the multiplication operation. For example, as described in Table 3 above, when the operation mode number is "12", the number "1" in it can be equivalent to the aforementioned "in_mode" signal, which is used to instruct to perform the multiplication operation of FP16*FP16, and The digit "2" in it can be equivalent to the "out_mode" signal, which is used to indicate that the data type of the output result is BF16. Therefore, it can be understood that, in some application scenarios, the output mode signal may be combined with the aforementioned input mode signal to provide the mode selection unit. Based on the combined mode signal, the mode selection unit can specify the data format of the input data and the output result at the initial stage of the multiplier operation without separately providing the output mode signal to the regularization, thereby further simplifying the operation.

In one or more embodiments, for the aforementioned rounding operation, the following five rounding modes may be exemplarily included.

(1) Round to the nearest value: In this mode, when two values are equally close, the even number takes precedence. At this time, the result will be rounded to the closest and representable value, but when there are two numbers that are equally close, the even number among them will be taken as the rounding result (the number ending in 0 in binary digits);

(2) Rounding: see the example below for an exemplary operation;

(3) Rounding towards +∞: Under this rule, the result will be rounded towards positive infinity;

(4) rounding towards -∞: Under this rule, the result is rounded towards negative infinity; and

(5) Rounding towards 0: Under this rule, the result will be rounded towards 0.

For example of mantissa rounding in "rounding" mode: for example, multiply the 24-bit mantissas of two normalized floating point numbers to obtain a 48-bit (47~0) mantissa, which is normalized (if the highest bit of the mantissa is If it is 0, move the mantissa to the left by 1; if the highest bit of the mantissa is 1, the mantissa will not change, and the temporary exponent obtained above will be added by 1), and only the 46th to 24th digits will be taken when outputting. When the 23rd digit of the mantissa is 0, the (23-0) digit is dropped; when the 23rd digit of the mantissa is 1, 1 is added to the 24th digit and the (23-0) digit is dropped.

Returning to FIG. 7, the multiplier of the present disclosure further includes an exponent processing unit 720 and a sign processing unit 722, wherein the exponent processing unit can be used to obtain according to the operation mode, the exponent of the first floating point number and the exponent of the second floating point number The exponent after the multiplication operation. For example, the exponent processing circuit may add the exponent bit data for the first floating point number, the exponent bit data for the second floating point number, and the offset values for their respective input floating point data types, and subtract the output floating point data type The offset value to obtain the exponent bit data of the product of the first floating point number and the second floating point number. In one or more embodiments, an exponent processing unit may be implemented as or include an addition and subtraction circuit for operating according to the operation mode, the exponent of the first floating point number, the exponent of the second floating point number and The operation mode obtains the exponent after the multiplication operation.

The sign processing unit may be implemented as an XOR circuit in one embodiment, which is configured to perform an XOR operation on the sign bit data of the first floating point number and the second floating point number to obtain the first floating point number Sign bit data for the product of the second floating point number.

The overall multiplier of the present disclosure is described in detail above with reference to FIG. 7 . Through this description, those skilled in the art can understand that the multiplier of the present disclosure supports operations in multiple operation modes, thereby overcoming the defect of the multiplier that only supports a single floating-point operation in the prior art. Further, since the multiplier of the present disclosure can be reused, it also supports high-bit-width floating-point data, which reduces operation cost and overhead. In one or more embodiments, the multipliers of the present disclosure may also be arranged or included in an integrated circuit chip or computing device to enable multiplication operations on floating point numbers in a variety of operational modes.

FIG. 8 is a flowchart illustrating a method 800 of performing a floating-point multiplication operation using a multiplier according to an embodiment of the present disclosure. It can be understood that the multiplier described here is the multiplier described in detail above in conjunction with Figures 1 to 7, so the previous descriptions about the multiplier and its internal composition, function and operation are also applicable here. description of.

As shown in FIG. 8, the method 800 may include utilizing the exponent processing unit of the multiplier at step S802 to obtain the said Exponent after multiplication. As previously mentioned, the operation mode can be one of several operation modes and can be used to indicate the data format of floating point numbers. In one or more embodiments, the operation mode may also be used to determine the data format of the floating point number of the output result.

Next, at step S804, the method 800 may utilize the mantissa processing unit of the multiplier to obtain the mantissa after the multiplication operation according to the operation mode, the first floating point number and the second floating point number. Regarding the exemplary manipulation of the mantissa, the present disclosure uses the Booth coding algorithm and the Wallace tree compressor in some preferred embodiments to improve the efficiency of the mantissa processing. In addition, when the first floating-point number and the second floating-point number are signed numbers, the method 800 may also be used in step S806 to obtain the multiplication operation according to the sign of the first floating-point number and the sign of the second floating-point number symbol.

Although the above method is shown in the form of steps to perform floating point multiplication operations using the multiplier of the present disclosure, the order of the steps does not imply that the steps of the method must be performed in the stated order, but may be performed in other orders or in parallel way to deal with. In addition, other steps of the method 800 are not described here for the sake of brevity of description, but those with ordinary knowledge in the art can understand from the content of the present disclosure that the method can also be performed by using a multiplier to perform the aforementioned combination of FIGS. 1-7. various operations described.

In the above-mentioned embodiments of the present disclosure, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference may be made to the relevant descriptions of other embodiments. The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity, all possible combinations of the technical features in the above embodiments are not described. However, as long as there is no contradiction in the combination of these technical features, it should be It is considered to be the range described in this specification.

FIG. 9 is a structural diagram illustrating a combined processing apparatus 900 according to an embodiment of the present disclosure. As shown, the combined processing device 900 includes a computing device 902, which may include the multipliers of the present disclosure as previously described in connection with the figures. In addition, the combined processing device also includes a general interconnection interface 904 and other processing devices 906 . The computing device according to the present disclosure interacts with other processing devices to jointly complete the operation specified by the user.

According to the solution of the present disclosure, the other processing device may include one or more types of general-purpose and/or special-purpose processors such as a central processing unit ("CPU"), a graphics processing unit ("GPU"), a neural network processor, etc. The number of processors is not limited but determined according to actual needs. In one or more embodiments, the other processing device can be used as an interface between the computing device of the present disclosure (which can be embodied as a machine learning computing device) and external data and control, performing operations including, but not limited to, data handling, completing the processing of this machine. Basic control of opening and stopping the learning computing device; other processing devices can also cooperate with the machine learning computing device to complete computing tasks.

According to the solution of the present disclosure, the universal interconnection interface can be used to transfer data and control instructions between the computing device and other processing devices. For example, the computing device can obtain required input data from other processing devices via the universal interconnection interface, and write the required input data into the on-chip storage device of the computing device. Further, the computing device can obtain control instructions from other processing devices via the universal interconnection interface, and write them into a control cache on the computing device chip. Alternatively or alternatively, the Universal Interconnection Interface can also read the data in the storage module of the computing device and transmit it to other processing devices.

Optionally, the combined processing device may further include a storage device 908, which may be respectively connected to the computing device and the other processing devices. In one or more embodiments, the storage device may be used to save the data of the computing device and the other processing device, especially for the data required for the operation that cannot be fully stored in the internal storage of the computing device or the other processing device saved data.

According to different application scenarios, the combined processing device of the present disclosure can be used as a SoC for equipment such as mobile phones, robots, drones, video capture, video surveillance equipment, etc., thereby effectively reducing the core area of the control part, improving the processing speed and reducing the overall power consumption. In this case, the general interconnection interface of the combined processing device is connected to certain components of the device. Some of the components here can be, for example, a monitor, display, mouse, keyboard, network card or wifi interface.

In some embodiments, the present disclosure also discloses a wafer or integrated circuit chip that includes the above-described computing device, combined processing device, and multiplier of the present disclosure. In other embodiments, the present disclosure also discloses a chip package structure including the above-mentioned chip.

In some embodiments, the present disclosure also discloses a board including the above-mentioned chip package structure. Referring to FIG. 10, the above-mentioned exemplary board 1000 is provided. In addition to the above-mentioned chip 1002, the above-mentioned board 1000 may also include other supporting components, and the supporting components may include but are not limited to: a storage device 1004, an interface device 1006 and control device 1008.

The storage device is connected to the chip in the chip package structure through a bus bar for storing data. The memory device may include groups of memory cells 1010 . Each group of the memory cells is connected to the wafer by bus bars. It can be understood that each group of the memory cells may be DDR SDRAM ("Double Data Rate SDRAM", double rate synchronous dynamic random access memory).

DDR does not need to increase the clock frequency to double the speed of SDRAM. DDR allows data to be read out on both the rising and falling edges of the clock pulse. DDR is twice as fast as standard SDRAM. In one embodiment, the memory device may include 4 sets of the memory cells. Each group of the memory cells may include a plurality of DDR4 granules (wafers). In one embodiment, the chip may include four 72-bit DDR4 controllers. Among the above 72-bit DDR4 controllers, 64 bits are used for data transmission and 8 bits are used for ECC verification.

In one embodiment, each group of the memory cells may comprise a plurality of double-rate synchronous dynamic random access memories arranged in parallel. DDR can transfer data twice in one clock cycle. A controller for controlling the DDR is arranged in the chip for controlling data transmission and data storage of each of the memory cells.

The interface device is electrically connected to the chip in the chip package structure. The interface device is used to realize data transfer between the chip and an external device 1012 (eg, a server or a computer). For example, in one embodiment, the interface device may be a standard PCIE interface. For example, the data to be processed is transmitted from the server to the chip through a standard PCIE interface to realize data transfer. In another embodiment, the interface device may also be other interfaces, and the present disclosure does not limit the specific expressions of the other interfaces, as long as the interface unit can realize the switching function. In addition, the calculation result of the chip is still sent back to an external device (eg a server) by the interface device.

The control device is electrically connected to the wafer to monitor the status of the wafer. Specifically, the chip and the control device may be electrically connected through an SPI interface. The control device may include a microcontroller ("MCU", Micro Controller Unit). The wafer may include multiple processing wafers, multiple processing cores, or multiple processing circuits, and may drive multiple loads. Thus, the wafer can be in different working states such as multi-load and light-load. The control device can realize the regulation of the working states of the plurality of processing wafers, the plurality of processing and/or the plurality of processing circuits in the wafer.

In some embodiments, the present disclosure also discloses an electronic device or device, which includes the above board. According to different application scenarios, electronic equipment or devices can include data processing devices, robots, computers, printers, scanners, tablet computers, smart terminals, mobile phones, driving recorders, navigators, sensors, monitors, Servers, Cloud Servers, Cameras, Video Cameras, Projectors, Watches, Headphones, Mobile Storage, Wearables, Vehicles, Home Appliances, and/or Medical Devices. The vehicles include airplanes, ships and/or vehicles; the household appliances include televisions, air conditioners, microwave ovens, refrigerators, electric cookers, humidifiers, washing machines, electric lamps, gas stoves, and range hoods; the medical equipment includes nuclear magnetic resonance device, B-ultrasound and/or electrocardiograph.

It should be noted that, for the sake of simple description, the foregoing method embodiments are all expressed as a series of action combinations, but those with ordinary knowledge in the art should know that the present disclosure is not limited by the described action sequence. limitation, as certain steps may be performed in other orders or concurrently in accordance with the present disclosure. Secondly, those with ordinary knowledge in the art should also know that the embodiments described in the specification are all optional embodiments, and the actions and modules involved are not necessarily required by the present disclosure.

In the above-mentioned embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference may be made to the relevant descriptions of other embodiments.

In the several embodiments provided in the present disclosure, it should be understood that the disclosed apparatus may be implemented in other manners. For example, the device embodiments described above are only illustrative. For example, the division of the units is only a logical function division. In actual implementation, there may be other division methods. For example, multiple units or elements may be combined or integrated. to another system, or some features can be ignored, or not implemented. Another point, the mutual coupling or direct coupling or communication connection shown or discussed may be through some interfaces, indirect coupling or communication connection of devices or units, which may be electrical, optical, acoustic, magnetic or other forms.

The unit described as a separate component may or may not be physically separated, and the component displayed as a unit may or may not be a physical unit, that is, it may be located in one place, or may be distributed to multiple network units . Some or all of the units may be selected according to actual needs to achieve the purpose of the solution in this embodiment.

In addition, each functional unit in each embodiment of the present disclosure may be integrated into one processing unit, or each unit may exist physically alone, or two or more units may be integrated into one unit. The above-mentioned integrated unit can be realized in the form of hardware, or can be realized in the form of software program module.

If the integrated unit is implemented in the form of a software program module and sold or used as an independent product, it can be stored in a computer-readable memory. Based on this understanding, when the technical solution of the present disclosure can be embodied in the form of a software product, the computer software product is stored in a memory and includes several instructions to enable a computer device (which may be a personal computer, a server or a network). road equipment, etc.) to perform all or part of the steps of the methods described in the various embodiments of the present disclosure. The aforementioned memory includes: flash drive, read-only memory ("ROM", Read-Only Memory), random access memory ("RAM", Random Access Memory), mobile hard disk, magnetic disk or CD, etc. The medium on which the code is stored.

The foregoing can be better understood in accordance with the following terms:

Clause A1, a multiplier for performing multiplication of floating point numbers, wherein the multiplier comprises:

a mantissa processing unit, configured to obtain the mantissa after the multiplication operation according to the mantissa of the floating-point number,

The mantissa processing unit includes a control circuit, and the control circuit is configured to call the mantissa multiple times when the mantissa bit width of at least one of the two floating-point numbers is larger than the data bit width that the mantissa processing unit can process at one time processing unit.

Clause A2, the multiplier of clause A1, wherein the two floating point numbers comprise a first floating point number and a second floating point number, the mantissa processing unit supports a first bit width and a second bit width, The mantissa of the first floating point number is used as the first input corresponding to the first bit width, the mantissa of the second floating point number is used as the second input corresponding to the second bit width, and the first The input bit width is less than or equal to the first bit width, and the control circuit is configured to call the mantissa processing unit multiple times to obtain the Mantissa after multiplication.

Clause A3. The multiplier of Clause A1 or Clause A2, wherein the two floating point numbers comprise a first floating point number and a second floating point number, the mantissa processing unit supporting a first wide and a second bit width, the mantissa of the first floating point number is used as the first input corresponding to the first bit width, and the mantissa of the second floating point number is used as the second input corresponding to the second bit width, so The control circuit is used for when the bit width of the first input is greater than the first bit width and the bit width of the second input is less than or equal to the second bit width, when the bit width of the second input is larger When the second bit width and the first input bit width is less than or equal to the first input width or when the first input bit width is greater than the first input width and the second input When the bit width is greater than the second bit width, the mantissa processing unit is called multiple times to obtain the mantissa after the multiplication operation.

Clause A4, the multiplier of any of clauses A1-A3, wherein when the mantissa bit width of the first floating point number is less than the mantissa bit width of the second floating point number and the first bit width is greater At the second bit width, or when the mantissa bit width of the first floating point number is greater than the mantissa bit width of the second floating point number and the first bit width is smaller than the second bit width, The control circuit selects the mantissa of the first floating point number as the second input corresponding to the second bit width and selects the mantissa of the second floating point number as the mantissa corresponding to the first bit width first input.

Clause A5, the multiplier of any of clauses A1-A4, wherein when the bit width of the first input is greater than the width of the first bit and the bit width of the second input is less than or equal to the width of the first input When the width is two bits, the control circuit determines the number of times to call the mantissa processing unit according to the bit width of the first input and the width of the first bit, and input data of the mantissa processing unit in each call.

Clause A6, the multiplier of any of clauses A1-A5, wherein when the bit width of the second input is greater than the second bit width and the bit width of the first input is less than or equal to the first input When the width is one bit, the control circuit determines the number of times of invoking the mantissa processing unit and the data input to the mantissa processing unit in each invocation according to the bit width of the second input and the second bit width.

Clause A7. The multiplier of any of clauses A1-A6, wherein when the first input has a bit width greater than the first bit width and the second input has a greater bit width than the second bit When it is wide, the control circuit determines the number of times to call the mantissa processing unit according to the bit width and the first bit width of the first input and the bit width and the second bit width of the second input and The data for the mantissa processing unit is entered in each call.

Clause A8. The multiplier of any one of clauses A1-A7, wherein the mantissa processing unit further includes a shift-and-add circuit for the mantissa result to obtain the mantissa after the multiplication.

Clause A9, the multiplier of any of clauses A1-A8, wherein the shift-add circuit includes a shifter, an intermediate memory, and an adder, when the control circuit calls the mantissa processing unit multiple times , after the first call, the shifter shifts the mantissa result obtained by the first call to obtain the shifted mantissa result and stores the shifted mantissa result in the intermediate memory, starting from the first When the second call starts, the shifter shifts the mantissa result obtained in the current call to obtain the current mantissa result, and the adder compares the current mantissa result with the result stored in the intermediate memory. The intermediate storage is updated by adding and storing the added result in the intermediate storage, and the result stored in the intermediate storage after the last call as the mantissa after the multiplication.

Clause A10, the multiplier according to any one of clauses A1-A9, wherein the multiplier further comprises an exponent processing unit for obtaining the exponent from the exponents of the two floating-point numbers The exponent after the multiplication operation, the exponent processing unit includes a second control circuit, and the second control circuit is configured to: One of the bit widths, or according to the exponent bit widths of the two floating-point numbers and the two bit widths supported by the exponent processing unit, the exponent processing unit is called multiple times to obtain the multiplication result. index.

Clause A11. The multiplier of any one of clauses A1-A10, wherein the two floating-point numbers comprise a first floating-point number and a second floating-point number, the exponent processing unit supporting a third bit width and The fourth bit width, the exponent of the first floating point number is used as the third input corresponding to the third bit width, and the exponent of the second floating point number is used as the fourth input corresponding to the fourth bit width , the bit width of the third input is less than or equal to the third bit width, and the second control circuit is configured to call the an exponent processing unit to obtain the multiplied exponent.

Clause A12. The multiplier of any of clauses A1-A11, wherein the two floating-point numbers comprise a first floating-point number and a second floating-point number, the exponent processing unit supporting a third bit width and The fourth bit width, the exponent of the first floating point number is used as the third input corresponding to the third bit width, and the exponent of the second floating point number is used as the fourth input corresponding to the fourth bit width , the second control circuit is used for when the bit width of the third input is greater than the third bit width and the bit width of the fourth input is less than or equal to the fourth bit width, when the fourth When the bit width of the input is greater than the fourth bit width and the bit width of the third input is less than or equal to the third bit width or when the bit width of the third input is greater than the third bit width and the When the bit width of the fourth input is larger than the fourth bit width, the exponent processing unit is called multiple times to obtain the exponent after the multiplication operation.

Clause A13. The multiplier of any one of clauses A1-A12, wherein when the exponent bit width of the first floating point number is smaller than the exponent bit width of the second floating point number and the third bit width is greater At the fourth bit width, or when the exponent bit width of the first floating point number is greater than the exponent bit width of the second floating point number and the third bit width is smaller than the fourth bit width, The second control circuit selects the exponent of the first floating point number as the fourth input corresponding to the fourth bit width and selects the exponent of the second floating point number as the exponent corresponding to the third bit width the corresponding third input.

Clause A14. The multiplier of any one of clauses A1-A13, wherein the second control circuit is configured to operate when the bit width of the third input is less than or equal to the bit width of the fourth input and the When the third bit width is less than or equal to the fourth bit width, the number of times to call the exponent processing unit is determined according to the bit width of the fourth input and the third bit width, and the number of times of calling the exponent processing unit is input in each call Data for the index processing unit.

Clause A15. The multiplier of any one of clauses A1-A14, wherein the exponent processing unit further includes a second shift-add circuit for invoking the exponent according to each call The exponent result obtained by the processing unit is used to obtain the multiplied exponent.

Clause A16. The multiplier of any of clauses A1-A15, wherein the mantissa processing unit includes a partial product operation unit and a partial product summation unit, wherein the partial product operation unit is configured to operate according to the two The mantissa of the floating-point number obtains an intermediate result, and the partial product summing unit is configured to perform an addition operation on the intermediate results to obtain an addition result, and use the addition result as the mantissa after the multiplication operation.

Clause A17. The multiplier according to any one of clauses A1-A16, wherein the partial product operation unit includes a Booth encoding circuit configured to perform an operation on the first floating point number or the The mantissa of the second floating point number is Booth-encoded to obtain the intermediate result.

Clause A18. The multiplier of any of clauses A1-A17, wherein the partial product summation unit includes an adder for adding the intermediate results to obtain the summation result.

Clause A19. The multiplier of any one of clauses A1-A18, wherein the partial product summation unit comprises a Wallace tree and an adder, wherein the Wallace tree is used to perform a computation on the intermediate result. summing to obtain a second intermediate result, and the adder is configured to add the second intermediate results to obtain the summing result.

Clause A20. The multiplier of any one of clauses A1-A19, wherein the adder includes at least one of a full adder, a serial adder, and a carry-lookahead adder.

Clause A21, the multiplier according to any one of clauses A1-A20, wherein, when the number of the intermediate results is less than M, a zero value is added as the intermediate result, so that the number of the intermediate results is equal to M, wherein M is a preset positive integer.

Clause A22, the multiplier of any one of clauses A1-A21, wherein each of the Wallace trees has M inputs and N outputs, and the number of Wallace trees is not less than K, where N is a preset positive integer smaller than M, and K is a positive integer not smaller than the maximum bit width of the intermediate result.

Clause A23. The multiplier of any one of clauses A1-A22, wherein the partial product summation unit is configured to select one or more sets of the Wallace tree to sum the intermediate results, wherein Each group of the Wallace trees has X Wallace trees, where X is the number of digits of the intermediate results, wherein the Wallace trees in each group are in a sequential carry relationship, and between the groups The Wallace tree does not have a carry relationship.

Clause A24, the multiplier of any one of clauses A1-A23, wherein the multiplier further comprises:

A normalization processing unit, configured to perform normalization processing on the at least one floating point number when at least one floating point number in the two floating point numbers is a denormalized non-zero floating point number to obtain a corresponding exponent and mantissa.

Clause A25. The multiplier of any one of clauses A1-A24, wherein the multiplier is configured to perform a multiplication of the two floating-point numbers according to an operation mode indicating the two floating-point numbers The data format of the number, the mantissa processing unit is used for obtaining the mantissa after the multiplication operation according to the operation mode and the mantissas of the two floating-point numbers, and the exponent processing unit is used for obtaining the mantissa after the multiplication operation according to the operation mode and the exponents of the two floating point numbers to obtain the multiplied exponent.

Item A26, the multiplier according to any one of Items A1-A25, the normalization processing unit is further configured to normalize at least one floating-point number in the two floating-point numbers according to the operation mode process to obtain the corresponding exponent and mantissa.

Clause A27, the multiplier according to any one of clauses A1-A26, wherein the data format includes half-precision floating-point number, single-precision floating-point number, brain floating-point number, double-precision floating-point number, custom At least one of floating point numbers.

Clause A28. The multiplier according to any one of clauses A1-A27, wherein the mantissa processing unit includes a number of bits expansion circuit for performing a comparison between the first floating point number and the first floating point number. The mantissa of at least one of the two floating-point numbers is digit-extended.

Clause A29. The multiplier of any one of clauses A1-A28, wherein the floating point number further comprises a sign, the multiplier further comprising:

A symbol processing unit, configured to obtain the symbol after the multiplication operation according to the symbols of the two floating-point numbers.

Clause A30. The multiplier according to any one of clauses A1-A29, wherein the sign processing unit includes an exclusive-OR logic circuit for XORing according to the signs of the two floating-point numbers OR operation to obtain the symbol after the multiplication operation.

Clause A31, the multiplier of any of clauses A1-A30, further comprising a regularization unit for:

performing floating point regularization processing on the mantissa and exponent after the multiplication operation to obtain a regularized exponent result and a regularized mantissa result, and using the regularized exponent result and the regularized mantissa result as the multiplication operation the exponent after the multiplication and the mantissa after the multiplication.

Clause A32, the multiplier of any of clauses A1-A31, further comprising:

A rounding unit, configured to perform a rounding operation on the regularized mantissa result according to a rounding mode to obtain a rounded mantissa, and use the rounded mantissa as the mantissa after the multiplication operation.

Clause A33, A method of performing a floating-point multiplication operation using a multiplier, wherein,

Using the mantissa processing unit of the multiplier to obtain the mantissa after the multiplication operation according to the mantissa of the floating point number,

The mantissa processing unit includes a control circuit, and the control circuit is configured to call the mantissa multiple times when the mantissa bit width of at least one of the two floating-point numbers is larger than the data bit width that the mantissa processing unit can process at one time processing unit.

Clause A34, an integrated circuit chip comprising the multiplier of any of clauses A1-A31.

Clause A35, A computing device comprising the multiplier of any one of clauses A1-A31 or the integrated circuit chip of clause A34.

The embodiments of the present disclosure have been introduced in detail above, and the principles and implementations of the present disclosure are described in this paper by using specific examples. The descriptions of the above embodiments are only used to help understand the methods and core ideas of the present disclosure; at the same time, for Those with ordinary knowledge in the art, according to the idea of the present disclosure, will have changes in the specific implementation manner and application scope. In conclusion, the contents of this description should not be construed as a limitation of the present disclosure.

It should be understood that the terms "first", "second", "third" and "fourth" in the scope of the application, the description and the drawings of the present disclosure are used to distinguish different items, rather than to describe specific items. order. The terms "comprising" and "comprising" used in the specification and scope of the present disclosure indicate the presence of the described feature, integer, step, operation, element and/or element, but do not exclude one or more other features, integers , step, operation, element, element and/or the presence or addition of a collection thereof.

It should also be understood that the terminology used in the present disclosure is for the purpose of describing particular embodiments only and is not intended to limit the present disclosure. As used in this disclosure and the claimed scope, the singular forms "a," "an," and "the" are intended to include the plural unless the context clearly dictates otherwise. It should further be understood that, as used in this disclosure and in the claims, the term "and/or" refers to and including any and all possible combinations of one or more of the associated listed items.

As used in this specification and the scope of the claims, the term "if" may be interpreted as "when" or "once" or "in response to determining" or "in response to detecting", depending on the context. Similarly, the phrases "if it is determined" or "if the [described condition or event] is detected" can be interpreted, depending on the context, to mean "once it is determined" or "in response to the determination" or "once the [described condition or event] is detected. event]" or "in response to detection of the [described condition or event]".

The embodiments of the present disclosure are described in detail above, and specific examples are used to illustrate the principles and implementations of the present disclosure. The descriptions of the above embodiments are only used to help understand the methods and core ideas of the present disclosure. Meanwhile, any changes or modifications made by those with ordinary knowledge in the art based on the ideas of the present disclosure, based on the specific embodiments and application scope of the present disclosure, all belong to the protection scope of the present disclosure. In conclusion, the contents of this specification should not be construed as limiting the present disclosure.

100: Floating point data format 102: Sign bit 104: Exponent bit 106: mantissa digits 200, 300, 700: Multiplier 202, 720: Index processing unit 204: Mantissa processing unit 206, 722: Symbol processing unit 308: Mode selection unit 312: Partial product operation unit 314: Partial product sum unit 316: Control circuit 318, 716: Regularization unit 320: rounding unit 322: XOR logic circuit 324: Normalized processing unit 400: Mantissa processing unit operation 402: Booth Encoding Circuit 404: Partial product generation circuit 406: Wallace Compressor 408, 714: Adder 500: Partial product 600: Operational flow and schematic block diagram of Wallace tree compressor 702: Mode selection unit 704: Normalized processing unit 706: Bit expansion circuit 708: Booth Encoder 710: Partial product generation circuit 712: Wallace Tree Compressor 800: Method for performing floating-point multiplication using multipliers 716: Mode selection unit 720: Mode selection unit 722: Mode selection unit 900: Combined Treatment Unit 902: Computing Devices 904: Universal Interconnect Interface 906: Other processing devices 908: Storage Device 1000: board 1002: Wafer 1004: Storage Device 1006: Interface Device 1008: Control device 1010: Storage Unit 1012: External Devices S802-S806: Steps

[FIG. 1] A schematic diagram showing a floating point data format according to an embodiment of the present disclosure. [Fig. 2] shows a schematic structural block diagram of a multiplier according to an embodiment of the present disclosure. [FIG. 3] A block diagram showing more details of the structure of the multiplier according to an embodiment of the present disclosure. [Fig. 4] shows a schematic block diagram of a mantissa processing unit according to an embodiment of the present disclosure. [FIG. 5] A schematic diagram showing a partial product operation according to an embodiment of the present disclosure. [Fig. 6] shows an operation flow and a schematic block diagram of a Wallace tree compressor according to an embodiment of the present disclosure. [Fig. 7] shows an overall schematic block diagram of a multiplier according to an embodiment of the present disclosure. [FIG. 8] A flowchart showing a method of performing a floating-point multiplication operation using a multiplier according to an embodiment of the present disclosure. [Fig. 9] shows a structural diagram of a combined processing apparatus according to an embodiment of the present disclosure. [Fig. 10] shows a schematic structural diagram of a board according to an embodiment of the present disclosure.

900: Combined Treatment Unit

902: Computing Devices

904: Universal Interconnect Interface

906: Other processing devices

908: Storage Device

Claims (34)

A multiplier for multiplying floating-point numbers, wherein the multiplier includes: a mantissa processing unit, configured to obtain the mantissa after the multiplication operation according to the mantissa of the floating-point number, and the mantissa processing The unit includes a control circuit for invoking the mantissa processing unit multiple times when the mantissa bit width of at least one of the two floating-point numbers is larger than the data bit width that the mantissa processing unit can process at one time, wherein , the multiplier further includes an exponent processing unit, which is configured to obtain the exponent after the multiplication operation according to the exponents of the two floating-point numbers, and the exponent processing unit includes a second control circuit, the The second control circuit is used for according to the exponent bit width of one of the two floating point numbers and one of the two bit widths supported by the exponent processing unit or according to the exponent bit of the two floating point numbers The width and the two bit widths supported by the exponent processing unit are used to determine that the exponent processing unit is called multiple times to obtain the multiplied exponent. The multiplier of claim 1, wherein the two floating point numbers include a first floating point number and a second floating point number, the mantissa processing unit supports a first bit width and a second bit width, the first floating point number The mantissa of the floating point number is used as the first input corresponding to the first bit width, the mantissa of the second floating point number is used as the second input corresponding to the second bit width, and the bit width of the first input is less than or equal to the first bit width, and the control circuit is configured to call the mantissa processing unit multiple times to obtain the multiplication result when the second input bit width is greater than the second bit width. mantissa. The multiplier of claim 1, wherein the two floating point numbers include a first floating point number and a second floating point number, the mantissa processing unit supports a first bit width and a second bit width, the first floating point number floating point The mantissa of the number is used as the first input corresponding to the first bit width, the mantissa of the second floating point number is used as the second input corresponding to the second bit width, and the control circuit is used for when the first When the bit width of an input is greater than the first bit width and the bit width of the second input is less than or equal to the second bit width, when the bit width of the second input is greater than the second bit width and all When the bit width of the first input is less than or equal to the first bit width or when the bit width of the first input is greater than the first bit width and the bit width of the second input is greater than the second bit width When , the mantissa processing unit is called multiple times to obtain the mantissa after the multiplication operation. The multiplier of claim 3, wherein when the mantissa bit width of the first floating point number is smaller than the mantissa bit width of the second floating point number and the first bit width is greater than the second bit width, or when the mantissa bit width of the first floating point number is greater than the mantissa bit width of the second floating point number and the first bit width is smaller than the second bit width, the control circuit selects the first The mantissa of the floating point number is used as the second input corresponding to the second bit width and the mantissa of the second floating point number is selected as the first input corresponding to the first bit width. The multiplier of claim 4, wherein when the bit width of the first input is greater than the first bit width and the bit width of the second input is less than or equal to the second bit width, the control circuit The number of times to call the mantissa processing unit and the data input to the mantissa processing unit in each call are determined according to the bit width of the first input and the first bit width. The multiplier of claim 4, wherein when the bit width of the second input is greater than the second bit width and the bit width of the first input is less than or equal to the first bit width, the control circuit The number of times to call the mantissa processing unit and the data input to the mantissa processing unit in each call are determined according to the bit width of the second input and the second bit width. The multiplier of claim 4, wherein when the bit width of the first input is greater than the first bit width and the bit width of the second input is greater than the second bit width, the control circuit The bit width and the first bit width of the first input and the bit width and the second bit width of the second input to determine the number of times to call the mantissa processing unit and input the mantissa in each call Processing unit data. The multiplier of any one of claim 2 to 7, wherein the mantissa processing unit further comprises a shift-add circuit, the shift-and-add circuit is configured to obtain a mantissa result obtained by calling the mantissa processing unit each time Obtain the mantissa after the multiplication operation. The multiplier of claim 8, wherein the shift and addition circuit includes a shifter, an intermediate memory and an adder, and when the control circuit calls the mantissa processing unit multiple times, after the first call, all The shifter shifts the mantissa result obtained by the first call to obtain the shifted mantissa result and stores the shifted mantissa result in the intermediate memory. Starting from the second call, the shift The adder shifts the mantissa result obtained in the current call to obtain the current mantissa result, the adder adds the current mantissa result and the result stored in the intermediate memory and stores the added result The intermediate storage is updated in the intermediate storage, and the result stored in the intermediate storage after the last call is used as the mantissa after the multiplication operation. The multiplier of claim 1, wherein the two floating-point numbers include a first floating-point number and a second floating-point number, the exponent processing unit supports a third bit width and a fourth bit width, the first The exponent of the floating point number is used as the third input corresponding to the third bit width, the exponent of the second floating point number is used as the fourth input corresponding to the fourth bit width, and the bit width of the third input is less than or equal to the third bit width, and the second control circuit is configured to call the exponent processing unit multiple times to obtain the multiplication operation when the bit width of the fourth input is greater than the fourth bit width after the index. The multiplier of claim 1, wherein the two floating-point numbers include a first floating-point number and a second floating-point number, the exponent processing unit supports a third bit width and a fourth bit width, the first floating point The exponent of the number is used as the third input corresponding to the third bit width, the exponent of the second floating point number is used as the fourth input corresponding to the fourth bit width, and the second control circuit is used when all the When the bit width of the third input is greater than the third bit width and the bit width of the fourth input is less than or equal to the fourth bit width, when the bit width of the fourth input is greater than the fourth bit width and the bit width of the third input is less than or equal to the third bit width or when the bit width of the third input is greater than the third bit width and the bit width of the fourth input is greater than the fourth When the bit width is large, the exponent processing unit is called multiple times to obtain the exponent after the multiplication operation. The multiplier of claim 11, wherein when the exponent bit width of the first floating point number is smaller than the exponent bit width of the second floating point number and the third bit width is greater than the fourth bit width, Or when the exponent bit width of the first floating point number is greater than the exponent bit width of the second floating point number and the third bit width is smaller than the fourth bit width, the second control circuit selects the The exponent of the first floating point number is selected as the fourth input corresponding to the fourth bit width and the exponent of the second floating point number is selected as the third input corresponding to the third bit width. The multiplier of claim 12, wherein the second control circuit is configured to operate when the bit width of the third input is less than or equal to the bit width of the fourth input and the third bit width is less than or equal to the When the fourth bit width is used, the number of times to call the exponent processing unit and the data input to the exponent processing unit in each call is determined according to the bit width of the fourth input and the third bit width. The multiplier of any one of claim 10 to 13, wherein the exponent processing unit further comprises a second shift-add circuit, the second shift-and-add circuit is configured to obtain the result obtained by calling the exponent processing unit each time the exponent result to obtain the multiplied exponent. The multiplier of claim 1, wherein the mantissa processing unit comprises a partial product operation unit and a partial product summation unit, wherein the partial product operation unit is configured to The mantissa of the number obtains an intermediate result, and the partial product summing unit is configured to perform an addition operation on the intermediate results to obtain an addition result, and use the addition result as the mantissa after the multiplication operation. The multiplier of claim 15, wherein the partial product operation unit comprises a Booth encoding circuit, and the Booth encoding circuit is used to distribute the mantissa of the first floating point number or the second floating point number s encoding process to obtain the intermediate result. The multiplier of claim 16, wherein the partial product summation unit includes an adder for adding the intermediate results to obtain the addition result. The multiplier of claim 16, wherein the partial product summation unit comprises a Wallace tree and an adder, wherein the Wallace tree is used to sum the intermediate results to obtain a second intermediate result , the adder is configured to add the second intermediate result to obtain the added result. The multiplier of claim 17 or 18, wherein the adder comprises at least one of a full adder, a serial adder, and a carry-lookahead adder. The multiplier of claim 18, wherein when the number of the intermediate results is less than M, a zero value is added as the intermediate result, so that the number of the intermediate results is equal to M, where M is a preset positive integer. The multiplier of claim 20, wherein each of the Wallace trees has M inputs and N outputs, and the number of the Wallace trees is not less than K, where N is a preset positive integer less than M , K is a positive integer not less than the maximum bit width of the intermediate result. The multiplier of claim 21, wherein the partial product summation unit is configured to select one or more groups of the Wallace trees to sum the intermediate results, wherein each group of the Wallace trees has X A Wallace tree, X is the number of digits of the intermediate result, wherein the Wallace tree in each group has a carry relationship in turn, and the Wallace tree between groups does not have a carry relationship . The multiplier of claim 1, wherein the multiplier further comprises: a normalization processing unit for when at least one of the two floating-point numbers is a denormalized non-zero floating-point number , normalize the at least one floating-point number to obtain the corresponding exponent and mantissa. The multiplier of claim 1, wherein the multiplier is configured to perform a multiplication operation of the two floating-point numbers according to an operation mode, the operation mode indicating the data format of the two floating-point numbers, and the mantissa processing The unit is configured to obtain the mantissa after the multiplication operation according to the operation mode and the mantissas of the two floating-point numbers, and the exponent processing unit is configured to obtain the mantissa after the multiplication operation according to the operation mode and the mantissas of the two floating-point numbers. exponent to obtain the multiplied exponent. The multiplier of claim 24, wherein the normalization processing unit is further configured to perform normalization processing on at least one floating-point number in the two floating-point numbers according to the operation mode to obtain a corresponding exponent and mantissa. The multiplier of claim 25, wherein the data format includes at least one of half-precision floating-point numbers, single-precision floating-point numbers, brain floating-point numbers, double-precision floating-point numbers, and custom floating-point numbers. The multiplier of claim 16, wherein the mantissa processing unit includes a number of bits expansion circuit for performing a multiplication of at least one of the first floating-point number and the second floating-point number The mantissa is digit-extended. The multiplier of claim 1, wherein the floating-point number further comprises a sign, and the multiplier further comprises: a sign processing unit, configured to obtain a multiplied sign according to the sign of the two floating-point numbers. The multiplier of claim 28, wherein the symbol processing unit includes an exclusive-OR logic circuit, and the exclusive-OR logic circuit is configured to perform an exclusive-OR operation according to the signs of the two floating-point numbers, and obtain the multiplication symbol. The multiplier of claim 24, further comprising a regularization unit for: performing floating point regularization processing on the mantissa and exponent after the multiplication operation to obtain a regularized exponent result and a regularized mantissa result, and The regularized exponent result and the regularized mantissa result are used as the multiplied exponent and the multiplied mantissa. The multiplier of claim 30, further comprising: a rounding unit configured to perform a rounding operation on the regularized mantissa result according to a rounding mode to obtain a rounded mantissa, and use the rounded mantissa as The mantissa after the multiplication operation. A method for performing a floating-point multiplication operation using a multiplier, wherein a mantissa after the multiplication operation is obtained according to the mantissa of the floating-point number by a mantissa processing unit of the multiplier, and the mantissa processing unit includes a control circuit , the control circuit is configured to call the mantissa processing unit multiple times when the mantissa bit width of at least one of the two floating-point numbers is larger than the data bit width that the mantissa processing unit can process at one time, and use the exponent to process The unit obtains the exponent after the multiplication operation according to the exponents of the two floating-point numbers, the exponent processing unit includes a second control circuit, and the second control circuit is used for according to the exponent of the two floating-point numbers. The exponent bit width of one and one of the two bit widths supported by the exponent processing unit, or the number of bits is determined according to the exponent bit width of the two floating-point numbers and the two bit widths supported by the exponent processing unit. The exponent processing unit is called several times to obtain the multiplied exponent. An integrated circuit chip comprising the multiplier of any one of claims 1 to 31. A computing device, comprising the multiplier of any one of claims 1-31 or the integrated circuit chip of claim 33.

Images