CN1932442A - Frequency divider adapted to optical fiber top - Google Patents
Frequency divider adapted to optical fiber top Download PDFInfo
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- CN1932442A CN1932442A CN 200610113626 CN200610113626A CN1932442A CN 1932442 A CN1932442 A CN 1932442A CN 200610113626 CN200610113626 CN 200610113626 CN 200610113626 A CN200610113626 A CN 200610113626A CN 1932442 A CN1932442 A CN 1932442A
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Abstract
The invention discloses a frequency dividing device used for the optical fibre gyro which is made up of the FPGA processor slug, the frequency dividing producer and the crystal oscillator. The CLKIN end of frequency outputted by the crystal oscillator is connected with the clock import CLKIN end of the FPGA processor. The frequency dividing producer outputs the frequency dividing coefficient to the configuration files of the FPGA processor slug and stores it in the EPROM. The invention can do the frequency dividing work of the signal, the double and three axes gyro by a FPGA combined with a crystal oscillating circuit. It can match to the characteristic frequency precisely before knowing the light path characteristic frequency to protect the performance of the optical fibre gyro.
Description
Technical field
The present invention relates to a kind of frequency divider that is applicable to optical fibre gyro, this device is to have utilized the built-in digital dock management resource of FPGA (field programmable logic array (FPLA)).
Background technology
Interference optical fiber top is a kind of instrument of measured angular speed, and its hardware comprises light source 1, coupling mechanism 2, Y waveguide 3, fiber optic loop 4, detector 5 and signal processing apparatus 6 compositions (seeing also shown in Figure 1).Described signal processing apparatus 6 comprises testing circuit 61, A/D converter 62, center processor 63, the D/A converter 64 of the optical power signals that is used to detect detector 5 outputs and amplifies modulate circuit 65 and form (seeing also shown in Figure 2).The center reason device 63 can be realized by DSP, also can be realized by FPGA, also can be realized by DSP+FPGA.Interference optical fiber top to the measurement of angular velocity be by the two bundles light in opposite directions in fiber optic loop 4, propagated in the rotation of optical fibre gyro self, the non-reciprocal phase extent that causes characterizes.Gyro is responsive device with respect to the inertial space angular motion.It is used to measure the attitude angle and the angular velocity of carrier as a kind of important inertial sensor, is the core devices that constitutes inertia system.Be applied in aircraft navigation, ship navigation and land with in the navigation.
In the interference optical fiber top ring interferometer, 1/2nd of the difference inverse in group's transmission time of the two-way light path of light wave between Y waveguide 3 and coupling mechanism 2 is called the eigenfrequency (eigen frequency) of optical fibre gyro.The response of the luminous power of optical fibre gyro minimum reciprocal structure is the cosine function of a protuberance, in order to obtain higher sensitivity, so apply a biasing to this signal, makes it to be operated near the non-vanishing point of response slope.And the parasitic non-linear or Modulation and Amplitude Modulation in the Y waveguide 3 may weaken the quality of biasing.Under Y waveguide 3 nonlinear situations, a kind of simple solution is that optical fibre gyro ring is operated on the eigenfrequency (or its odd harmonic), and therefore, the signal processing apparatus 6 of optical fibre gyro all is based on its eigenfrequency usually and designs its control timing.
Because during 4 coilings of actual fiber ring, be subjected to four extremely symmetrical restrictions around factors such as loop technique, optical fiber tension control technology and assemblings, can not make the fiber optic loop of producing, has identical length, thereby has identical eigenfrequency, but roughly in certain scope, this numerical range is decided by the optical fibre gyro precision index.Be convenient debugging and batch process, the sequence generation module of signal processing apparatus 6 must be followed the tracks of the optical fiber gyroscope eigenfrequency by the decision of the fiber lengths on the fiber optic loop 4 under the prerequisite of not changing hardware.At present, generally adopt discrete phaselocked loop (PLL) circuit to cooperate logical device to realize the fractional frequency division of specific crystal oscillator frequency to optical fiber gyroscope eigenfrequency; The digital frequency synthesizer spare (DFS) of the employing special use that also has is finished same work.These two kinds of implementations have increased the optical fibre gyro volume, are not suitable for the production and the application of mini optical fibre gyro, have also strengthened the production cost of optical fiber simultaneously.
Summary of the invention
The purpose of this invention is to provide a kind of frequency divider that is applicable to optical fibre gyro, the crystal oscillator frequency of the different divide ratios of this frequency divider by adopting the output of divide ratio generator, crystal oscillator output and FPGA sheet internal clock management resource adaptive, obtain the frequency division of the optical fibre gyro under the different frequency condition, improved the volume of optical fibre gyro effectively, optical fibre gyro is developed to micro-miniature structures, enlarged the range of application of optical fibre gyro.
The present invention is a kind of frequency divider that is applicable to optical fibre gyro, is made of FPGA processor chips, divide ratio generator and crystal oscillator; The crystal oscillator frequency Clk_in end of crystal oscillator output connects with the clock input CLKIN end of FPGA processor, and the divide ratio generator is with the divide ratio M that produces
n, D
n, Z
nExport to the configuration file of FPGA, be kept among the EPROM.
Described divide ratio generator is used to realize to reading
(a) running parameter during the optical fibre gyro operate as normal; With
(b) performance parameter of fpga chip;
According to the parameter frequency division
Carry out frequency division and handle, obtain divide ratio M, D, Z; And described divide ratio M, D, Z and optical fibre gyro integrated mode mated, and the divide ratio M after will mating
n, D
n, Z
nExport to the configuration file of FPGA, be kept among the EPROM;
Described FPGA processor is used for receiving
(a) the divide ratio M after the coupling of described divide ratio generator output
n, D
n, Z
nWith
(b) crystal oscillator frequency of described crystal oscillator output;
And the information of utilizing the sheet internal clock resource of described fpga chip and its reception is carried out that sheet internal classification frequency division is handled, after the shaping, output
(c) clock AD_CLK gives A/D converter (62) as A/D converter (62) sampled clock signal; With
(d) provide the timing control signal that mates with described optical fibre gyro integrated mode for center processor (63).
The frequency divider of described optical fibre gyro, its optical fibre gyro integrated mode have single axis fiber gyro, double-shaft optical fiber gyroscope combination and three axis optical fibre gyro combination.
The advantage of optical fibre gyro frequency divider of the present invention is: (1) finishes timing sequence generating and digital signal processing in a slice FPGA, simplified hardware design, manufacturing cost, area and the power consumption of testing circuit have been reduced, and by means of with the supporting zero propagation special clock line of digital dock manager, can improve the reliability and the speed of testing circuit, help the testing circuit miniaturization, especially three axis optical fibre gyro is made up; (2) adopt and in a slice FPGA, to finish sequential control and reduced the interference of high frequency clock signal faint simulating signal; (3) according to fpga chip internal clock manager resource quantity and the optical fibre gyro accuracy requirement chosen, can provide best sequential organization, carry out the monitoring and the clock control of clock running status simultaneously very easily by the divide ratio generator; (4) crystal oscillator frequency by crystal oscillator output and divide ratio generator provide the frequency division that best sequential organization can any configuration goes out the different fiber gyro, and adaptability is strong.
Description of drawings
Fig. 1 is the structured flowchart of conventional fiber gyro.
Fig. 2 is the structured flowchart of normal signal treating apparatus.
Fig. 3 is the structure diagram of divide ratio generator of the present invention.
Fig. 4 is the frequency division logical diagram of three axis optical fibre gyro combination of the present invention.
Fig. 5 is the frequency division logical organization block diagram of single axis fiber gyro of the present invention.
Fig. 6 A is the fractional frequency division partial logic structured flowchart of three axis optical fibre gyro of the present invention.
Fig. 6 B is the integral frequency divisioil partial logic structured flowchart of three axis optical fibre gyro of the present invention.
Embodiment
The present invention is described in further detail below in conjunction with drawings and Examples.
The present invention is a kind of frequency divider that is applicable to optical fibre gyro, constitute by FPGA processor chips (mainly be the sheet internal clock resource of utilizing fpga chip in the present invention, this chip is chosen Viltex II, the Viltex II Pro family chip of Xilinx company), divide ratio generator and crystal oscillator; The crystal oscillator frequency Clk_in end of crystal oscillator output connects (referring to shown in Figure 3) with the clock input CLKIN end of FPGA processor, and the divide ratio generator is with the divide ratio M that produces
n, D
n, Z
nExport to the configuration file (realizing the configuration of associated documents) of FPGA, be kept at (do not have figure, this is common technology means) among the EPROM.The FPGA processor chips have superior clock resource, can be with the clock resource in its sheet according to required frequency splitting technology requirements, and refinement goes out a plurality of digital dock manager, triggers of realizing identical function that have.And the FPGA processor chips are main control chips (referring to shown in Figure 2) of the center processor of optical fibre gyro self, such frequency divider has utilized the resource of optical fibre gyro, reduced the manufacturing cost of optical fibre gyro effectively, also made the volume of optical fibre gyro obtain reducing to have created condition simultaneously.
Running parameter when described divide ratio generator is used to realize to (a) optical fibre gyro operate as normal that reads (sample frequency of eigenfrequency, A/D converter, wherein, the sample frequency of A/D converter obtains referring to the instructions of selected device; Eigenfrequency is to obtain by signal generator and oscilloscope measurement) and (b) performance parameter of fpga chip (number of digital dock manager, divide ratio scope, input and output frequency range, can obtain in the instructions referring to selected fpga chip), according to the parameter frequency division
(in the formula, f
pBe parameter frequency division, f
0Be the crystal frequency that crystal oscillator produces, M is the Clock Multiplier Factor of the digital dock manager in the FPGA sheet, and D is the divide ratio of the digital dock manager in the FPGA sheet, and n is a frequency division progression, and Z is the integral frequency divisioil coefficient, and S is a sampling number.) carry out the frequency division processing, obtain divide ratio M, D, Z; And to described divide ratio M, D, Z and optical fibre gyro integrated mode (the optical fibre gyro integrated mode has single axis fiber gyro, double-shaft optical fiber gyroscope, and three axis optical fibre gyro, according to the optical fibre gyro difference of selecting for use, its parameter that reads when work is also different) mate, and the divide ratio M after will mating
n, D
n, Z
nExport to the configuration file of FPGA, be kept among the EPROM; The divide ratio M that deposits among the EPROM
n, D
n, Z
nDuring according to the optical fibre gyro operate as normal, the mode of operation that the FPGA processor should be carried out is carried out sequential control.The hardware configuration of the digital dock manager of FPGA processor is the technology of FPGA processor manufacturer, do not belong to the content of patented claim of the present invention, and the present invention utilizes the sheet internal clock resource on the fpga chip to carry out the adaptive of divide ratio.
Divide ratio M after the coupling of described FPGA reception (a) divide ratio generator output
n, D
n, Z
n(b) crystal oscillator frequency of crystal oscillator output, and it is carried out sheet internal classification frequency division is handled, shaping.
In the present invention, when the optical fibre gyro of choosing is single axis fiber gyro, running parameter (the eigenfrequency f when the divide ratio generator that adopts in its frequency divider reads (a) single axis fiber gyro operate as normal
p, sample frequency, the eigenfrequency limits of error); (b) performance parameter of FPGA processor chips (number of digital dock manager, divide ratio scope, input and output frequency range); And according to the parameter frequency division
Carry out frequency division and handle, obtain divide ratio M, D, Z; And described divide ratio M, D, Z and single axis fiber gyro mated, and the divide ratio M after will mating
1, D
1, M
2, D
2, Z exports to FPGA; FPGA will receive the divide ratio M after the coupling of (a) divide ratio generator output
1, D
1, M
2, D
2, Z and (b) the crystal oscillator frequency Clk-in of crystal oscillator output, and it is carried out sheet internal classification frequency division is handled, shaping.Its sheet internal classification frequency division is handled, matching process is:
See also shown in Figure 5ly, first order fractional frequency division unit is made of digital dock manager A U1.Fractional frequency division unit, the second level is made of digital dock manager B U2, shift register A N1 and phase inverter A A1.The integral frequency divisioil unit is made of phase inverter B A2, phase inverter C A3, phase inverter D A4, trigger A B1, trigger B B2, trigger C B3, trigger D B4, and the sample frequency AD_CLK output of about 350m of the fiber lengths of its fiber optic loop 4 and A/D converter 62 is about 9M.The number of the required phase inverter in integral frequency divisioil unit, trigger is that centering low-precision optical fiber gyro such as fiber lengths adopt 1 phase inverter, 2 triggers at 100m～300m according to the sample frequency AD_CLK decision of the length of fiber optic loop 4 and A/D converter 62; 300m～500m adopts 2～3 phase inverters, 3～4 triggers.
After the single axis fiber gyro system powers on, the crystal oscillator frequency Clk-in conducting that the input end of clock CLKIN of digital dock manager A U1 and crystal oscillator produce, the global reset signal RESET conducting of reset terminal RST and single axis fiber gyro system, digital dock manager A U1 to the crystal oscillator frequency clk-in that receives according to first order fractional frequency division
Carry out exporting to shift register A N1, digital dock manager BU2 after frequency division is handled; When the output frequency end CLKFX of digital dock manager A U1 stablized, locking signal end LOCKED put height.Shift register A N1 delays time to the locking signal end LOCKED that receives, and (time-delay herein is first order fractional frequency division
16 times of output cycle) handle after phase inverter A A1 exports to digital dock manager B U2 (as the reset signal of digital dock manager B U2); The output frequency end CLKFX conducting of the input end of clock CLKIN of digital dock manager B U2 and digital dock manager A U1, the output terminal conducting of reset terminal RST and phase inverter A A1, the first order fractional frequency division CLKFX of digital dock manager B U2 to receiving
U1Carry out second level fractional frequency division
Carry out exporting to after frequency division is handled the trigger A B1 and the trigger D B4 of integral frequency divisioil unit; Whether a plurality of phase inverters in the integral frequency divisioil unit, a plurality of trigger receive respectively by the clock gating end SWTCH that exports in the FPGA sheet, be used to determine the integral frequency divisioil unit to center processor 63 output timing control signals; Described trigger D B4 is used for the second level fractional frequency division CLKFX to receiving
U2Carry out exporting to after the clock shaping is handled the input end of clock AD_CLK of A/D converter 62.The second level fractional frequency division CLKFX of trigger A B1 to receiving
U2Two divided-frequency information B1 gives trigger B B2 to carry out exporting for the first time after the first time, two divided-frequency was handled, trigger B B2 carries out exporting for the second time after the second time, two divided-frequency was handled to the two divided-frequency information B1 first time that receives, and two divided-frequency information B2 gives trigger C B3, trigger C B3 carries out exporting for the third time after two divided-frequency is handled for the third time to the two divided-frequency information B2 second time that receives, and two divided-frequency information B3 gives trigger D B4, trigger D B4 provides timing control signal for center processor 63 (adopting FPGA processor chips in the present invention as center processor) simultaneously to the input end of clock AD_CLK that the information of the two divided-frequency for the third time B3 that receives carries out exporting to after shaping is handled A/D converter 62.
Frequency division workflow for single axis fiber gyro is: after the optical fibre gyro light path assembles, obtain eigenfrequency by signal generator and oscilloscope measurement, and will record eigenfrequency and be input to foundation in the divide ratio generator (actual is a software to be installed on the known computer realize)
After carrying out the processing of two-stage fractional frequency division and multistage integral frequency divisioil, the output frequency division coefficient is given among the EPROM of FPGA and is stored.Then, when single axis fiber gyro works on power, the divide ratio that utilization is stored among the EPROM triggers the sequential of unit (first order fractional frequency division unit, fractional frequency division unit, the second level and integral frequency divisioil unit) generation control FPGA in the different sheets, thereby realizes the frequency division of single axis fiber gyro.
The frequency division of the single axis fiber gyro among the present invention, wherein, U1, U2, A1, A2, A3, A4, B1, B2, B3, B4 and N1 are the basic logic units in the fpga chip.U1 and U2 are the digital dock manager, be responsible for finishing the fractional frequency division from " Clk_in " to " CLK_NET ", divide ratio is calculated by the hardware configuration (fpga chip, crystal oscillator) of supporting divide ratio generator according to the optical fibre gyro characteristic frequency of measuring and the present invention's employing; N1 is a shift register, is used for finishing after the U1 output frequency is stable reliably U2 being resetted; B is a trigger, is used for finishing 2 integral multiple frequency division to " CLK_NET ", and output is needed A/D sampling clock frequency, equals the optical fibre gyro characteristic frequency and multiply by periodic sampling and count.
See also shown in Figure 4ly, this is the frequency division logical diagram of three axis optical fibre gyro combination.Adopt three shared frequency unit forms for first order fractional frequency division, second level fractional frequency division and integral frequency divisioil adopt each independent dividing method to finish.
See also shown in Fig. 6 A, Fig. 6 B, this is the frequency division logical organization block diagram of a three axis optical fibre gyro combination.First order fractional frequency division unit is made of digital dock manager C U11.Fractional frequency division unit, the second level is made of digital dock manager D U12, digital dock manager E U13, digital dock manager F U14, shift register BN11 and phase inverter E A11.The integral frequency divisioil unit comprises X-axis frequency unit, Y-axis frequency unit, Z axle frequency unit, wherein, the X-axis frequency unit is made of phase inverter F A12, phase inverter G A13, phase inverter H A14, trigger E B11, trigger F B12, trigger G B13, trigger H B14; Y-axis frequency unit phase inverter I A22, phase inverter J A23, phase inverter K A24, trigger I B21, trigger J B22, trigger K B23, trigger L B24 constitute; Z axle frequency unit by phase inverter L A32, phase inverter M A33, phase inverter N A34, trigger M B31, trigger N B32, trigger O B33, trigger P B34, constitute, the about 350m of fiber lengths of the fiber optic loop 4 on its each and the sample frequency AD_CLK output of A/D converter 62 are about 9M.The number of the required phase inverter in integral frequency divisioil unit, trigger is that centering low-precision optical fiber gyro such as fiber lengths adopt 1 phase inverter, 2 triggers at 100m～300m according to the sample frequency AD_CLK decision of the length of fiber optic loop 4 and A/D converter 62; 300m～500m adopts 2～3 phase inverters, 3～4 triggers.
After the three axis optical fibre gyro combined system powers on, the crystal oscillator frequency Clk-in conducting that the input end of clock CLKIN of digital dock manager C U11 and crystal oscillator produce, the global reset signal RESET conducting of reset terminal RST and three axis optical fibre gyro combined system, digital dock manager C U11 to the crystal oscillator frequency Clk-in that receives according to first order fractional frequency division
Carry out exporting to shift register B N11, digital dock manager D U12 (X-axis), digital dock manager E U13 (Y-axis), digital dock manager F U14 (Z axle) respectively after frequency division is handled; When the output frequency end CLKFX of digital dock manager C U11 stablized, locking signal end LOCKED put height.Shift register B N11 delays time to the locking signal end LOCKED that receives, and (time-delay herein is first order fractional frequency division
16 times of output cycle) handle after phase inverter E A11 exports to digital dock manager D U12, digital dock manager E U13, digital dock manager F U14 (as the reset signal of digital dock manager D U12, digital dock manager E U13, digital dock manager F U14) respectively; The first order fractional frequency division CLKFX of digital dock manager D U12 to receiving
U1Carry out second level fractional frequency division
After carrying out the frequency division processing, export to the trigger E B11 and the trigger H B14 of integral frequency divisioil unit; Whether a plurality of phase inverters in the integral frequency divisioil unit, a plurality of trigger receive respectively by the clock gating end SWTCH that exports in the FPGA sheet, be used to determine the integral frequency divisioil unit to center processor 63 output timing control signals; The second level fractional frequency division CLKFX of trigger E B11 to receiving
U2XCarry out exporting two divided-frequency information B for the first time after the first time, two divided-frequency was handled
11Give trigger F B12, the first time two divided-frequency information B of trigger F B12 to receiving
11Carry out exporting two divided-frequency information B for the second time after the second time, two divided-frequency was handled
12Give trigger G B13, the second time two divided-frequency information B of trigger G B13 to receiving
12Carry out exporting two divided-frequency information B for the third time after the two divided-frequency processing for the third time
13Give trigger H B14; Trigger H B14 utilizes the second level fractional frequency division CLKFX that receives
U2XTo the information of the two divided-frequency for the third time B that receives
13After carrying out the shaping processing, export to the input end of clock AD_CLK of A/D converter 62,, provide the timing control signal of X-axis simultaneously for center processor 63 as the sampled clock signal of A/D converter 62.This is the integral frequency divisioil process of the X-axis in the three axis optical fibre gyro combined system, and the integral frequency divisioil of other Y-axis and Z axle is identical.
The first order fractional frequency division CLKFX of digital dock manager E U13 to receiving
U1Carry out second level fractional frequency division
Carry out exporting to after frequency division is handled the trigger I B21 and the trigger L B24 of integral frequency divisioil unit;
The first order fractional frequency division CLKFX of digital dock manager F U14 to receiving
U1Carry out second level fractional frequency division
Carry out exporting to after frequency division is handled the trigger M B31 and the trigger P B34 of integral frequency divisioil unit;
(shown in Fig. 6 B) i.e. be the second level fractional frequency division CLKFX of (Y-axis integral frequency divisioil) trigger I B21 to receiving
U2YCarry out exporting two divided-frequency information B for the first time after the first time, two divided-frequency was handled
21Give trigger J B22, the first time two divided-frequency information B of trigger J B22 to receiving
21Carry out exporting two divided-frequency information B for the second time after the second time, two divided-frequency was handled
22Give trigger K B23, the second time two divided-frequency information B of trigger K B23 to receiving
22Carry out exporting two divided-frequency information B for the third time after the two divided-frequency processing for the third time
23Give trigger L B24, trigger L B24 utilizes the second level fractional frequency division CLKFX that receives
U2To the information of the two divided-frequency for the third time B that receives
23After carrying out the shaping processing, export to the input end of clock AD_CLK of A/D converter 62, provide the Y-axis timing control signal for center processor 63 simultaneously.The second level fractional frequency division CLKFX of (Z axle integral frequency divisioil) trigger M B31 to receiving
U2ZCarry out exporting two divided-frequency information B for the first time after the first time, two divided-frequency was handled
31Give trigger N B32, the first time two divided-frequency information B of trigger NF B32 to receiving
31Carry out exporting two divided-frequency information B for the second time after the second time, two divided-frequency was handled
32Give trigger O B33, the second time two divided-frequency information B of trigger O B33 to receiving
32Carry out exporting two divided-frequency information B for the third time after the two divided-frequency processing for the third time
32Give trigger P B34, trigger P B34 utilizes the second level fractional frequency division CLKFX that receives
U2ZAfter the information of the two divided-frequency for the third time B33 that receives carried out shaping and handle, export to the input end of clock AD_CLK of A/D converter 62, provide Z axle timing control signal for center processor 63 simultaneously.
Frequency division workflow for the three axis optical fibre gyro combination is: after the optical fibre gyro light path assembles, obtain three eigenfrequency by signal generator and oscilloscope measurement, and will record eigenfrequency and be input to foundation in the divide ratio generator (actual is a software to be installed on the known computer realize)
After carrying out the processing of two-stage fractional frequency division and multistage integral frequency divisioil, the output frequency division coefficient is given among the EPROM of FPGA and is stored.Then, when the three axis optical fibre gyro combination works on power, the divide ratio that utilization is stored among the EPROM triggers the sequential of unit (first order fractional frequency division unit, fractional frequency division unit, the second level and integral frequency divisioil unit) generation control FPGA in the different sheets, thereby realizes the frequency division of three axis optical fibre gyro combination.
Be actually first order fractional frequency division unit to common for three axis optical fibre gyro combination, fractional frequency division unit, the second level and integral frequency divisioil unit then carry out frequency division according to each of gyro, thereby realize the frequency division that three axis optical fibre gyro makes up.
The present invention is applicable to the frequency divider of optical fibre gyro, is to utilize the outer crystal oscillating circuit of a field programmable logic array (FPLA) (FPGA) engagement tabs, finishes single shaft, twin shaft so that the frequency division work of three gyros.One of its advantage also is the frequency division that it is different from communication system, under the light path characteristic frequency situation that is not know in advance to be connected with it, approaches characteristic frequency with certain precision after assembling is finished, thereby guarantees the performance of optical fibre gyro.For the clock design, early stage optical fibre gyro is to use discrete phaselocked loop (PLL) to realize the fractional frequency division of specific crystal oscillator frequency to the fiber optic loop characteristic frequency.Use the built-in digital dock manager (DCM) of fpga chip not only can reduce cost, area and the power consumption of testing circuit, and by means of with the supporting zero propagation special clock line of DCM, can improve the reliability and the speed of testing circuit.
Claims (5)
1, a kind of frequency divider that is applicable to optical fibre gyro comprises the FPGA processor, it is characterized in that: also comprise divide ratio generator, crystal oscillator;
Described divide ratio generator is used to realize to reading
(a) running parameter during the optical fibre gyro operate as normal; With
(b) performance parameter of fpga chip;
According to the parameter frequency division
Carry out frequency division and handle, obtain divide ratio M, D, Z; And described divide ratio M, D, Z and optical fibre gyro integrated mode mated, and the divide ratio M after will mating
n, D
n, Z
nExport to the configuration file of FPGA, be kept among the EPROM;
In the formula, f
pBe parameter frequency division, f
oBe the frequency that crystal oscillator produces, M is the Clock Multiplier Factor of the digital dock manager in the FPGA sheet, and D is the divide ratio of the digital dock manager in the FPGA sheet, and n is a frequency division progression, and Z is the integral frequency divisioil coefficient, and S is a sampling number;
Described FPGA processor is used for receiving
(a) the divide ratio M after the coupling of described divide ratio generator output
n, D
n, Z
nWith
(b) crystal oscillator frequency of described crystal oscillator output;
And the information of utilizing the sheet internal clock resource of described fpga chip and its reception is carried out that sheet internal classification frequency division is handled, after the shaping, output
(c) clock AD_CLK gives A/D converter (62) as A/D converter (62) sampled clock signal; With
(d) provide the timing control signal that mates with described optical fibre gyro integrated mode for center processor (63).
2, the frequency divider of optical fibre gyro according to claim 1 is characterized in that: the sheet internal classification frequency division of the sheet internal clock resource of described FPGA processor and its reception information is,
The crystal oscillator frequency Clk-in conducting that the input end of clock CLKIN of digital dock manager C U11 and crystal oscillator produce, the global reset signal RESET conducting of reset terminal RST and three axis optical fibre gyro combination, digital dock manager C U11 to the crystal oscillator frequency clk-in that receives according to first order fractional frequency division
Carry out exporting to shift register B N11, digital dock manager D U12, digital dock manager E U13, digital dock manager F U14 respectively after frequency division is handled;
When the output frequency end CLKFX of digital dock manager C U11 stablized, locking signal end LOCKED put height;
Shift register B N11 carries out delay process after phase inverter EA11 exports to digital dock manager D U12, digital dock manager E U13, digital dock manager F U14 respectively to the locking signal end LOCKED that receives;
The first order fractional frequency division CLKFX of digital dock manager D U12 to receiving
U1Carry out second level fractional frequency division
Carry out exporting to after frequency division is handled the trigger E B11 and the trigger H B14 of integral frequency divisioil unit;
The second level fractional frequency division CLKFX of trigger E B11 to receiving
U2XCarry out exporting two divided-frequency information B for the first time after the first time, two divided-frequency was handled
11Give trigger F B12, the first time two divided-frequency information B of trigger F B12 to receiving
11Carry out exporting two divided-frequency information B for the second time after the second time, two divided-frequency was handled
12Give trigger G B13, the second time two divided-frequency information B of trigger G B13 to receiving
12Carry out exporting two divided-frequency information B for the third time after the two divided-frequency processing for the third time
13Give trigger H B14;
Trigger H B14 utilizes the second level fractional frequency division CLKFX that receives
U2XTo the information of the two divided-frequency for the third time B that receives
13After carrying out the shaping processing, export to the sampled clock signal of the input end of clock AD_CLK of A/D converter (62), provide timing control signal for center processor (63) simultaneously as A/D converter (62);
The first order fractional frequency division CLKFX of digital dock manager E U13 to receiving
U1Carry out second level fractional frequency division
Carry out exporting to after frequency division is handled the trigger I B21 and the trigger L B24 of integral frequency divisioil unit;
The second level fractional frequency division CLKFX of trigger I B21 to receiving
U2YCarry out exporting two divided-frequency information B for the first time after the first time, two divided-frequency was handled
21Give trigger J B22, the first time two divided-frequency information B of trigger J B22 to receiving
21Carry out exporting two divided-frequency information B for the second time after the second time, two divided-frequency was handled
22Give trigger K B23, the second time two divided-frequency information B of trigger K B23 to receiving
22Carry out exporting two divided-frequency information B for the third time after the two divided-frequency processing for the third time
23Give trigger L B24;
Trigger L B24 utilizes the second level fractional frequency division CLKFX that receives
U2To the information of the two divided-frequency for the third time B that receives
23After carrying out the shaping processing, export to the sampled clock signal of the input end of clock AD_CLK of A/D converter (62), provide timing control signal for center processor (63) simultaneously as A/D converter (62);
The first order fractional frequency division CLKFX of digital dock manager F U14 to receiving
U1Carry out second level fractional frequency division
Carry out exporting to after frequency division is handled the trigger M B31 and the trigger P B34 of integral frequency divisioil unit;
The second level fractional frequency division CLKFX of trigger M B31 to receiving
U2ZCarry out exporting two divided-frequency information B for the first time after the first time, two divided-frequency was handled
31Give trigger N B32, the first time two divided-frequency information B of trigger NF B32 to receiving
31Carry out exporting two divided-frequency information B for the second time after the second time, two divided-frequency was handled
32Give trigger O B33, the second time two divided-frequency information B of trigger OB33 to receiving
32Carry out exporting two divided-frequency information B for the third time after the two divided-frequency processing for the third time
33Give trigger P B34;
Trigger P B34 utilizes the second level fractional frequency division CLKFX that receives
U2ZTo the information of the two divided-frequency for the third time B that receives
33After carrying out the shaping processing, export to the sampled clock signal of the input end of clock AD_CLK of A/D converter (62), provide timing control signal for center processor (63) simultaneously as A/D converter (62).
3, the frequency divider of optical fibre gyro according to claim 1 is characterized in that: the optical fibre gyro integrated mode has single axis fiber gyro.
4, the frequency divider of optical fibre gyro according to claim 1 is characterized in that: the optical fibre gyro integrated mode has the double-shaft optical fiber gyroscope combination.
5, the frequency divider of optical fibre gyro according to claim 1 is characterized in that: the optical fibre gyro integrated mode has the three axis optical fibre gyro combination.
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101566475B (en) * | 2009-05-22 | 2011-08-03 | 东南大学 | Biaxial optical gyroscope |
| CN102253848A (en) * | 2011-05-31 | 2011-11-23 | 国营红峰机械厂 | Method for automatically generating fiber optic gyros with field programmable gate array (FPGA) logic in batches |
| CN109724582A (en) * | 2018-12-28 | 2019-05-07 | 北京航空航天大学 | A kind of method of the on-line automatic tracking of optical fiber gyroscope eigenfrequency |
| CN109974682A (en) * | 2019-03-21 | 2019-07-05 | 中国船舶重工集团公司第七0七研究所 | A kind of three axis optical fiber top modulation-demodulation device of microminiature |
| CN110849344A (en) * | 2019-11-21 | 2020-02-28 | 中国船舶重工集团公司第七0七研究所 | Precise frequency division method for triaxial fiber-optic gyroscope |
| CN111044081A (en) * | 2020-01-03 | 2020-04-21 | 中国船舶重工集团公司第七0七研究所 | Self-adaptive miniaturized optical fiber loop test system and test method |
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| JPH04270914A (en) * | 1991-02-27 | 1992-09-28 | Japan Aviation Electron Ind Ltd | Synchronous detector |
| CN100454786C (en) * | 2003-11-19 | 2009-01-21 | 华为技术有限公司 | Device and method for proceeding simulation to time delay |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101566475B (en) * | 2009-05-22 | 2011-08-03 | 东南大学 | Biaxial optical gyroscope |
| CN102253848A (en) * | 2011-05-31 | 2011-11-23 | 国营红峰机械厂 | Method for automatically generating fiber optic gyros with field programmable gate array (FPGA) logic in batches |
| CN102253848B (en) * | 2011-05-31 | 2013-09-25 | 湖北三江航天红峰控制有限公司 | Method for automatically generating fiber optic gyros with field programmable gate array (FPGA) logic in batches |
| CN109724582A (en) * | 2018-12-28 | 2019-05-07 | 北京航空航天大学 | A kind of method of the on-line automatic tracking of optical fiber gyroscope eigenfrequency |
| CN109974682A (en) * | 2019-03-21 | 2019-07-05 | 中国船舶重工集团公司第七0七研究所 | A kind of three axis optical fiber top modulation-demodulation device of microminiature |
| CN110849344A (en) * | 2019-11-21 | 2020-02-28 | 中国船舶重工集团公司第七0七研究所 | Precise frequency division method for triaxial fiber-optic gyroscope |
| CN111044081A (en) * | 2020-01-03 | 2020-04-21 | 中国船舶重工集团公司第七0七研究所 | Self-adaptive miniaturized optical fiber loop test system and test method |
| CN114104856A (en) * | 2021-12-28 | 2022-03-01 | 天津工业大学 | Machine vision-based yarn tension non-contact real-time detection control system and method |
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