CN1929137A - High density hybrid MOSFET device - Google Patents
High density hybrid MOSFET device Download PDFInfo
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- CN1929137A CN1929137A CN 200610127127 CN200610127127A CN1929137A CN 1929137 A CN1929137 A CN 1929137A CN 200610127127 CN200610127127 CN 200610127127 CN 200610127127 A CN200610127127 A CN 200610127127A CN 1929137 A CN1929137 A CN 1929137A
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- H—ELECTRICITY
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- H01L2924/01—Chemical elements
- H01L2924/01015—Phosphorus [P]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01074—Tungsten [W]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
Abstract
A hybrid semiconductor power device that includes a plurality of closed power transistor cells each surrounded by a first and second trenched gates constituting substantially a closed cell and a plurality of stripe cells comprising two substantially parallel trenched gates constituting substantially an elongated stripe cell wherein the closed cells and stripe cells constituting neighboring cells sharing trenched gates disposed thereinbetween as common boundary trenched gates. The closed MOSFET cell further includes a source contact disposed substantially at a center portion of the closed cell wherein the trenched gates are maintained a critical distance (CD) away from the source contact.
Description
Technical field
What the present invention was general involved is the unit structure of power semiconductor, device architecture and manufacturing process.Say thinlyyer, the present invention will introduce a kind of new improved unit structure, and device architecture and being used to is made by reducing the improved manufacture method that grid to the requirement of the contact critical dimension (CD) in source makes it to have the trench semiconductor power device of improved higher cell density.
Background technology
Since the increase of semiconductor power device cell density, some critical dimensions (CD), and for example, the distance between contact and the groove will become limiting factor.Particularly, the required distance between contact and groove should be able to prevent electrical short between grid and the source electrode.In a groove metal oxide semiconductor field effect transistor (MOSFET) unit, when using the non-self-align course of processing and make groove and contact with source electrode, an imbalance tolerance just must be provided, with guarantee trench-gate with can not come in contact between source electrode contacts.Yet, when the big distance between being applied in trench-gate and source electrode contacting when allowing contingent imbalance, the cell density of this semiconductor power device will be limited to 600,000,000 unit (600M/in per square inch
2) about.
More particularly, applicant has just been registered another application for patent 11/147,075 on June 6th, 2005, by reducing the source electrode contact distance so that cell density is improved.A kind of structure of improved MOSFET device has been shown in Figure 1A and Figure 1B, and wherein the distance between the source electrode contact is positioned within source electrode-matrix contact trench of leaving in oxide skin(coating) 35 by source electrode is contacted 45, and has obtained reducing.Shown in Figure 1B, this source electrode-matrix contact trench 45 stretches among matrix region 25, so both contacted source region 30 also contact matrix region 25 with provide improvement more reliable electrical contact.But, because the influence of imbalance is arranged, source matrix contact trench 45 is opened to such an extent that must have the minimum distance of critical dimension (CD) more than 40 with trench-gate 20, with electrically contacting of preventing to meet accident between this source electrode contact and grid 20.Like this, to the requirement of this minimum critical dimension (CD), just limited the size that further reduces the unit.Shown in Figure 1A and Figure 1B, even the distance between the source electrode contact of MOSFET device has been reduced, the density of unit still is limited in 600,000,000 unit (600M/in per square inch approx
2).Because this critical dimension requires the minimum range between maintenance source matrix contact trench 0 and the trench-gate 20, just be difficult to further increase cell density.
Therefore, in the manufacture craft of semiconductor device,, still need to provide a kind of new unit structure, device architecture and manufacture method can solve these difficult problems and design limitation particularly for design and the making of groove power MOSFET.Specifically, be desirably in exactly when can keep low resistance also and then can overcome above-described problem and difficulty, reach the cell density of further raising trench semiconductor power device with activation.
Summary of the invention
Therefore, one object of the present invention is exactly that a new improved semiconductor power device structure will be provided, for example, and a MOSFET device that includes mixed cell.These mixed cells are to realize with closed MOSFET unit and strip MOSFET unit, these closed MOSFET unit by the trench-gate that has the contact of groove source matrix round, matrix contact of this groove source then is placed in central authorities, with the requirement of the critical dimension that meets the minimum range between maintaining trench-gate and source electrode contacting.These strips MOSFET unit constitutes the unit that is elongated, and has trench-gate to stretch but not have the source electrode contact in the both sides of these unit, the conduction of current effect still is provided simultaneously, has increased cell density but also has reduced the resistance of source to drain electrode so that not only shown.Like this, those above-mentioned limitation, the mixed cell structure that discloses with the present invention promptly obtains solution.
Another aspect of the present invention is a combination that includes the MOSFET unit and the strip MOSFET unit of many closures, with the way that the source electrode contact plug is filled in source electrode-matrix contact trench, makes cell density increase to 2.5G/in simultaneously
2(2,500,000,000 unit per square inch), and drain electrode to the resistance in source approx by 0.4 ohm reduce 0.3 to ohm.
Another aspect of the present invention, then be by use a special matrix inject light shield stopped matrix impurity enter into constitute within the bar element further reduced resistance as the bar element of AccuFET (accumulation pattern field-effect transistor) unit.
In brief, in a recommended scheme, the present invention discloses mixed semiconductor's power device, this device comprises many closed power transistor cell, its each all by first and second trench-gate that in fact constitute a closed cell round; This device also comprise many actual be the bar element of two parallel trench-gates, and these two parallel grid actual sets have become a bar element that is elongated, wherein, closed cell and bar element have been formed the adjacent unit of shared trench-gate, and these trench-gates then are the trench-gates that is distributed in the shared border of conduct between them.In a recommended scheme, its closed MOSFET unit also comprises a source electrode contact that in fact is placed in this closed cell centre, wherein trench-gate therewith the source electrode contact keep the distance of a critical dimension (CD).In a recommended scheme, this source electrode contact is gone back and then is formed a groove source electrode that comprises the one source pole contact plug and contacts, this source electrode contact plug filling is in being covered with within source electrode-matrix contact trench of leaving in the insulating barrier of this closed cell one, and source region below this insulating barrier and one are within the matrix region that stretches under this source region between first and second trench-gate of this closed cell and this source-matrix contact trench stretches.In a recommended scheme, this semiconductor power device also comprises one and is placed in and is used for the drain electrode of transmission sources to drain current under the matrix region.In a recommended scheme, this semiconductor power device also comprises one and is placed in the source metal level on this insulating barrier and realizes electrically contacting with the source electrode contact plug.In a recommended scheme, this source electrode contact plug also comprises one round a barrier layer as the Ti/TiN of the tungsten core of source electrode-matrix contacting metal.In a recommended scheme, this semiconductor power device also comprises a thin resistance decrement conductive layer that is placed on the upper face, it is covered with this insulating barrier and is contacted with this source electrode contact plug, this resistance decrement conductive layer is had than the top surface of this contacting metal plug also want bigger area, to reduce the resistance of source electrode-matrix.In a recommended scheme, this mixed semiconductor's power device also comprises a N-channel mosfet unit.In a recommended scheme, this mixed semiconductor's power device also comprises a P-channel mosfet unit.In a recommended scheme, this bar element also comprises a strip AccuFET unit.
The present invention goes back and then discloses a method of making a kind of mixed semiconductor power device, this method comprises a step: the power transistor cell that constitutes many closures, a closed cell is formed in its each unit in fact by first and second trench-gate round, and constitute many bar elements that comprise two virtually parallel trench-gates, in fact these two virtually parallel trench-gates form a bar element that is elongated, and those closed cells wherein and bar element are made into shared those and are distributed in their adjacent units as the common boundary trench-gate each other.This method also comprises a step: in fact a source electrode contact is placed in the centre of this closed cell, and makes trench-gate contact the distance that keeps a critical dimension (CD) with this source electrode.In a recommended scheme, also comprise a step: in being covered with an insulating barrier of this closure semiconductor power device, leave a source electrode-matrix contact trench, in fact be placed in the centre of this closed cell with this source electrode contact, and this source electrode-matrix contact trench stretched in the source region and the matrix region under this source region below this insulating barrier, and in this source matrix contact trench filling with a source electrode contact plug.This method also comprises a step: settle a drain electrode to transmit from the source to the electric current of drain electrode under this matrix region.This method and then also comprise a step settles a source metal level and makes it to contact to be plugged with source electrode to electrically contact on this insulating barrier.In a recommended scheme, also and then comprise one with step round filling source, the barrier layer matrix contact trench of the Ti/TiN of a tungsten core with the step of this source matrix contact trench of source electrode contact plug filling.In a recommended scheme, this method also comprises a step, settle a thin resistance decrement conductive layer and contact this source electrode contact plug being covered with on the upper surface of this insulating barrier, this resistance decrement conductive layer has than the more bigger area of the upper surface of this contacting metal plug to reduce the resistance of source electrode-matrix thus.In a recommended scheme, also comprise a step, this mixed semiconductor's power device is made as the MOSFET unit of a N-raceway groove.In a recommended scheme, also comprise a step that this mixed semiconductor's power device is made as the MOSFET unit of a P-raceway groove.In a recommended scheme, also comprise a step that this bar element is made as a strip AccuFET unit.
Undoubtedly, these of this invention and some other purposes and advantage for those people that are familiar with general manufacture craft technology, after the detailed description of recommended scheme, will be perfectly clear below reading.In each is drawn, these recommended schemes have been done to specify.
Description of drawings
Figure 1A and Figure 1B be respectively, as the present patent application people disclosed in the related application book of one this invention, a vertical view and a viewgraph of cross-section of the relevant MOSFET cellular construction that distance between the source electrode contact is reduced.
Fig. 2 A and Fig. 2 B are respectively that the present invention is used to provide a vertical view and a viewgraph of cross-section that mixes the first string of MOSFET structure.
Fig. 3 is a chart, in order to expression and relatively MOSFET unit and a drain electrode that mixes MOSFET of the present invention of a closure to the resistance R ds in source measurement data to cell density.
Fig. 4 A is respectively in order to a vertical view and viewgraph of cross-section that mixes second scheme of MOSFET structure of the present invention to be provided with Fig. 4 B.
Fig. 5 A to Fig. 5 E is a series of side cross-sectional view of making MOSFET device fabrication step shown in Fig. 2 A to Fig. 2 B in order to explanation.
Fig. 5 C ' is a side cross-sectional view, makes another procedure of processing that replaces Fig. 5 C as the shown MOSFET device of Fig. 4 A to Fig. 4 B in order to explanation.
Embodiment
For first recommended scheme of the present invention, see also Fig. 2 A to Fig. 2 B, wherein, a mos field effect transistor (MOSFET) device 100 is carried on and forms to such an extent that have on the substrate 105 of epitaxial loayer 110.This MOSFET device 100 comprises a trench-gate 120 that is placed among the groove, then is formed with gate insulator 115 on the wall of this groove.One is mixed with second kind of conductive type impurity, and for example the matrix region 125 of p type impurity stretches between these trench-gates 120.This P-matrix region 125 surrounds one and is mixed with first kind of conductive type impurity, for example, and the source region 130 of N+ impurity.This source region 130 is built near the upper surface of the epitaxial loayer of this trench-gate 120.The upper surface of the Semiconductor substrate on top, P matrix region 125 and the source region 130 of this trench-gate that stretches is capped with a unadulterated silex glass (NSG) and a boron-phosphorosilicate glass (BPSG) protective layer 135.Source metal level 140 and gate metal layer (not shown) are formed on the top of this protection insulating barrier 135.
In order to improve the contact of the source electrode of source region 130, polynary groove source electrode contacts one of all filling by the circumjacent tungsten plug 145 in Ti/TiN barrier layer.These contact trench are opened to such an extent that pass NSG and BPSG protective layer 135 to contact those source regions 130 and P-matrix 125.Then, on upper surface, form a low-resistance conductive layer (not shown) to contact this groove source electrode contact 145.Form a top contact layer 140 at this again above the source electrode contact 145.This top contact layer 140 is to use aluminium, aluminium-Cooper, and AlCuSi, or Ni/Ag, Al/NiAu, AlCu/NiAu, or AlCuSi/NiAu formation are to follow closely layer as wired nation.Between the wired nation in top nail layer 140 and contact plug 145 tops, groove source, generate a low resistance conductive layer (not shown), reduce resistance so that bigger electrical-contact area to be provided.
Avoid being limited to critical dimension (CD) between source electrode contact 145 and the trench-gate 120 for further improving cell density, this MOSFET device 100 will be implemented a kind of improved mixed cell structure newly.This MOSFET device comprises the MOSFET unit of mixing, and these unit comprise the MOSFET unit 150 and strip MOSFET unit 160 of many closures again.In fact this closed MOSFET unit is surrounded by trench-gate 120 on its four limit, and the structure of this unit actual be a rectangular elements, source electrode contact 145 distances to trench-gate 120 accord with the requirement of critical dimension (CD) therein.160 of those bar elements become the list structure that is elongated, and stretch between two trench-gates 120.All source electrode contacts 145 that are placed in those source electrodes-matrix contact trench all are placed in the position of leaving 120 1 critical dimensions of trench-gate (CD) distance, and simultaneously, cell density is improved.The channel length of per unit area increases to 2.6/ micron (500,000,000 closed cells per square inch that mixing with 2,500,000,000 bar elements) per square inch for closed cell by 2.2/ micron (500,000,000 closed cells per square inch).This drain electrode to the resistance R ds in source then because the increase of channel length and further reducing.
Fig. 3 is a chart, in order to explanation in the past closed MOSFET structure and the drain electrode that includes closed MOSFET and this MOSFET structure of mixing of the MOSFET of strip to the resistance in source measurement data to cell density.Very clear, the mixed structure of this invention can be issued to higher cell density having the condition of low drain electrode to the resistance R ds in source.This mixed cell structure can be compared cell density with the cell density that is about 600,000,000 per square inch, bring up to 2,500,000,000 numerical value per square inch.This drain electrode also has been reduced to 0.3 ohm by 0.4 ohm to the resistance R ds in source.The Rds that records shown in this chart to reduce with the above calculating recruitment of making channel length per square inch and increasing be consistent from analyzing.
Shown in Fig. 4 A and Fig. 4 B, be a multi-form MOSFET instantiation of realizing with another mixed cell structure of this invention.This mixes MOSFET device 100 ', except that different matrix region distributions is arranged, is similar to Fig. 2 A to the MOSFET shown in Fig. 2 B.In matrix impurity injection process, a matrix light shield 128 is placed in round the top of the trench-gate of bar element 160, so that under the source region within the bar element 160, just can not form the P-matrix region, so promptly constitute accumulation mode field-effect transistor (accuFET) unit of strip.This accuFET is accumulation mode MOSFET, because there is not the P-matrix between two trench regions, such MOSFET does not just have channel length and can say.The conducting path of N+ electric current is formed by positive multiple grid bias induction along trenched side-wall in accuFET.Conducting path resistance in this accuFET, the corresponding resistor than the MOSFET of the enhancement mode that the P-matrix region is arranged between two trench regions of routine approximately has been reduced to one of percentage.Conducting path in the MOSFET of enhancement mode is by the P-matrix along trenched side-wall in N type zone is formed by the induction of positive gate bias is inverted.The favourable part of AccuFET is, because the result of electric field blockage effect effect in the drain electrode-source bias voltage of counter-rotating can make resistance R ds reduce but can not show the drain electrode-source electrode reverse current that increases in narrow bar element area (less than 0.5 micron) greatly.The mixing AccuFET cellular construction of Pi Luing in the present invention, it has the source Metal Contact of the shared identical contact of indirect and adjacent mixing closed cell, and this point is to be different with the AccuFET of routine.Conventional AccuFET has the direct source electrode contact to this AccuFET, as disclosures that the worker did such as B.J.Baliga, can consult: " accumulation pattern field-effect transistor; New super connection resistance MOSFET " IEEE ElectronDevice Letters, Vol.13 No.8, Aug, 1992, PP.427 ~ 429.Therefore the present invention and then disclosed a kind of semiconductor power device, it comprises an accumulation pattern field-effect transistor (accuFET) unit, not having direct source electrode with above-mentioned AccuFET contacts, and with an adjacent unit, such as the semiconductor circuit of a semiconductor power transistor or other types, shared source electrode contact.
Fig. 5 A to Fig. 5 E is in order to a series of side cross-sectional view of explanation making as Fig. 2 A and the shown MOSFET device fabrication of Fig. 2 B step.In Fig. 5 A, used a groove light shield (not shown), among the epitaxial loayer on the substrate 205 210, leave polynary groove 208.In Fig. 5 B, carry out an oxidizing process and form an oxide skin(coating) that is covered with trench wall.With a sacrificial oxide with this groove oxidation, to remove in leaving the process of this groove by the silicon layer of plasma damage.Form an oxide skin(coating) 215 then, come this groove of filling and cover its upper surface, then mix impurity again with N+ along with depositing a polysilicon layer 220 again.This polysilicon layer 220 is etched back.In Fig. 5 C, this manufacturing process will be injected with the P-matrix with P-type impurity thereupon.With the method for heating P-matrix region 225 is diffused into epitaxial loayer 210 again.In Fig. 5 D, at first use a source light shield (not shown), the source that thereupon has N type impurity is injected.Spread this source region 230 with the method for heating again.Not doping oxide of deposition (NSG) layer and a BPSG (boron-phosphorosilicate glass) layer 240 on this upper face.In Fig. 5 E, use the contact light shield and carry out contact etching, leave source-matrix contact trench 245 with the oxide etching of passing 240 layers on BPSG and NSG layer, then again with silicon etching this contact openings open so that more penetrate with this source region 230 and this matrix region 225.So this MOSFET device just comprises one at first to be used and passes oxide skin(coating), the etching of BPSG and NSG layer and make it to have the source electrode-matrix contact trench of an oxide groove for example.These source matrix contact trench also comprise one and are following oxide etching applying silicon etching and the silicon trench that forms again.This oxide etching and silicon etching can be dry oxide and silicon etching, can control the critical dimension (CD) of this source-matrix contact trench preferably with this.Then, this source-matrix contact trench filling is with a Ti/TiN/W layer 245.Form a low resistance conductive layer 250 covers this oxide skin(coating) 240 and also contacts this source matrix contact layer 245 and reduce its contact resistance to increase the conduction of current area on top.The low resistance metal layer 250 that is deposited on upper face can be made of Ti/AlCu or Ti/TiN/AlCu, to guarantee to set up good electrical contact.Then, deposit a upper metal conductive layer that constitutes by Al/Cu, with metal etch this metal level is shaped to a source metal pad 260 thereupon.
At last, see also Fig. 5 C ', it is another method that forms the AccuFET cellular construction shown in Fig. 4 A and Fig. 4 B.P-matrix light shield 228 is used to cover the top area between those trench-gates 220.Thereby, only among the MOSFET unit of closure, just form P-matrix region 225, and in bar element, do not form, so just constituted in the AccuFET unit shown in Fig. 4 A and Fig. 4 B.
Although team's description that the present invention did is the scheme by present recommendation, can know that it is conditional should not be construed in this disclosure of doing.Those after disclosing, can make diversified modification and replacement to the worker of art technology consummation undoubtedly more than reading.Thereby can expect that below Fu Jia all claim should be interpreted as containing replacement and the modification that all that belongs to field of the present invention and meets spirit of the present invention.
Claims (32)
1. a mixed-metal oxides semiconductor field effect transistor (MOSFET) device, it comprises:
Form the MOSFET unit of first and second circumjacent closure of trench-gate of a rectangular elements by reality for one, and above-mentioned first and second trench-gate stretch further therefrom to being used to constitute parallel first of being actually of the adjacent MOSFET unit that is elongated and second trench-gate that quilt stretches.
2. among the MOSFET of claim 1 device:
The MOSFET unit of above-mentioned closure and then comprise a source electrode contact that in fact is placed in above-mentioned rectangle centre, wherein above-mentioned first and second trench-gate contact the distance of a critical dimension of maintenance (CD) to above-mentioned source electrode.
3. among the MOSFET of claim 2 device:
Above-mentioned source electrode contacts and then forms a groove source electrode that includes a source electrode contact stopper and contacts, this source electrode contact plug filling is within a source-matrix contact trench of leaving in the insulating barrier of the MOSFET unit that is being covered with above-mentioned closure, and above-mentioned source-matrix contact trench is further stretched source region under the above-mentioned insulating barrier and one within the matrix region that stretches under the above-mentioned source region between above-mentioned first of the MOSFET unit of above-mentioned closure and second trench-gate.
4. the MOSFET device of claim 2 and then comprise:
One is placed in and is used for the drain electrode of transmission sources to the electric current of drain electrode under the above-mentioned matrix region.
5. among the MOSFET of claim 1 device:
Above-mentioned bar element and then comprise the AccuFET unit of a strip.
6. the MOSFET device of claim 3 and then comprise:
A source metal level that is placed on the above-mentioned insulating barrier and is in electrical contact with above-mentioned source electrode contact plug.
7. among the MOSFET of claim 3 device:
This source electrode contacts stopper and then comprises one round a Ti/TiN barrier layer as the tungsten core of source-matrix contacting metal.
8. the MOSFET device of claim 3 and then comprise:
A thin resistance decrement conductive layer that is placed in upper face, be covered with above-mentioned insulating barrier and be contacted with above-mentioned source electrode contact stopper, make above-mentioned resistance decrement conductive layer have the bigger area of upper surface of more above-mentioned contact plug and can reduce source-matrix resistance with this.
9. among the MOSFET of claim 3 device:
It is columniform stopper that the above-mentioned source electrode contact stopper that is filled with in the matrix contact trench of described source comprises a reality.
10. the MOSFET device of claim 9 also comprises:
A thick outer metal layer that is placed in above the above-mentioned resistance decrement layer thinks that the nail encapsulation of wired or wireless nation provides a contact layer.
11. among the MOSFET of claim 8 device:
Described resistance decrement conductive layer comprises a titanium (Ti) layer.
12. among the MOSFET of claim 8 device:
Described resistance decrement conductive layer comprises a titanium nitride (Ti/TiN) layer.
13. among the MOSFET of claim 10 device:
Described outside thick metal layers comprises an aluminium lamination.
14. among the MOSFET of claim 10 device:
Described outside thick metal layers comprises an AlCu layer.
15. among the MOSFET of claim 10 device:
Described outside thick metal layers comprises an AlCuSi layer.
16. among the MOSFET of claim 10 device:
Described outside thick metal layers comprises an Al/NiAu layer.
17. among the MOSFET of claim 10 device:
Described outside thick metal layers comprises an AlCu/NiAu layer.
18. among the MOSFET of claim 10 device:
Described outside thick metal layers comprises an AlCuSi/NiAu layer.
19. among the MOSFET of claim 10 device:
Described outside thick metal layers comprises a NiAg layer.
20. among the MOSFET of claim 10 device:
Described outside thick metal layers comprises a NiAu layer.
21. among the MOSFET of claim 1 device:
Described MOSFET unit also comprises the MOSFET unit of a N-raceway groove.
22. among the MOSFET of claim 1 device:
Described MOSFET unit also comprises the MOSFET unit of a P-raceway groove.
23. mixed semiconductor's power device, it comprises:
In fact each polynary unit is all constituted the power transistor cell of first and second circumjacent closure of trench-gate of a closed cell, with a polynary bar element that comprises two virtually parallel trench-gates, and in fact this two parallel trench-gate constitutes a bar element that is elongated, above-mentioned within it closed cell and bar element constitute adjacent unit, and their shared these are placed between them trench-gate as the common boundary trench-gate.
24. among mixed semiconductor's power device of claim 23:
Above-mentioned closed MOSFET unit and then comprise an actual placement in the contact of the source electrode in above-mentioned closed cell centre, wherein said trench-gate contacts the distance of a critical dimension of maintenance (CD) with above-mentioned source electrode.
25. among mixed semiconductor's power device of claim 24:
Above-mentioned source electrode contacts and then constitutes a groove source electrode and contacts, it comprises the source electrode contact plug of a filling within a source electrode-matrix contact trench of leaving in the insulating barrier that is being covered with described closed cell, above-mentioned source-matrix contact trench and then stretch source region under above-mentioned insulating barrier and one within the matrix region under the above-mentioned source region, and this source region stretches between first and second trench-gate of above-mentioned closed cell.
26. mixed semiconductor's power device of claim 23 also comprises:
One is placed in and is used for the drain electrode of transmission sources to drain current under the above-mentioned matrix region.
27. mixed semiconductor's power device of claim 24 also comprises:
A source metal level that is placed on the above-mentioned insulating barrier and is in electrical contact with above-mentioned source electrode contact plug.
28. among mixed semiconductor's power device of claim 25:
This source electrode contact plug and then comprise one round Ti/TiN barrier layer as the tungsten core of source-matrix contacting metal.
29. mixed semiconductor's power device of claim 25 also comprises:
A thin resistance decrement conductive layer, it is placed in the upper face that is covered with above-mentioned insulating barrier and touches above-mentioned source electrode contact plug, make above-mentioned resistance decrement conductive layer have the more bigger area of upper surface of more above-mentioned contacting metal plug with this, and source-matrix resistance is reduced.
30. among mixed semiconductor's power device of claim 23:
Described mixed semiconductor power device and then comprise a N-channel mosfet unit.
31. among mixed semiconductor's power device of claim 23:
Described mixed semiconductor power device and then comprise a P-channel mosfet unit.
32. among mixed semiconductor's power device of claim 23:
Described bar element and then comprise a strip AccuFET unit.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US11/223,621 | 2005-09-11 | ||
| US11/223,621 US7592650B2 (en) | 2005-06-06 | 2005-09-11 | High density hybrid MOSFET device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1929137A true CN1929137A (en) | 2007-03-14 |
| CN1929137B CN1929137B (en) | 2011-06-15 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200610127127 Expired - Fee Related CN1929137B (en) | 2005-09-11 | 2006-09-07 | High density hybrid Metal-Oxide -Semiconductor Field Effect Transistor device |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN1929137B (en) |
| TW (1) | TW200711126A (en) |
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| CN102044567A (en) * | 2010-11-03 | 2011-05-04 | 无锡中星微电子有限公司 | MOS tube and layout design method thereof |
| CN101452936B (en) * | 2007-12-06 | 2011-12-14 | 上海华虹Nec电子有限公司 | Single source multiple leakage MOS device |
| WO2016124086A1 (en) * | 2015-02-02 | 2016-08-11 | 无锡华润上华半导体有限公司 | Lateral double-diffused field-effect transistor |
| CN108899318A (en) * | 2018-08-30 | 2018-11-27 | 无锡摩斯法特电子有限公司 | A kind of snakelike layouts and layout method increasing VDMOS gully density |
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| US7781832B2 (en) | 2008-05-28 | 2010-08-24 | Ptek Technology Co., Ltd. | Trench-type power MOS transistor and integrated circuit utilizing the same |
| TWI387105B (en) * | 2008-11-10 | 2013-02-21 | Anpec Electronics Corp | Semiconductor device for improving the peak induced voltage in switching converter |
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| US6049108A (en) * | 1995-06-02 | 2000-04-11 | Siliconix Incorporated | Trench-gated MOSFET with bidirectional voltage clamping |
| US6104049A (en) * | 1997-03-03 | 2000-08-15 | Symetrix Corporation | Ferroelectric memory with ferroelectric thin film having thickness of 90 nanometers or less, and method of making same |
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2005
- 2005-12-30 TW TW094147710A patent/TW200711126A/en unknown
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2006
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101452936B (en) * | 2007-12-06 | 2011-12-14 | 上海华虹Nec电子有限公司 | Single source multiple leakage MOS device |
| CN101727526A (en) * | 2009-12-23 | 2010-06-09 | 北京中星微电子有限公司 | Method and device for designing MOS tube layout and chip |
| CN102044567A (en) * | 2010-11-03 | 2011-05-04 | 无锡中星微电子有限公司 | MOS tube and layout design method thereof |
| WO2016124086A1 (en) * | 2015-02-02 | 2016-08-11 | 无锡华润上华半导体有限公司 | Lateral double-diffused field-effect transistor |
| CN108899318A (en) * | 2018-08-30 | 2018-11-27 | 无锡摩斯法特电子有限公司 | A kind of snakelike layouts and layout method increasing VDMOS gully density |
| CN108899318B (en) * | 2018-08-30 | 2024-01-26 | 无锡摩斯法特电子有限公司 | Serpentine layout structure and layout method for increasing VDMOS channel density |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1929137B (en) | 2011-06-15 |
| TW200711126A (en) | 2007-03-16 |
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