CN1928845A - Singlet debug interface protocol for on-chip system - Google Patents
Singlet debug interface protocol for on-chip system Download PDFInfo
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- CN1928845A CN1928845A CN 200510029542 CN200510029542A CN1928845A CN 1928845 A CN1928845 A CN 1928845A CN 200510029542 CN200510029542 CN 200510029542 CN 200510029542 A CN200510029542 A CN 200510029542A CN 1928845 A CN1928845 A CN 1928845A
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Abstract
The single-line debug interference protocol based on SOC comprises: packing target data for serialization; applying dual-way communication between the main controller and secondary controller just by single line. Wherein, in current IEEE1149.1 JTAG, it needs five signal lines. This invention can reduce cost for high-speed transmission.
Description
Technical field
The present invention relates to a kind of singlet debug interface protocol that is used for SOC (system on a chip) (SOC), belong to the large scale integrated circuit design technical field.
Background technology
Present SOC (system on a chip) generally adopts the debugging interface of JTAG agreement (international standard IEEE 1149.1) as micro-processor kernel, realize the JTAG agreement need take 5 signal wires (TCK, TMS, TDI, TDO, TnRST).These additional signals lines have increased the cost of chip manufacturing and encapsulation, and especially for the less chip of those number of pin, it is huger to cost impact.Therefore, a lot of low-cost SOC (system on a chip) products (as 8/16 8-digit microcontrollers) have been cancelled debugging interface.But this has caused chip debugging method scarcity again, thereby has increased the development difficulty of final products.
Summary of the invention
In order to overcome the shortcoming of existing debugging interface agreement, the present invention proposes a kind of new singlet debug interface protocol, use it can finish primary controller (debugger) and, and only need a signal wire from the two-way communication between the control device (debug circuit in the sheet).
Concrete technical scheme of the present invention is as follows:
The bus signals agreement:
Bus is used pull-up resistor, and when no signal, state is a high level.
Bit stream needs earlier through coding by before the bus transfer.
During coding, at first adopt the bit filling algorithm.Transmitting terminal must insert 1 bit 0 when transmitting 6 bits 1 continuously.Receiving end abandons back to back bit 0 automatically when receiving 6 bits 1.
Adopting non-return-to-zero to be inverted (Non-Return to Zero Inverted) algorithm encodes to the bit stream of doing after bit is filled.If transmitted bit is 0, then the signal on the bus is inverted, and promptly uprises level by low level, perhaps by high level step-down level; Transmitted bit is 1, and then the signal on the bus remains unchanged.The bit filling algorithm inserted 0, be exactly in fact on bus, to insert a skip signal.
Continuous 7 or 7 above cycles are high level on the bus, and the expression bus is in the free time.An end that is ready for sending data must wait for that bus after the free time, just can send data.
Continuous 15 or 15 above cycles are low level on the bus, the expression reset signal.Receive reset signal from the control device, should finish reset operation.
Fig. 1 has shown the circuit structure of bus
The composition of bag:
Bag is by sync byte, the type byte, and data field and check byte are formed.Transmit in order to make to wrap on the single order wire, whole bag must pass through serialization, and to each byte in wrapping, transmission lowest bit is earlier transmitted higher bit at last.
Sync byte is fixed as 0x80, as the sign of unwrapping the beginning.
The type byte-identifier bag type, comprising:
| Types value | The bag type | Explanation |
| 0x01 | Write order | The expression primary controller is to sending data from the control device, and data are included in the data field |
| 0x02 | Read command | The expression primary controller requires to read in data to sending request from the control device |
| 0x10 | Packet | Expression sends data from the control device to primary controller, is the response to read command |
| 0x80 | Response packet | Expression sends to primary controller from the control device and replys, and is the response to write order |
| Other | Keep | Be considered as erroneous packets, do not do and reply |
Data field is the carrier of bag, to dissimilar bags, different implications is arranged.
To write order, data field is exactly that primary controller is to the data that send from the control device.
To reading name, data field is 1 byte, and the maximum byte number that reads in that allows of expression subtracts 1.
To packet, data field is exactly the data that send to primary controller from the control device.
To response packet, data field is 1 byte, and 0x0 represents that write order completes successfully, and other is worth reservation.The verification of correctness that check byte is used to wrap.
The last byte of all bags all is a check byte, and it is used for the verification to type byte and data field.Adopt the Cyclic Redundancy Check algorithm, polynomial table is shown:
X
8+X
5+X
4+1
Shift register initial value in the CRC check device is complete 1, when last byte of data field by behind the checker, the value of shift register is exactly a check byte.
Fig. 2 has shown the structure of various bags.
After check byte sent and finishes, transmitting terminal must send 1 cycle high level, stops the driving to bus then, allows bus remain on high level.
Bag transmits agreement:
Have only when primary controller allows (after just receiving the write order or read command of primary controller) from the control device, just can drive bus, send data.If receive write order, then should on bus, begin to send response packet in the 8th to 15 cycle after the write order end from the control device.If receive read command, then should on bus, begin to send packet in the 8th to 15 cycle after the read command end from the control device.Should send packet according to the byte number of read command appointment from the control device, if data are not enough, can only send less data, in advance end data packet.
Primary controller need be to from control device transmission information the time, and first testbus state if continuous 7 cycles of bus are high level, then illustrates the bus free time, can send read write command.After write order is sent completely,, illustrate that then write order is successfully received from the control device,, then represent the write order failure if do not have low level to occur on 15 cycle internal buses if in 15 cycles, receive low level (beginning of response packet).After read command is sent completely,, illustrate that then read command is successfully received from the control device,, then represent the read command failure if do not receive that low level is arranged on the bus in 15 cycles if low level (beginning of packet) on 15 cycle internal buses, occurs.
Fig. 3 has shown that bag transmits the formation of agreement.
Claims (6)
1, a kind of singlet debug interface protocol is characterized in that using single communication line, and adopts non-return-to-zero to be inverted encryption algorithm and bit insertion algorithm, can finish primary controller and from the two-way communication between the control device.
2, single line debugging agreement according to claim 1 is characterized in that using the cyclic redundancy check (CRC) algorithm, and the data of transmission are carried out verification of correctness.
3, single line debugging agreement according to claim 1 is characterized in that using pull-up resistor, makes bus be in high level when not having driving.
4, single line debugging agreement according to claim 1 is characterized in that using above low level of continuous 15 cycles to represent reset signal.
5, single line debugging agreement according to claim 1 is characterized in that the transmission of data is finished in the mode of bag.
6, single line debugging agreement according to claim 5 is characterized in that wrapping and is made up of sync byte, type byte, data field and check byte.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200510029542 CN1928845A (en) | 2005-09-09 | 2005-09-09 | Singlet debug interface protocol for on-chip system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200510029542 CN1928845A (en) | 2005-09-09 | 2005-09-09 | Singlet debug interface protocol for on-chip system |
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| CN1928845A true CN1928845A (en) | 2007-03-14 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN 200510029542 Pending CN1928845A (en) | 2005-09-09 | 2005-09-09 | Singlet debug interface protocol for on-chip system |
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Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101339738B (en) * | 2008-07-21 | 2010-06-02 | 北京巨数数字技术开发有限公司 | Single line cascade chip for lamp point display |
| CN102571472A (en) * | 2010-12-27 | 2012-07-11 | 北京国睿中数科技股份有限公司 | Debugging system and method |
| CN102035690B (en) * | 2009-09-27 | 2014-03-12 | 中兴通讯股份有限公司 | Data transmission method and device based on system-level joint test action group interface |
| CN104572337A (en) * | 2015-01-26 | 2015-04-29 | 中国航天科技集团公司第九研究院第七七一研究所 | Inter-chip data transmission method |
| CN104899166A (en) * | 2014-03-05 | 2015-09-09 | 上海华虹集成电路有限责任公司 | CBUS data receiving device and CBUS data receiving method |
| CN107622010A (en) * | 2017-08-22 | 2018-01-23 | 上海爱矽半导体科技有限公司 | A kind of microcontroller single line detail programming interface arrangement and adjustment method |
| WO2018157431A1 (en) * | 2017-03-01 | 2018-09-07 | 华为技术有限公司 | Method and device for single-line communication |
| CN110851388A (en) * | 2019-11-08 | 2020-02-28 | 南京沁恒微电子股份有限公司 | Debugging system and debugging signal transmission method for RISC-V processor |
| CN116028391A (en) * | 2022-07-15 | 2023-04-28 | 荣耀终端有限公司 | Electronic device, peripheral device, and single-wire communication system |
-
2005
- 2005-09-09 CN CN 200510029542 patent/CN1928845A/en active Pending
Cited By (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101339738B (en) * | 2008-07-21 | 2010-06-02 | 北京巨数数字技术开发有限公司 | Single line cascade chip for lamp point display |
| CN102035690B (en) * | 2009-09-27 | 2014-03-12 | 中兴通讯股份有限公司 | Data transmission method and device based on system-level joint test action group interface |
| CN102571472A (en) * | 2010-12-27 | 2012-07-11 | 北京国睿中数科技股份有限公司 | Debugging system and method |
| CN104899166B (en) * | 2014-03-05 | 2018-04-27 | 上海华虹集成电路有限责任公司 | CBUS bus data receiving devices and method |
| CN104899166A (en) * | 2014-03-05 | 2015-09-09 | 上海华虹集成电路有限责任公司 | CBUS data receiving device and CBUS data receiving method |
| CN104572337A (en) * | 2015-01-26 | 2015-04-29 | 中国航天科技集团公司第九研究院第七七一研究所 | Inter-chip data transmission method |
| CN104572337B (en) * | 2015-01-26 | 2018-07-10 | 中国航天科技集团公司第九研究院第七七一研究所 | A kind of data transmission method of chip chamber |
| WO2018157431A1 (en) * | 2017-03-01 | 2018-09-07 | 华为技术有限公司 | Method and device for single-line communication |
| CN109564557A (en) * | 2017-03-01 | 2019-04-02 | 华为技术有限公司 | Single line communication method and apparatus |
| CN109564557B (en) * | 2017-03-01 | 2021-01-29 | 华为技术有限公司 | Single-wire communication method and equipment |
| CN107622010A (en) * | 2017-08-22 | 2018-01-23 | 上海爱矽半导体科技有限公司 | A kind of microcontroller single line detail programming interface arrangement and adjustment method |
| CN110851388A (en) * | 2019-11-08 | 2020-02-28 | 南京沁恒微电子股份有限公司 | Debugging system and debugging signal transmission method for RISC-V processor |
| CN110851388B (en) * | 2019-11-08 | 2024-05-10 | 南京沁恒微电子股份有限公司 | Debugging system and debugging signal transmission method for RISC-V processor |
| CN116028391A (en) * | 2022-07-15 | 2023-04-28 | 荣耀终端有限公司 | Electronic device, peripheral device, and single-wire communication system |
| CN116028391B (en) * | 2022-07-15 | 2024-03-22 | 荣耀终端有限公司 | Electronic device, peripheral device, and single-wire communication system |
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