CN104899166B - CBUS bus data receiving devices and method - Google Patents
CBUS bus data receiving devices and method Download PDFInfo
- Publication number
- CN104899166B CN104899166B CN201410077604.6A CN201410077604A CN104899166B CN 104899166 B CN104899166 B CN 104899166B CN 201410077604 A CN201410077604 A CN 201410077604A CN 104899166 B CN104899166 B CN 104899166B
- Authority
- CN
- China
- Prior art keywords
- cbus
- data
- module
- verification
- packet header
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Landscapes
- Small-Scale Networks (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Abstract
The invention discloses a kind of CBUS bus data receiving devices, including：One idle condition detection module, together pace pulse detection module, a packet header file detection module, a control bit detection module, a data reception module, one first correction verification module, one second correction verification module, one the 3rd correction verification module, a responder module.The invention also discloses a kind of CBUS bus datas method of reseptance.The present invention meets the transmission specification of CBUS buses in MHL agreements, can receive the data packet that sender sends.When the data packet received has the error of link layer checks position, the data packet can be abandoned, and system is returned to idle condition.The present invention is rapidly completed check bit error detection using the signal characteristic of CBUS buses, calculates a large amount of hardware logic resources of detection check position saving using hardware logic than general, improves error detection efficiency.
Description
Technical field
The present invention relates to a kind of CBUS (link controlling bus) bus data receiving device.The invention further relates to a kind of CBUS
Bus data method of reseptance.
Background technology
Widely using and deeply develop with smart mobile phone and HDTV, by information such as the video in mobile phone or pictures
Become main trend with HDTV Real-Time Sharing.MHL (Mobile High-Definition Link, mobile terminal high definition
Audio-visual standard interface) interface solves the smart mobile phone of user and HDTV is connected demand.
MHL interface includes MHL+, MHL-, CBUS, five signals of VBUS, GND.Wherein, MHL+, MHL- are a pair of of difference letters
Number, complete audio, video data transfer function；VBUS signals are power supply signals, and GND is earth signal, and CBUS signals are collection DDC
(Direct Digital Control direct data controls) passage and MHL sideband channels signal are completed in a signal wire
EDID (Extended Display Identification Data extension display identification numbers between all mobile phone terminals and receiving terminal
According to) information, HDCP (High-bandwidth Digital Content Protection high-bandwidth digital content protection technology)
Deng the alternating transmission of order.
CBUS is single-wire-protocol, its data packet format is as shown in Figure 2.
The coding form of CBUS uses two-way mark coding mode (BMC：Bi-phase Mark Coding), i.e., 1 by half
A high level and half of low level form a clock cycle, and 0 forms a clock cycle by same level.It is necessary between 1 and 0
There is saltus step.
Sync (synchronous head) pulse is by the low level and the high level of 0.5 clock cycle in 1.5 continuous clock cycles
The certain pulses of composition.Packet header is to determine that the bag order belongs to DDC orders or MHL sideband channel orders.Control bit shows subsequently
Data zone content is order or data.Data field storage is actual data content.Check bit is according to transmission or receives number
It is calculated according to wrapping.CBUS agreements regulation uses even parity check, i.e., the preceding 11bit (bit) of Sync pulses is removed in data packet,
There is odd number 1 in data, then check bit is 1；There is even number 1 in data, then check bit is 0.Response bits should be sent by recipient,
Show that current data packet normally receives.
For MHL interface, CBUS is most important signal wire, it needs to have transceiving data bag concurrently, completes order and passes
Transmission function, its protocol format is relative complex, is the emphasis of MHL interface hardware design.And generally carry the data packet of check bit
Check bit can be provided by software, but shortcoming is elapsed time expense, fast with hardware realization speed, but be wasted to a certain extent hard
Part resource.
The content of the invention
The technical problem to be solved in the present invention is to provide a kind of CBUS bus data receiving devices, CBUS buses can be realized
Received data packet and quick detection check position；For this reason, the present invention also provides a kind of CBUS bus datas method of reseptance.
In order to solve the above technical problems, the CBUS bus data receiving end devices of the present invention, including：
One idle condition detection module, when CBUS buses do not have transmission demand, makes system keep idle condition；
Together pace pulse detection module, is connected with the Idle state detection module, in an idle state, when detecting
When having the data transfer of reception in CBUS buses, whether detection wherein has satisfactory lock-out pulse；
One packet header file detection module, is connected with the lock-out pulse detection module, successfully be detected lock-out pulse
Afterwards, according to the data jump of reception rule, detect packet header file and the packet header file deposit detected received into packet header register,
To determine the order classification of the packet header file；
One control bit detection module, is connected with the packet header file detection module, after packet header file is detected, according to
The data jump rule of reception, detects control bit, and the control bit information detected is stored in and receives control register, to determine
The attribute of the packet header file, i.e. the packet header file are data packet or control bag；
One data reception module, is connected with the control bit detection module, is encoded according to BMC and receives data, and is stored in
Receive data register；
One first correction verification module, is connected with the data reception module and idle condition detection module, when check bit
Be worth for 1 when, into first verification status check；In the first verification status check, if in CBUS buses always in no signal
Edge is risen, then verification failure, system returns to idle condition；If signal rising edge, then into the 3rd verification state；
One second correction verification module, is connected with the data reception module and idle condition detection module, when check bit
Be worth for 0 when, into second verification status check；In the second verification status check, if occurring signal decline in CBUS buses
Edge, then verification failure, system return to idle condition；If no signal trailing edge always, the second verification status check success；
One the 3rd correction verification module, is connected with first correction verification module, carries out the 3rd verification status check；In the 3rd school
Test in status check, then verify failure if there is signal trailing edge, return to idle condition；If there is no signal in CBUS buses
Edge transition, then carry out reply process after 0.5 clock cycle；
One responder module, is connected with second correction verification module, the 3rd correction verification module and idle condition detection module, root
Being returned according to the command to answer correctly (ack) or negative response (nack) value of receiving terminal write-in response register in CBUS buses should
Answer signal.
The CBUS bus datas method of reseptance, includes the following steps：
Step 1, when not having transmission demand in CBUS buses, system is made to keep idle condition；
Step 2, in an idle state, when detecting the data transfer for having reception in CBUS buses, wherein whether detection
There is satisfactory lock-out pulse；
Step 3, after it successfully be detected lock-out pulse, according to the data jump of reception rule, detection packet header file simultaneously will
The packet header file deposit detected receives packet header register, to determine the order classification of the packet header file；
Step 4, after packet header file is detected, according to the data jump of reception rule, control bit is detected, and will detect
Control bit information deposit receive control register, with determine the packet header file attribute, i.e., the packet header file be data packet also
It is control bag；
Step 5, encoded according to BMC and receive data, and be stored in reception data register；When the value of check bit is 1, perform
Step 6；When the value of check bit is 0, step 7 is performed；
Step 6, into the first verification status check, if no signal rising edge always in CBUS buses, verification fails,
Return to step 1；If signal rising edge, then step 8 is performed；
Step 7, into the second verification status check；In the second verification status check, if believed in CBUS buses
Number trailing edge, then verification failure, return to step 1；If without trailing edge, the second verification status check success, holds signal always
Row step 9；
Step 8, the 3rd verification status check is carried out, failure is then verified if there is signal trailing edge, returns to idle condition；
If not having signal edge transition in CBUS buses, step 9 is performed after 0.5 clock cycle；
Step 9, the command to answer correctly (ack) of response register is write according to receiving terminal or negative response (nack) value exists
Answer signal is returned in CBUS buses.
The lock-out pulse, is the low level and the high level of 0.5 clock cycle in 1.5 continuous clock cycles.
The present invention meets the transmission specification of CBUS buses in MHL agreements, can receive the data packet that sender sends.Receiving
To data packet there is a situation where link layer checks position error when, the data packet can be abandoned, and system is returned to idle condition.
The present invention is rapidly completed check bit error detection using the signal characteristic of CBUS buses, and hardware logic meter is utilized than general
Calculate detection check position and save a large amount of hardware logic resources, improve error detection efficiency.
Brief description of the drawings
The present invention is described in further detail with embodiment below in conjunction with the accompanying drawings：
Fig. 1 is CBUS bus data receiving device structure diagrams；
Fig. 2 is CBUS bus data bag form schematic diagrams；
Fig. 3 is CBUS bus data method of reseptance flow charts.
Embodiment
It is shown in Figure 1, the CBUS bus datas receiving end device, including：One idle condition detection module, one is synchronous
Pulse detection module, a packet header file detection module, a control bit detection module, a data reception module, one first calibration mode
Block, one second correction verification module, one the 3rd correction verification module, a responder module.Fig. 3 is the CBUS bus datas method of reseptance flow
Figure.
With reference to Fig. 1,2, the CBUS bus data receiving devices and method are broadly divided into two large divisions, i.e. CBUS buses connect
Receiving end state machine design and the detection of CBUS bus datas.
The state machine design mode can be divided into following state：Idle state, lock-out pulse detection state, packet header file
Detect state, control bit detection state, data mode, the first verification state, the second verification state, the 3rd verification state, response state.
The CBUS bus datas detection realization focuses on detecting the hopping edge of signal (i.e. data) in CBUS buses.By
It is single-wire-protocol in CBUS buses, its data transfer meets BMC codings.According to the data jump edge of detection and signal transmission time
(being 0.5 clock cycle or 1 clock cycle) judges data value.
Based on CBUS bus data bag forms, when Idle state detects the data transfer of reception, into lock-out pulse
Detect state.Lock-out pulse is the low level and the high level of 0.5 clock cycle of 1.5 clock cycle.It successfully be detected synchronization
Enter file detection state in packet header after pulse, Idle state is returned to if lock-out pulse is detected not successfully.Packet header file detection state, is
According to the data jump of reception rule, packet header file is detected, to judge the command property of packet header file (order classification), and will inspection
The packet header file deposit measured receives packet header register.
The type of the packet header file, it is as shown in table 1 below.
Table 1
Control bit detects state, is the data jump rule according to reception, detects control bit, the control bit information table detected
It is data packet or control bag to have levied the packet header file, and the control bit information detected is stored in and receives control register.Control
The information of position is as shown in table 2 below.
| Control bit | Description |
| 0 | 8 information tables next show data packet |
| 1 | 8 information next represents control bag |
Table 2
Data state, is to be encoded to receive data according to BMC, and is stored in reception data register.
First verification state, the second verification state and the 3rd verification state constitute the even-odd check detection shape of CBUS bus receiving terminals
State；Complete the calculating of the check bit of data packet format.
Traditional even-odd check detection is by the way of software calculates write-in register, or is counted after hardware data step-by-step exclusive or
Draw, the characteristics of being encoded using CBUS bus Bs MC of the invention, in verification state by judging data jump along guarantee check results
Correctness.Since CBUS bus checks are using even parity check, according to the bit numbers of BMC encoding laws and data packet through pushing away
Managing can draw to draw a conclusion, i.e.,：Rear half of clock cycle of check bit must be high level, and preceding half of clock cycle is high level
Or low level can be obtained according to the principle of even parity check.
When the value of check bit is 1 (" when data bit and check bit intersection have trailing edge " i.e. shown in Fig. 3), enter
First verification state.When the value of check bit is 0 (" when data bit and check bit intersection are without trailing edge " i.e. shown in Fig. 3),
Then enter the second verification state.If the first verification state error, i.e., verify state no signal rising edge always, then explanation verification first
Failure, state machine jump to Idle state；There is signal rising edge in the first verification state, then complete verification into the 3rd verification state.
If the second verification state error, i.e., there is trailing edge in CBUS bus signals in the second verification state, then explanation verification
Failure, state machine jump to Idle state；State no signal rising edge always is verified second, then is verified successfully, state machine is transferred to should
Answer state and reply answer signal.
Ack the or nack values of receiving terminal write-in response register are returned to answer signal by response state in CBUS buses.
Using the designing scheme of the CBUS receiving terminals proposed by the present invention surveyed with quick self-checking, it can be achieved that CBUS data packets
Reception, and complete rapidly and efficiently check bit detection.
The present invention is described in detail above by embodiment, but these are not formed to the present invention's
Limitation.Without departing from the principles of the present invention, those skilled in the art can also make many modification and improvement, these
It should be regarded as protection scope of the present invention.
Claims (4)
- A kind of 1. CBUS bus data receiving devices, it is characterised in that including：One idle condition detection module, when CBUS buses do not have transmission demand, makes system keep idle condition；Together pace pulse detection module, is connected with the idle condition detection module, in an idle state, when detecting CBUS When having the data transfer of reception in bus, whether detection wherein has satisfactory lock-out pulse；One packet header file detection module, is connected with the lock-out pulse detection module, after it successfully be detected lock-out pulse, root According to the data jump rule of reception, detect packet header file and the packet header file deposit detected is received into packet header register, with true The order classification of the fixed packet header file；One control bit detection module, is connected with the packet header file detection module, after packet header file is detected, according to reception Data jump rule, detect control bit, and by the control bit information detected be stored in receive control register, with determine the bag The attribute of header file；One data reception module, is connected with the control bit detection module, is encoded according to BMC and receives data, and is stored in reception Data register；One first correction verification module, is connected with the data reception module and idle condition detection module, when the value of check bit is 1 When, into the first verification status check；In the first verification status check, if no signal rising edge always in CBUS buses, Then verification failure, system return to idle condition；If signal rising edge, then into the 3rd verification status check；One second correction verification module, is connected with the data reception module and idle condition detection module, when the value of check bit is 0 When, into the second verification status check；In the second verification status check, if occurring signal trailing edge in CBUS buses, Verification failure, system return to idle condition；If no signal trailing edge always, the second verification status check success；One the 3rd correction verification module, is connected with first correction verification module, carries out the 3rd verification status check, shape is verified the 3rd In state verification, failure is then verified if there is signal trailing edge, returns to idle condition；If there is no signal edge in CBUS buses Saltus step, then carry out reply process after 0.5 clock cycle；One responder module, is connected with second correction verification module, the 3rd correction verification module and idle condition detection module, according to connecing The command to answer correctly or negative response value of receiving end write-in response register return to answer signal in CBUS buses.
- 2. device as claimed in claim 1, it is characterised in that：The lock-out pulse is the low electricity in 1.5 continuous clock cycles The high level of gentle 0.5 clock cycle.
- 3. a kind of CBUS bus datas method of reseptance, it is characterised in that include the following steps：Step 1, when not having transmission demand in CBUS buses, system is made to keep idle condition；Step 2, in an idle state, when detecting the data transfer for having reception in CBUS buses, whether detection wherein has symbol Close desired lock-out pulse；Step 3, after it successfully be detected lock-out pulse, according to the data jump of reception rule, detect packet header file and will detect The packet header file deposit arrived receives packet header register, to determine the order classification of the packet header file；Step 4, after packet header file is detected, according to the data jump of reception rule, control bit, and the control that will be detected are detected Information deposit in position processed receives control register, and to determine the attribute of the packet header file, i.e. the packet header file is data packet or control System bag；Step 5, encoded according to BMC and receive data, and be stored in reception data register；When the value of check bit is 1, step is performed 6；When the value of check bit is 0, step 7 is performed；Step 6, into the first verification status check, if no signal rising edge always in CBUS buses, verification failure, returns Step 1；If signal rising edge, then step 8 is performed；Step 7, into the second verification status check；In the second verification status check, if occurred in CBUS buses under signal Edge drops, then verification failure, return to step 1；If no signal trailing edge always, the second verification status check success, performs step Rapid 9；Step 8, the 3rd verification status check is carried out, failure is then verified if there is signal trailing edge, returns to idle condition；If There is no signal edge transition in CBUS buses, then step 9 is performed after 0.5 clock cycle；Step 9, the command to answer correctly of response register is write according to receiving terminal or negative response value returns in CBUS buses Answer signal.
- 4. method as claimed in claim 3, it is characterised in that：The lock-out pulse is the low electricity in 1.5 continuous clock cycles The high level of gentle 0.5 clock cycle.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410077604.6A CN104899166B (en) | 2014-03-05 | 2014-03-05 | CBUS bus data receiving devices and method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410077604.6A CN104899166B (en) | 2014-03-05 | 2014-03-05 | CBUS bus data receiving devices and method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104899166A CN104899166A (en) | 2015-09-09 |
| CN104899166B true CN104899166B (en) | 2018-04-27 |
Family
ID=54031838
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410077604.6A Active CN104899166B (en) | 2014-03-05 | 2014-03-05 | CBUS bus data receiving devices and method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104899166B (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6310807B1 (en) * | 2000-10-06 | 2001-10-30 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor integrated circuit device including tester circuit for defective memory cell replacement |
| CN1928845A (en) * | 2005-09-09 | 2007-03-14 | 上海采微电子科技有限公司 | Singlet debug interface protocol for on-chip system |
| CN101911000A (en) * | 2008-01-04 | 2010-12-08 | 晶像股份有限公司 | Control bus for connection of electronic devices |
| CN101938453A (en) * | 2009-06-29 | 2011-01-05 | 中兴通讯股份有限公司 | Device and method for realizing data transmission between central processing unit and Ethernet |
-
2014
- 2014-03-05 CN CN201410077604.6A patent/CN104899166B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6310807B1 (en) * | 2000-10-06 | 2001-10-30 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor integrated circuit device including tester circuit for defective memory cell replacement |
| CN1928845A (en) * | 2005-09-09 | 2007-03-14 | 上海采微电子科技有限公司 | Singlet debug interface protocol for on-chip system |
| CN101911000A (en) * | 2008-01-04 | 2010-12-08 | 晶像股份有限公司 | Control bus for connection of electronic devices |
| CN101938453A (en) * | 2009-06-29 | 2011-01-05 | 中兴通讯股份有限公司 | Device and method for realizing data transmission between central processing unit and Ethernet |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104899166A (en) | 2015-09-09 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US11347580B2 (en) | Method of encoding data | |
| CN105068966B (en) | Serial ports automatic identifying method | |
| US9264740B2 (en) | Methods and apparatus for error rate estimation | |
| CN104239254B (en) | serial asynchronous communication data transmission method | |
| CN104714920A (en) | Baud rate self-adaptation signal receiving method | |
| CN107078931A (en) | By bus system from sender by the participant of the method for frame serial transmission at least one recipient and bus system | |
| CN109951366A (en) | A kind of Modbus RTU bus control unit and control method | |
| CN105491369B (en) | A kind of VR video data processing systems | |
| US11403251B2 (en) | Single-wire transmission method, chip and communication system | |
| CN114257772A (en) | Data transmission adjusting method and device, computer equipment and readable storage medium | |
| CN106201973A (en) | A kind of method and system of single wire serial communication interface | |
| CN104899166B (en) | CBUS bus data receiving devices and method | |
| CN201215974Y (en) | Communication interface without polarity | |
| CN107346997A (en) | A kind of data transmission method and terminal | |
| CN102932103B (en) | A kind of message transmission rate adaptive reception method based on digital transformer substation | |
| CN104144137B (en) | A kind of high speed LVDS serial synchronous communication controllers | |
| CN105005511A (en) | Serial communication data checking method | |
| CN105933244A (en) | Channel aligning de-skew device and method | |
| CN105897494A (en) | Testing method of network transmission rate | |
| CN102043683B (en) | Smart card and method for operating data in smart card memory | |
| CN205015660U (en) | Stage self -adaptation matching unit | |
| CN105406943A (en) | High-integrity coding method of 1553B bus | |
| CN104883286A (en) | BLVDS bus data transmitter based on FPGA | |
| CN103631740B (en) | The circuit of SD card adaptation transmitter byte-aligned in the spi mode | |
| US8254494B2 (en) | Method and device for implementing data transmission |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |