CN1921313A - Grid electrode control circuit of up-draw transistor for high-voltage input - Google Patents
Grid electrode control circuit of up-draw transistor for high-voltage input Download PDFInfo
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Abstract
The invention relates to a circuit with grid control circuit used to boost transistor. Wherein, the grid G of boost transistor is connected to the grid control circuit; the source S of boost transistor is connected to the power; the drain D of boost transistor is connected to the welding pad node; and the substrate B of boost transistor is connected to N well. The invention is characterized in that: when the high-voltage signal is functioned, the grid control circuit can control the grid bias voltage of boost transistor, to improve the reliability.
Description
The application's application number is dividing an application of 200310108419.0 applications for a patent for invention.
Technical field
The present invention refers to a kind of grid control circuit that pulls up transistor that is used for the high voltage input especially about a kind of grid control circuit that is used to pull up transistor.
Background technology
Fig. 1 has schematically shown a known circuit that pulls up transistor, in this circuit, the pull up transistor source terminal S of MPU1 and its substrate B of PMOS links together, be connected to power supply potential Vdd then, the gate terminal G of transistor MPU1 is connected to Vss, and the drain electrode end D of transistor MPU 1 is connected to the drain electrode end D of nmos pass transistor MN1, the substrate B of transistor MN1 is connected to Vss, the gate terminal G of transistor MN1 is connected to power supply potential Vdd, and the source terminal S of transistor MN1 is connected to weld pad PAD.In the circuit of Fig. 1, because the gate terminal G of nmos pass transistor MN1 is connected to power supply potential Vdd, so under normal condition, the current potential of weld pad node will be the source voltage of transistor MN1, therefore, weld pad voltage can be up to Vdd-Vtn.If this weld pad node is one of them input signal on the system circuit board, then can produce following problem.
(1) little noise tolerance limit:, then can reduce weld pad voltage according to this on power plane if noise is arranged.If weld pad voltage is the input critical voltage that is lower than on other wafers, then may the generation systems fault.
(2) leakage current: because weld pad voltage does not fully arrive power supply potential, so have leakage current in other wafers, this is because input signal can not make the PMOS transistor in other wafers end fully.
Therefore, in the circuit of Fig. 1, weld pad voltage can not fully rise and arrive the power supply potential current potential, so can cause the system failure because of little noise tolerance limit.
Fig. 2 has schematically shown another known circuit that pulls up transistor, in this circuit, on draw the source terminal S of PMOS transistor MPU 2 to be connected to power supply potential Vdd, the gate terminal G of transistor MPU 2 is connected to Vss, the substrate B of MPU 2 of pulling up transistor is connected to a N trap, and the drain electrode end D of the MPU 2 that pulls up transistor is connected to weld pad.
In the circuit of Fig. 2, can be also higher between weld pad and the voltage difference that is used between the gate terminal G of the MPU 2 that pulls up transistor of pullup resistor than gate oxide breakdown voltage and TDDB (time variable dielectric collapse) specification voltage.Therefore, in the circuit of Fig. 2, reliability issues can take place, for example TDDB.
In sum, when the high voltage signal is applied in weld pad,, then can produce reliability issues such as TDDB if people can not control the grid bias voltage that pulls up transistor, and owing to less noise tolerance limit causes the system failure.
Summary of the invention:
The objective of the invention is to overcome the problem such as little noise tolerance limit, leakage current and TDDB of the known circuit that pulls up transistor and a kind of grid control circuit that pulls up transistor that pullup resistor is used that is used for is provided, so that give the weld pad node with the Vdd current potential, and enough noise tolerance limits, remove reliability issues substantially.
According to the present invention, a kind of circuit that comprises a grid control circuit that is used to pull up transistor is provided, wherein, the gate terminal G that pulls up transistor is connected to grid control circuit, and the source terminal S that pulls up transistor is connected to power supply potential, and the drain electrode end D that pulls up transistor is connected to the weld pad node, and the substrate B that pulls up transistor is connected to a N trap, this circuit is characterised in that when the high voltage signal was applied in, this grid control circuit was used to control the grid bias voltage that pulls up transistor.
According to the present invention, a kind of grid control circuit that is used to pull up transistor is provided, it comprises two n passage MOSFETs and a p passage MOSFET.
According to the present invention, the grid control circuit that provides another kind to be used to pull up transistor, it uses multistage power supply.
According to the present invention, the grid control circuit that provides another kind to be used to pull up transistor, it comprises two nmos pass transistors and connects to constitute diode.
According to the present invention, the grid control circuit that provides another kind to be used to pull up transistor, its nmos pass transistor that comprises series connection more than two connects to constitute diode.
According to the present invention, the grid control circuit that provides another kind to be used to pull up transistor, it comprises two PMOS transistors and connects to constitute diode.
According to the present invention, the grid control circuit that provides another kind to be used to pull up transistor, its PMOS transistor that comprises series connection more than two connects to constitute diode.
According to the present invention, the grid control circuit that provides another kind to be used to pull up transistor, it comprises two passive resistors to form a voltage divider.
According to the present invention, the grid control circuit that provides another kind to be used to pull up transistor, it comprises two diodes to form a voltage divider.
According to the present invention, the grid control circuit that provides another kind to be used to pull up transistor, it comprises being connected in series as voltage divider of two groups of above diodes.
According to the present invention, the grid control circuit that provides another kind to be used to pull up transistor, it comprises a nmos pass transistor and a PMOS transistor to constitute a bias circuit.
According to the present invention, the grid control circuit that provides another kind to be used to pull up transistor, it comprises plural nmos pass transistor and plural PMOS transistor to constitute bias circuit.
According to the present invention, the grid control circuit that provides another kind to be used to pull up transistor, it comprises a nmos pass transistor and a PMOS transistor to constitute an inverter.
Description of drawings
For advantage, feature and other purposes that can further understand the present invention, attachedly now be described in more detail in down with graphic.
Fig. 1 has schematically shown the circuit diagram of a known circuit that pulls up transistor.
Fig. 2 has schematically shown the circuit diagram of another known circuit that pulls up transistor.
Fig. 3 has schematically shown the circuit diagram according to representative circuit of the present invention.
The grid control circuit that Fig. 4 has schematically shown Fig. 3 is the circuit diagram of an embodiment wherein.
Fig. 5 has schematically shown the circuit diagram of foundation another representative circuit of the present invention of using multistage power supply.
Fig. 6 has shown the schematic circuit diagram according to grid control circuit of the present invention.
Fig. 7 has shown the schematic circuit diagram according to another grid control circuit of the present invention.
Fig. 8 has shown the schematic circuit diagram according to another grid control circuit of the present invention.
Fig. 9 has shown the schematic circuit diagram according to another grid control circuit of the present invention.
Figure 10 has shown the schematic circuit diagram according to another grid control circuit of the present invention.
Figure 11 has shown the schematic circuit diagram according to another grid control circuit of the present invention.
Figure 12 has shown the schematic circuit diagram according to another grid control circuit of the present invention.
Figure 13 has shown the schematic circuit diagram according to another grid control circuit of the present invention.
Figure 14 has shown the schematic circuit diagram according to another grid control circuit of the present invention.
Figure 15 has shown the schematic circuit diagram according to another grid control circuit of the present invention.
Embodiment
Now will illustrate according to preferred embodiment of the present invention with reference to accompanying drawing hereinafter.
Fig. 3 has shown according to the schematic circuit diagram that comprises a grid control circuit that is used to pull up transistor of the present invention, in this circuit, the gate terminal G of MPU 3 of pulling up transistor is connected to grid control circuit 31, the source terminal S of transistor MPU 3 is connected to power supply potential Vdd, the drain electrode end D of transistor MPU 3 is connected to weld pad PAD node, and the substrate B of transistor MPU 3 is connected to a N trap.Being operating as when the high voltage signal is applied in of the circuit of Fig. 3, grid control circuit 31 is to be used for controlling the grid bias voltage of MPU 3 of pulling up transistor, that is to say, control the grid voltage of the MPU 3 that pulls up transistor by grid control circuit 31, and the well bias voltage Be Controlled of transistor MPU 3 is to remove the leakage current between weld pad and the power supply potential Vdd.
The grid control circuit that Fig. 4 has shown Fig. 3 is the illustrative circuitry of an embodiment wherein, in this circuit, grid control circuit 41 is made of two n passage MOSFET (MOS field-effect transistor) MN2 and MN3 and a p passage MOSFET MP1, wherein, the gate terminal G of transistor MN2 and MN3 is connected to Vdd (power supply), the drain electrode end D of transistor MN2 is connected to the gate terminal G of the MPU 4 that pulls up transistor, the drain electrode end D of the source terminal S of transistor MN2 and transistor MN3 links together, the source terminal S of transistor MN3 is connected to earthing potential GND, and the substrate B of transistor MN2 and MN3 also is connected to GND.Moreover, the gate terminal G of transistor MP1 is connected to Vdd, the source terminal S of transistor MP1 or drain electrode end D are connected to gate terminal G or the PAD node of the MPU 4 that pulls up transistor respectively, look closely the voltage of PAD and decide, and the change in voltage scope of PAD is to lie prostrate Vdd+ α from zero, and the substrate B of transistor MP1 is connected to a N trap.That is to say, when PAD voltage during less than Vdd+Vtp (Vtp is the conducting voltage of transistor MP1), transistor MP1 will end, the gate terminal G voltage of MPU 4 is zero so pull up transistor, and when PAD voltage during greater than Vdd+Vtp and less than Vdd+Vtp+ α, transistor MP1 will conducting, so the gate terminal G voltage of the MPU 4 that pulls up transistor equals PAD voltage.In addition, the source terminal S of transistor MPU 4 is connected to power supply potential, and the drain electrode end D of transistor MPU 4 is connected to the weld pad node, and the substrate B of transistor MPU 4 is connected to a N trap.
With reference to Fig. 4, because transistor MN2 and MN3 are the very little transistor of ratio of width and length compared to transistor MP1, so under normal state, transistor MP1 closes, at this moment, the grid voltage of transistor MPU 4 is via nmos pass transistor MN2 and MN3 and be connected to ground connection.But, if be applied in the PAD node than the also high voltage of Vdd+Vthp (Vthp is the critical voltage of transistor MP1), then the grid voltage of transistor MPU 4 will rise and arrives PAD voltage, and people can give suitable size of the grid voltage of transistor MPU 4 and suitable bias voltage.This circuit has been arranged, under normal state, PAD voltage can draw on fully, if and higher voltage is applied in weld pad, then the grid voltage of transistor MPU 4 will be situated between between PAD voltage and ground connection, therefore, the voltage difference between the grid voltage of PAD node and transistor MPU 4 is less than the gate oxide breakdown voltage.Though PAD voltage is higher than the restriction of reliability specification, because the grid voltage of transistor MPU 4 system equals the voltage potential of PAD node, so there is not reliability issues to take place.
Fig. 5 is another representative circuit of the present invention, its use multistage (multi-level) power supply, and in this case, wherein the power supply of one-level is connected directly to the gate terminal G that pulls up transistor.In the circuit of Fig. 5, the gate terminal G of MPU 5 of pulling up transistor is connected to VGC (it has the voltage potential between power supply and the ground connection), the source terminal S of transistor MPU 5 is connected to Vdd, the drain electrode end D of transistor MPU 5 is connected to the PAD node, and the substrate B of transistor MPU 5 is connected to the N trap.
Under normal state, the gate terminal G of MPU 5 is connected to VGC because pull up transistor, so PAD voltage can via on draw PMOS transistor MPU 5 and drawn on fully, and because the voltage difference between the grid voltage of PAD node and transistor MPU 5 is less than the gate oxide breakdown voltage, so there is not reliability issues to take place.
The embodiment of foundation grid control circuit of the present invention is described to Figure 15 below with reference to Fig. 6.
Fig. 6 has schematically shown according to grid control circuit of the present invention, wherein, uses two nmos pass transistors to constitute diode and connects.In the circuit of Fig. 6, grid control circuit 61 comprises two n passage MOSFETsMN4 and MN5, in this circuit, the gate terminal G of nmos pass transistor MN5 is connected with its drain electrode end D, and then be connected to Vdd, the gate terminal G of nmos pass transistor MN4 is connected to its drain electrode end D, and the source terminal S of the drain electrode end D of transistor MN4 and transistor MN5 is connected, and then be connected to the gate terminal G of the MPU 6 that pulls up transistor, the source terminal S of transistor MN4 is connected to GND, and the substrate B of transistor MN4 and MN5 also is connected to GND.In addition, the source terminal S of the MPU 6 that pulls up transistor is connected to power supply potential Vdd, and the drain electrode end D of transistor MPU 6 is connected to the PAD node, and the substrate B of transistor MPU 6 is connected to a N trap.
At this moment, the grid voltage that draws PMOS transistor MPU 6 on is between power supply and ground connection.With the explanation of Fig. 5 in the same manner, PAD voltage can be pulled to power supply potential fully, and because be less than the gate oxide breakdown voltage at grid voltage and the voltage difference between PAD voltage of transistor MPU 6, so there is not the reliability issues generation.
Fig. 7 has schematically shown according to another grid control circuit of the present invention, wherein, uses the nmos pass transistor of series connection more than two to constitute the diode connection.In the circuit of Fig. 7, grid control circuit 71 comprises four n passage MOSFETs MN6, MN7, MN8, and MN9, in this circuit, transistor MN6 and MN7 form one group of diode and connect, and the gate terminal G of transistor MN7 and its drain electrode end D link together, and then are connected to Vdd, the gate terminal G of transistor MN6 and its drain electrode end D link together, and then are connected to the source terminal S of transistor MN7.Simultaneously, transistor MN8 and MN9 form another group diode and connect, and the gate terminal G of transistor MN9 is connected to its drain electrode end D, the gate terminal G of transistor MN8 and its drain electrode end D link together, and then be connected to the source terminal S of transistor MN9, and the source terminal S of transistor MN8 is connected to GND.In addition, the drain electrode end D of the source terminal S of transistor MN6 and transistor MN9 is connected, and then is connected to the gate terminal G of the MPU 7 that pulls up transistor, and transistor MN6, MN7, and MN8, and the substrate B of MN9 is connected to GND together.
Moreover the source terminal S of the MPU 7 that pulls up transistor is connected to power supply potential Vdd, and the drain electrode end D of transistor MPU 7 is connected to PAD, and the substrate B of transistor MPU 7 is connected to a N trap.The operation of the circuit of Fig. 7 is identical with the operation of the circuit of Fig. 6, more than to draw the grid voltage of PMOS transistor MPU 7 be between power supply and ground connection.Similarly, PAD voltage can be pulled to power supply potential fully, and because be less than the gate oxide breakdown voltage at grid voltage and the voltage difference between PAD voltage of transistor MPU 7, so there is not the reliability issues generation.
Fig. 8 has schematically shown according to another grid control circuit of the present invention, wherein, uses the PMOS transistor to constitute diode and connects.In the circuit of Fig. 8, grid control circuit 81 comprises two p passage MOSFETsMP2 and MP3, in this circuit, the gate terminal G of transistor MP3 is connected to its drain electrode end D, and the source terminal S of transistor MP3 is connected to Vdd, the gate terminal G of transistor MP2 is connected to its drain electrode end D, and the drain electrode end D of the source terminal S of transistor MP2 and transistor MP3 is connected, and then be connected to the gate terminal G of the MPU8 that pulls up transistor, the drain electrode end D of transistor MP2 is connected to GND, and the substrate B of transistor MP2 and MP3 also is connected to Vdd together.
In addition, the source terminal S of the MPU 8 that pulls up transistor is connected to power supply potential Vdd, and the drain electrode end D of transistor MPU 8 is connected to PAD, and the substrate B of transistor MPU 8 is connected to a N trap.The operation of the circuit of Fig. 8 is identical with the operation of the circuit of Fig. 6, more than to draw the grid voltage of PMOS transistor MPU 8 be between power supply and ground connection.Similarly, PAD voltage can be pulled to power supply potential fully, and because be less than the gate oxide breakdown voltage at grid voltage and the voltage difference between PAD voltage of transistor MPU 8, so there is not the reliability issues generation.
Fig. 9 illustrates to show according to another grid control circuit of the present invention, wherein, uses the PMOS transistor of series connection more than two to constitute the diode connection.In the circuit of Fig. 9, grid control circuit 91 comprises four p passage MOSFETs MP4, MP5, MP6, and MP7 are in this circuit, transistor MP4 and MP5 form one group of diode and connect, and the gate terminal G of transistor MP4 and MP5 is connected to its drain electrode end D respectively, and the source terminal S of transistor MP5 is connected to Vdd, and the source terminal S of transistor MP4 is connected to the drain electrode end D of transistor MP5.Simultaneously, transistor MP6 and MP7 form another group diode and connect, and the gate terminal G of transistor MP6 and MP7 is connected to its drain electrode end D respectively, and the source terminal S of transistor MP6 is connected to the drain electrode end D of transistor MP7, and the drain electrode end D of transistor MP6 is connected to GND.In addition, the drain electrode end D of transistor MP4 is connected with the source terminal S of transistor MP7, and then is connected to the gate terminal G of the MPU 9 that pulls up transistor, and transistor MP4, MP5, and MP6, and the substrate B of MP7 is connected to Vdd together.
Moreover the source terminal S of the MPU 9 that pulls up transistor is connected to power supply potential Vdd, and the drain electrode end D of transistor MPU 9 is connected to PAD, and the substrate B of transistor MPU 9 is connected to a N trap.The operation of the circuit of Fig. 9 is identical with the operation of the circuit of Fig. 6, more than to draw the grid voltage of PMOS transistor MPU 9 be between power supply and ground connection.Similarly, PAD voltage can be pulled to power supply potential fully, and because be less than the gate oxide breakdown voltage at grid voltage and the voltage difference between PAD voltage of transistor MPU 9, so there is not the reliability issues generation.
Figure 10 has schematically shown according to another grid control circuit of the present invention, wherein, has used two passive resistors as voltage divider.In the circuit of Figure 10, grid control circuit 101 comprises two resistor R 1 and R2, wherein, first end of resistor R 1 is connected to Vdd, second end of resistor R 1 is connected with first end of resistor R 2, and then be connected to the gate terminal G of the MPU 10 that pulls up transistor, and second end of resistor R 2 is connected to GND.
In addition, the source terminal S of the MPU 10 that pulls up transistor is connected to power supply potential Vdd, and the drain electrode end D of transistor MPU 10 is connected to PAD, and the substrate B of transistor MPU 10 is connected to a N trap.The operation of the circuit of Figure 10 is identical with the operation of the circuit of Fig. 6, more than to draw the grid voltage of PMOS transistor MPU 10 be between power supply and ground connection.Similarly, PAD voltage can be pulled to power supply potential fully, and because be less than the gate oxide breakdown voltage at grid voltage and the voltage difference between PAD voltage of transistor MPU 10, so there is not the reliability issues generation.
Figure 11 has schematically shown according to another grid control circuit of the present invention, wherein, has used two diodes as voltage divider.In the circuit of Figure 11, grid control circuit 111 comprises two diode D1 and D2, wherein, the anode tap of diode D1 is connected to Vdd, the cathode terminal of diode D1 is connected with the anode tap of diode D2, and then be connected to the gate terminal G that draws PMOS transistor MPU 11, and the cathode terminal of diode D2 is connected to GND.
In addition, the source terminal S of the MPU 11 that pulls up transistor is connected to power supply potential Vdd, and the drain electrode end D of transistor MPU 11 is connected to PAD, and the substrate B of transistor MPU 11 is connected to a N trap.The operation of the circuit of Figure 11 is identical with the operation of the circuit of Fig. 6, more than to draw the grid voltage of PMOS transistor MPU 11 be between power supply and ground connection.Similarly, PAD voltage can be pulled to power supply potential fully, and because at the grid voltage of transistor MPU 11 and the voltage difference between PAD voltage less than the gate oxide breakdown voltage, so there is not the reliability issues generation.
Figure 12 has schematically shown according to another grid control circuit of the present invention, wherein, uses being connected in series as voltage divider of two groups of above diodes.In the circuit of Figure 12, grid control circuit 121 comprises four diode D3, D4, D5, and D6, in this circuit, diode D1 and D2 form first group of diode and are connected in series, and forming second group of diode, diode D3 and D4 be connected in series, and the anode tap of first group of diode that is connected in series is connected to Vdd, and the cathode terminal of first group of diode that is connected in series is connected with the anode tap of second group of diode that is connected in series, and then be connected to the gate terminal G that draws PMOS transistor MPU 12, and the cathode terminal of second group of diode that is connected in series is connected to GND.
In addition, the source terminal S of the MPU 12 that pulls up transistor is connected to power supply potential Vdd, and the drain electrode end D of transistor MPU 12 is connected to PAD, and the substrate B of transistor MPU 12 is connected to a N trap.The operation of the circuit of Figure 12 is identical with the operation of the circuit of Fig. 6, more than to draw the grid voltage of PMOS transistor MPU 12 be between power supply and ground connection.Similarly, PAD voltage can be pulled to power supply potential fully, and because at the grid voltage of transistor MPU 12 and the voltage difference between PAD voltage less than the gate oxide breakdown voltage, so there is not the reliability issues generation.
Figure 13 has schematically shown according to another grid control circuit of the present invention, wherein, has used a nmos pass transistor and a PMOS transistor to constitute bias circuit.In the circuit of Figure 13, grid control circuit 131 comprises a PMOS transistor MP8 and is connected to form diode with a nmos pass transistor MN10, in this circuit, the gate terminal G of PMOS transistor MP8 is connected with the gate terminal G of nmos pass transistor MN10, and then be connected to the gate terminal G that draws PMOS transistor MPU 13, the source terminal S of PMOS transistor MP8 and its substrate B link together, and then be connected to Vdd, the drain electrode end D of PMOS transistor MP8 is connected with the drain electrode end D of nmos pass transistor MN10, and then be connected to the gate terminal G that draws PMOS transistor MPU 13, and the source terminal S of nmos pass transistor MN10 and its substrate B link together, and then are connected to GND.
In addition, the source terminal S of the MPU 13 that pulls up transistor is connected to power supply potential Vdd, and the drain electrode end D of transistor MPU 13 is connected to PAD, and the substrate B of transistor MPU 13 is connected to a N trap.The operation of the circuit of Figure 13 is identical with the operation of the circuit of Fig. 6, more than to draw the grid voltage of PMOS transistor MPU 13 be between power supply and ground connection.Similarly, PAD voltage can be pulled to power supply potential fully, and because be less than the gate oxide breakdown voltage at grid voltage and the voltage difference between PAD voltage of transistor MPU 13, so there is not the reliability issues generation.
Figure 14 has schematically shown according to another grid control circuit of the present invention, wherein, has used plural nmos pass transistor and plural PMOS transistor to constitute bias circuit.In the circuit of Figure 14, grid control circuit 141 comprises two PMOS transistor MP9 and MP10 and two nmos pass transistor MN11 and MN12, in this circuit, PMOS transistor MP9 and MP10 form first group and are connected in series, and the substrate B of transistor MP9 and MP10 and the source terminal S of transistor MP9 link together, and then being connected to Vdd, the gate terminal G of transistor MP9 is connected to its drain electrode end D, and then is connected with the source terminal S of transistor MP10.Simultaneously, nmos pass transistor MN11 and MN12 form second group and are connected in series, and the substrate B of transistor MN11 and MN12 and the drain electrode end D of transistor MN12 link together, and then be connected to GND, the gate terminal G of transistor MN12 is connected to its source terminal S, and then is connected with the drain electrode end D of transistor MN11.Moreover, the gate terminal G of first group of transistor MP10 that is connected in series is connected with the gate terminal G of second group of transistor MN11 that is connected in series, and then be connected to the gate terminal G that draws PMOS transistor MPU 14, the drain electrode end D of first group of transistor MP10 that is connected in series is connected with the source terminal S of second group of transistor MN11 that is connected in series, and then is connected to the gate terminal G that draws PMOS transistor MPU 14.
In addition, the source terminal S of the MPU 14 that pulls up transistor is connected to power supply potential Vdd, and the drain electrode end D of transistor MPU 14 is connected to PAD, and the substrate B of transistor MPU 14 is connected to a N trap.The operation of the circuit of Figure 14 is identical with the operation of the circuit of Fig. 6, more than to draw the grid voltage of PMOS transistor MPU 14 be between power supply and ground connection.Similarly, PAD voltage can be pulled to power supply potential fully, and because be less than the gate oxide breakdown voltage at grid voltage and the voltage difference between PAD voltage of transistor MPU 14, so there is not the reliability issues generation.
Figure 15 has schematically shown according to another grid control circuit of the present invention, wherein, has used a nmos pass transistor and a PMOS transistor to constitute bias circuit.In the circuit of Figure 15, grid control circuit 151 comprises a PMOS transistor MP11 and a nmos pass transistor MN13, to form an inverter, in this circuit, the drain electrode end D of transistor MP11 and MN13 is connected to the gate terminal G of pullup resistor transistor MPU 15, the gate terminal G of transistor MP11 and MN13 is connected to Res_en, the source terminal S of transistor MP11 is connected to the drain electrode end D of pullup resistor transistor MPU 15, the source terminal S of transistor MN13 is connected to VGC, and the VGC employed wherein a kind of power supply that is native system and must be lower than the Vdd current potential, and the substrate B of transistor MN13 is connected to GND.
In addition, the source terminal S of the MPU 15 that pulls up transistor is connected to power supply potential Vdd, and the drain electrode end D of transistor MPU 15 is connected to PAD, and the substrate B of transistor MPU 15 is connected to a N trap.
The operation of the circuit of Figure 15 is as follows, if Res_en is input as logic " height ", then the gate terminal G of pullup resistor transistor MPU 15 is connected to VGC, its have power supply and ground connection between voltage potential, and the operation of the circuit of the operation of this circuit and Fig. 6 is identical, more than draw the grid voltage of PMOS transistor MPU 15 to tie up between power supply and the ground connection.Similarly, PAD voltage can be pulled to power supply potential fully, and because be less than the gate oxide breakdown voltage at grid voltage and the voltage difference between PAD voltage of transistor MPU 15, so there is not the reliability issues generation.If Res_en is input as logic " low ", the gate terminal G of the MPU 15 that then pulls up transistor is connected to power supply Vdd, and therefore, this MPU 15 that pulls up transistor is failure to actuate.
Therefore, control the grid voltage that pulls up transistor by the grid bias control circuit, the foundation grid control circuit that is used to pull up transistor of the present invention can solve the problems such as little noise tolerance limit, leakage current and TDDB of the known circuit that pulls up transistor, and removes reliability issues substantially.
So by the detailed description of aforementioned grid control circuit embodiment of the present invention as can be known, the invention provides a kind of grid control circuit that is used to pull up transistor of novelty, can improve the shortcoming of the known circuit that pulls up transistor effectively.
Claims (1)
1, a kind of circuit that comprises a grid control circuit that is used to pull up transistor, wherein, the gate terminal (G) of (MPU) of pulling up transistor is connected to grid control circuit, the source terminal that pulls up transistor (S) is connected to power supply potential (Vdd), the drain electrode end that pulls up transistor (D) is connected to weld pad (PAD) node, and the substrate that pulls up transistor (B) is connected to a N trap
It is characterized in that grid control circuit comprises:
The one n passage MOSFET (MN4) and the 2nd n passage MOSFET (MN5), connect to form one group of diode, wherein, the gate terminal (G) of the 2nd n passage MOSFET (MN5) is connected to its drain electrode end (D), and the drain electrode end (D) of the 2nd n passage MOSFET (MN5) is connected to power supply (Vdd), the gate terminal (G) of the one n passage MOSFET (MN4) is connected to its drain electrode end (D), and the source terminal (S) of the drain electrode end (D) of a n passage MOSFET (MN4) and the 2nd n passage MOSFET (MN5) is connected, and then be connected to the gate terminal (G) that pulls up transistor, the source terminal (S) of the one n passage MOSFET (MN4) is connected to earthing potential (GND), and the substrate (B) of a n passage MOSFET (MN4) and a n passage MOSFET (MN5) also is connected to earthing potential (GND).
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006100798214A CN100452654C (en) | 2003-11-05 | 2003-11-05 | Grid electrode control circuit of up-draw transistor for high-voltage input |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006100798214A CN100452654C (en) | 2003-11-05 | 2003-11-05 | Grid electrode control circuit of up-draw transistor for high-voltage input |
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|---|---|---|---|
| CNB2003101084190A Division CN1293703C (en) | 2003-11-05 | 2003-11-05 | Gate controlling circuit for raising transistor with nigh voltage input |
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| CN1921313A true CN1921313A (en) | 2007-02-28 |
| CN100452654C CN100452654C (en) | 2009-01-14 |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101686046A (en) * | 2008-09-28 | 2010-03-31 | 飞思卡尔半导体公司 | Method for driving new grid electrode of H-bridge circuit |
| CN106411311A (en) * | 2015-07-31 | 2017-02-15 | 旺宏电子股份有限公司 | Output circuit |
| CN112840567A (en) * | 2018-10-18 | 2021-05-25 | 日立安斯泰莫株式会社 | Control circuit and sensor device |
| CN114325483A (en) * | 2022-03-14 | 2022-04-12 | 广东省大湾区集成电路与系统应用研究院 | Open circuit and short circuit detection circuit and motor control circuit |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5381061A (en) * | 1993-03-02 | 1995-01-10 | National Semiconductor Corporation | Overvoltage tolerant output buffer circuit |
| JP2964971B2 (en) * | 1997-01-24 | 1999-10-18 | 日本電気株式会社 | Pull-up circuit and pull-down circuit |
| JP3400294B2 (en) * | 1997-04-25 | 2003-04-28 | 富士通株式会社 | Pull-up circuit and semiconductor device |
| US6545506B1 (en) * | 1999-03-12 | 2003-04-08 | Silable, Inc. | CMOS output driver that can tolerant a high input voltage |
-
2003
- 2003-11-05 CN CNB2006100798214A patent/CN100452654C/en not_active Expired - Lifetime
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101686046A (en) * | 2008-09-28 | 2010-03-31 | 飞思卡尔半导体公司 | Method for driving new grid electrode of H-bridge circuit |
| CN101686046B (en) * | 2008-09-28 | 2013-12-18 | 飞思卡尔半导体公司 | Method for driving new grid electrode of H-bridge circuit |
| CN106411311A (en) * | 2015-07-31 | 2017-02-15 | 旺宏电子股份有限公司 | Output circuit |
| CN106411311B (en) * | 2015-07-31 | 2019-10-01 | 旺宏电子股份有限公司 | Output circuit |
| CN112840567A (en) * | 2018-10-18 | 2021-05-25 | 日立安斯泰莫株式会社 | Control circuit and sensor device |
| CN114325483A (en) * | 2022-03-14 | 2022-04-12 | 广东省大湾区集成电路与系统应用研究院 | Open circuit and short circuit detection circuit and motor control circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| CN100452654C (en) | 2009-01-14 |
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